hw/a15mpcore.c

   1 /*
   2  * Cortex-A15MPCore internal peripheral emulation.
   3  *
   4  * Copyright (c) 2012 Linaro Limited.
   5  * Written by Peter Maydell.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "sysbus.h"
  22
  23 /* Configuration for arm_gic.c:
  24  * max number of CPUs, how to ID current CPU
  25  */
  26 #define NCPU 4
  27
  28 static inline int gic_get_current_cpu(void)
  29 {
  30   return cpu_single_env->cpu_index;
  31 }
  32
  33 #include "arm_gic.c"
  34
  35 /* A15MP private memory region.  */
  36
  37 typedef struct A15MPPrivState {
  38     gic_state gic;
  39     uint32_t num_cpu;
  40     uint32_t num_irq;
  41     MemoryRegion container;
  42 } A15MPPrivState;
  43
  44 static int a15mp_priv_init(SysBusDevice *dev)
  45 {
  46     A15MPPrivState *s = FROM_SYSBUSGIC(A15MPPrivState, dev);
  47
  48     if (s->num_cpu > NCPU) {
  49         hw_error("a15mp_priv_init: num-cpu may not be more than %d\n", NCPU);
  50     }
  51
  52     gic_init(&s->gic, s->num_cpu, s->num_irq);
  53
  54     /* Memory map (addresses are offsets from PERIPHBASE):
  55      *  0x0000-0x0fff -- reserved
  56      *  0x1000-0x1fff -- GIC Distributor
  57      *  0x2000-0x2fff -- GIC CPU interface
  58      *  0x4000-0x4fff -- GIC virtual interface control (not modelled)
  59      *  0x5000-0x5fff -- GIC virtual interface control (not modelled)
  60      *  0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
  61      */
  62     memory_region_init(&s->container, "a15mp-priv-container", 0x8000);
  63     memory_region_add_subregion(&s->container, 0x1000, &s->gic.iomem);
  64     memory_region_add_subregion(&s->container, 0x2000, &s->gic.cpuiomem[0]);
  65
  66     sysbus_init_mmio(dev, &s->container);
  67     return 0;
  68 }
  69
  70 static Property a15mp_priv_properties[] = {
  71     DEFINE_PROP_UINT32("num-cpu", A15MPPrivState, num_cpu, 1),
  72     /* The Cortex-A15MP may have anything from 0 to 224 external interrupt
  73      * IRQ lines (with another 32 internal). We default to 64+32, which
  74      * is the number provided by the Cortex-A15MP test chip in the
  75      * Versatile Express A15 development board.
  76      * Other boards may differ and should set this property appropriately.
  77      */
  78     DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 96),
  79     DEFINE_PROP_END_OF_LIST(),
  80 };
  81
  82 static void a15mp_priv_class_init(ObjectClass *klass, void *data)
  83 {
  84     DeviceClass *dc = DEVICE_CLASS(klass);
  85     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  86     k->init = a15mp_priv_init;
  87     dc->props = a15mp_priv_properties;
  88     /* We currently have no savable state outside the common GIC state */
  89 }
  90
  91 static TypeInfo a15mp_priv_info = {
  92     .name  = "a15mpcore_priv",
  93     .parent = TYPE_SYS_BUS_DEVICE,
  94     .instance_size  = sizeof(A15MPPrivState),
  95     .class_init = a15mp_priv_class_init,
  96 };
  97
  98 static void a15mp_register_types(void)
  99 {
 100     type_register_static(&a15mp_priv_info);
 101 }
 102
 103 type_init(a15mp_register_types)