hw/char/cadence_uart.c

   1 /*
   2  * Device model for Cadence UART
   3  *
   4  * Copyright (c) 2010 Xilinx Inc.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
   6  * Copyright (c) 2012 PetaLogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *            M.Habib
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version
  13  * 2 of the License, or (at your option) any later version.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "hw/sysbus.h"
  20 #include "sysemu/char.h"
  21 #include "qemu/timer.h"
  22
  23 #ifdef CADENCE_UART_ERR_DEBUG
  24 #define DB_PRINT(...) do { \
  25     fprintf(stderr,  ": %s: ", __func__); \
  26     fprintf(stderr, ## __VA_ARGS__); \
  27     } while (0);
  28 #else
  29     #define DB_PRINT(...)
  30 #endif
  31
  32 #define UART_SR_INTR_RTRIG     0x00000001
  33 #define UART_SR_INTR_REMPTY    0x00000002
  34 #define UART_SR_INTR_RFUL      0x00000004
  35 #define UART_SR_INTR_TEMPTY    0x00000008
  36 #define UART_SR_INTR_TFUL      0x00000010
  37 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
  38  * SR, then the same bit in CISR is set high too */
  39 #define UART_SR_TO_CISR_MASK   0x0000001F
  40
  41 #define UART_INTR_ROVR         0x00000020
  42 #define UART_INTR_FRAME        0x00000040
  43 #define UART_INTR_PARE         0x00000080
  44 #define UART_INTR_TIMEOUT      0x00000100
  45 #define UART_INTR_DMSI         0x00000200
  46
  47 #define UART_SR_RACTIVE    0x00000400
  48 #define UART_SR_TACTIVE    0x00000800
  49 #define UART_SR_FDELT      0x00001000
  50
  51 #define UART_CR_RXRST       0x00000001
  52 #define UART_CR_TXRST       0x00000002
  53 #define UART_CR_RX_EN       0x00000004
  54 #define UART_CR_RX_DIS      0x00000008
  55 #define UART_CR_TX_EN       0x00000010
  56 #define UART_CR_TX_DIS      0x00000020
  57 #define UART_CR_RST_TO      0x00000040
  58 #define UART_CR_STARTBRK    0x00000080
  59 #define UART_CR_STOPBRK     0x00000100
  60
  61 #define UART_MR_CLKS            0x00000001
  62 #define UART_MR_CHRL            0x00000006
  63 #define UART_MR_CHRL_SH         1
  64 #define UART_MR_PAR             0x00000038
  65 #define UART_MR_PAR_SH          3
  66 #define UART_MR_NBSTOP          0x000000C0
  67 #define UART_MR_NBSTOP_SH       6
  68 #define UART_MR_CHMODE          0x00000300
  69 #define UART_MR_CHMODE_SH       8
  70 #define UART_MR_UCLKEN          0x00000400
  71 #define UART_MR_IRMODE          0x00000800
  72
  73 #define UART_DATA_BITS_6       (0x3 << UART_MR_CHRL_SH)
  74 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
  75 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
  76 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
  77 #define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
  78 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
  79 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
  80 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)
  81 #define LOCAL_LOOPBACK         (0x2 << UART_MR_CHMODE_SH)
  82 #define REMOTE_LOOPBACK        (0x3 << UART_MR_CHMODE_SH)
  83
  84 #define RX_FIFO_SIZE           16
  85 #define TX_FIFO_SIZE           16
  86 #define UART_INPUT_CLK         50000000
  87
  88 #define R_CR       (0x00/4)
  89 #define R_MR       (0x04/4)
  90 #define R_IER      (0x08/4)
  91 #define R_IDR      (0x0C/4)
  92 #define R_IMR      (0x10/4)
  93 #define R_CISR     (0x14/4)
  94 #define R_BRGR     (0x18/4)
  95 #define R_RTOR     (0x1C/4)
  96 #define R_RTRIG    (0x20/4)
  97 #define R_MCR      (0x24/4)
  98 #define R_MSR      (0x28/4)
  99 #define R_SR       (0x2C/4)
 100 #define R_TX_RX    (0x30/4)
 101 #define R_BDIV     (0x34/4)
 102 #define R_FDEL     (0x38/4)
 103 #define R_PMIN     (0x3C/4)
 104 #define R_PWID     (0x40/4)
 105 #define R_TTRIG    (0x44/4)
 106
 107 #define R_MAX (R_TTRIG + 1)
 108
 109 #define TYPE_CADENCE_UART "cadence_uart"
 110 #define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
 111
 112 typedef struct {
 113     /*< private >*/
 114     SysBusDevice parent_obj;
 115     /*< public >*/
 116
 117     MemoryRegion iomem;
 118     uint32_t r[R_MAX];
 119     uint8_t rx_fifo[RX_FIFO_SIZE];
 120     uint32_t rx_wpos;
 121     uint32_t rx_count;
 122     uint64_t char_tx_time;
 123     CharDriverState *chr;
 124     qemu_irq irq;
 125     QEMUTimer *fifo_trigger_handle;
 126     QEMUTimer *tx_time_handle;
 127 } UartState;
 128
 129 static void uart_update_status(UartState *s)
 130 {
 131     s->r[R_SR] = 0;
 132
 133     s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
 134     s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
 135     s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
 136
 137     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
 138     s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
 139     qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
 140 }
 141
 142 static void fifo_trigger_update(void *opaque)
 143 {
 144     UartState *s = (UartState *)opaque;
 145
 146     s->r[R_CISR] |= UART_INTR_TIMEOUT;
 147
 148     uart_update_status(s);
 149 }
 150
 151 static void uart_tx_redo(UartState *s)
 152 {
 153     uint64_t new_tx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 154
 155     timer_mod(s->tx_time_handle, new_tx_time + s->char_tx_time);
 156
 157     s->r[R_SR] |= UART_SR_INTR_TEMPTY;
 158
 159     uart_update_status(s);
 160 }
 161
 162 static void uart_tx_write(void *opaque)
 163 {
 164     UartState *s = (UartState *)opaque;
 165
 166     uart_tx_redo(s);
 167 }
 168
 169 static void uart_rx_reset(UartState *s)
 170 {
 171     s->rx_wpos = 0;
 172     s->rx_count = 0;
 173     if (s->chr) {
 174         qemu_chr_accept_input(s->chr);
 175     }
 176 }
 177
 178 static void uart_tx_reset(UartState *s)
 179 {
 180 }
 181
 182 static void uart_send_breaks(UartState *s)
 183 {
 184     int break_enabled = 1;
 185
 186     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 187                                &break_enabled);
 188 }
 189
 190 static void uart_parameters_setup(UartState *s)
 191 {
 192     QEMUSerialSetParams ssp;
 193     unsigned int baud_rate, packet_size;
 194
 195     baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
 196             UART_INPUT_CLK / 8 : UART_INPUT_CLK;
 197
 198     ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
 199     packet_size = 1;
 200
 201     switch (s->r[R_MR] & UART_MR_PAR) {
 202     case UART_PARITY_EVEN:
 203         ssp.parity = 'E';
 204         packet_size++;
 205         break;
 206     case UART_PARITY_ODD:
 207         ssp.parity = 'O';
 208         packet_size++;
 209         break;
 210     default:
 211         ssp.parity = 'N';
 212         break;
 213     }
 214
 215     switch (s->r[R_MR] & UART_MR_CHRL) {
 216     case UART_DATA_BITS_6:
 217         ssp.data_bits = 6;
 218         break;
 219     case UART_DATA_BITS_7:
 220         ssp.data_bits = 7;
 221         break;
 222     default:
 223         ssp.data_bits = 8;
 224         break;
 225     }
 226
 227     switch (s->r[R_MR] & UART_MR_NBSTOP) {
 228     case UART_STOP_BITS_1:
 229         ssp.stop_bits = 1;
 230         break;
 231     default:
 232         ssp.stop_bits = 2;
 233         break;
 234     }
 235
 236     packet_size += ssp.data_bits + ssp.stop_bits;
 237     s->char_tx_time = (get_ticks_per_sec() / ssp.speed) * packet_size;
 238     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 239 }
 240
 241 static int uart_can_receive(void *opaque)
 242 {
 243     UartState *s = (UartState *)opaque;
 244
 245     return RX_FIFO_SIZE - s->rx_count;
 246 }
 247
 248 static void uart_ctrl_update(UartState *s)
 249 {
 250     if (s->r[R_CR] & UART_CR_TXRST) {
 251         uart_tx_reset(s);
 252     }
 253
 254     if (s->r[R_CR] & UART_CR_RXRST) {
 255         uart_rx_reset(s);
 256     }
 257
 258     s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
 259
 260     if ((s->r[R_CR] & UART_CR_TX_EN) && !(s->r[R_CR] & UART_CR_TX_DIS)) {
 261             uart_tx_redo(s);
 262     }
 263
 264     if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
 265         uart_send_breaks(s);
 266     }
 267 }
 268
 269 static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
 270 {
 271     UartState *s = (UartState *)opaque;
 272     uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 273     int i;
 274
 275     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 276         return;
 277     }
 278
 279     if (s->rx_count == RX_FIFO_SIZE) {
 280         s->r[R_CISR] |= UART_INTR_ROVR;
 281     } else {
 282         for (i = 0; i < size; i++) {
 283             s->rx_fifo[s->rx_wpos] = buf[i];
 284             s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
 285             s->rx_count++;
 286         }
 287         timer_mod(s->fifo_trigger_handle, new_rx_time +
 288                                                 (s->char_tx_time * 4));
 289     }
 290     uart_update_status(s);
 291 }
 292
 293 static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
 294 {
 295     if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
 296         return;
 297     }
 298
 299     qemu_chr_fe_write_all(s->chr, buf, size);
 300 }
 301
 302 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 303 {
 304     UartState *s = (UartState *)opaque;
 305     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 306
 307     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
 308         uart_write_rx_fifo(opaque, buf, size);
 309     }
 310     if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
 311         uart_write_tx_fifo(s, buf, size);
 312     }
 313 }
 314
 315 static void uart_event(void *opaque, int event)
 316 {
 317     UartState *s = (UartState *)opaque;
 318     uint8_t buf = '\0';
 319
 320     if (event == CHR_EVENT_BREAK) {
 321         uart_write_rx_fifo(opaque, &buf, 1);
 322     }
 323
 324     uart_update_status(s);
 325 }
 326
 327 static void uart_read_rx_fifo(UartState *s, uint32_t *c)
 328 {
 329     if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
 330         return;
 331     }
 332
 333     if (s->rx_count) {
 334         uint32_t rx_rpos =
 335                 (RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
 336         *c = s->rx_fifo[rx_rpos];
 337         s->rx_count--;
 338
 339         qemu_chr_accept_input(s->chr);
 340     } else {
 341         *c = 0;
 342     }
 343
 344     uart_update_status(s);
 345 }
 346
 347 static void uart_write(void *opaque, hwaddr offset,
 348                           uint64_t value, unsigned size)
 349 {
 350     UartState *s = (UartState *)opaque;
 351
 352     DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
 353     offset >>= 2;
 354     switch (offset) {
 355     case R_IER: /* ier (wts imr) */
 356         s->r[R_IMR] |= value;
 357         break;
 358     case R_IDR: /* idr (wtc imr) */
 359         s->r[R_IMR] &= ~value;
 360         break;
 361     case R_IMR: /* imr (read only) */
 362         break;
 363     case R_CISR: /* cisr (wtc) */
 364         s->r[R_CISR] &= ~value;
 365         break;
 366     case R_TX_RX: /* UARTDR */
 367         switch (s->r[R_MR] & UART_MR_CHMODE) {
 368         case NORMAL_MODE:
 369             uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 370             break;
 371         case LOCAL_LOOPBACK:
 372             uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
 373             break;
 374         }
 375         break;
 376     default:
 377         s->r[offset] = value;
 378     }
 379
 380     switch (offset) {
 381     case R_CR:
 382         uart_ctrl_update(s);
 383         break;
 384     case R_MR:
 385         uart_parameters_setup(s);
 386         break;
 387     }
 388     uart_update_status(s);
 389 }
 390
 391 static uint64_t uart_read(void *opaque, hwaddr offset,
 392         unsigned size)
 393 {
 394     UartState *s = (UartState *)opaque;
 395     uint32_t c = 0;
 396
 397     offset >>= 2;
 398     if (offset >= R_MAX) {
 399         c = 0;
 400     } else if (offset == R_TX_RX) {
 401         uart_read_rx_fifo(s, &c);
 402     } else {
 403        c = s->r[offset];
 404     }
 405
 406     DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
 407     return c;
 408 }
 409
 410 static const MemoryRegionOps uart_ops = {
 411     .read = uart_read,
 412     .write = uart_write,
 413     .endianness = DEVICE_NATIVE_ENDIAN,
 414 };
 415
 416 static void cadence_uart_reset(DeviceState *dev)
 417 {
 418     UartState *s = CADENCE_UART(dev);
 419
 420     s->r[R_CR] = 0x00000128;
 421     s->r[R_IMR] = 0;
 422     s->r[R_CISR] = 0;
 423     s->r[R_RTRIG] = 0x00000020;
 424     s->r[R_BRGR] = 0x0000000F;
 425     s->r[R_TTRIG] = 0x00000020;
 426
 427     uart_rx_reset(s);
 428     uart_tx_reset(s);
 429
 430     s->rx_count = 0;
 431     s->rx_wpos = 0;
 432     uart_update_status(s);
 433 }
 434
 435 static int cadence_uart_init(SysBusDevice *dev)
 436 {
 437     UartState *s = CADENCE_UART(dev);
 438
 439     memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
 440     sysbus_init_mmio(dev, &s->iomem);
 441     sysbus_init_irq(dev, &s->irq);
 442
 443     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 444             (QEMUTimerCB *)fifo_trigger_update, s);
 445
 446     s->tx_time_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 447             (QEMUTimerCB *)uart_tx_write, s);
 448
 449     s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
 450
 451     s->chr = qemu_char_get_next_serial();
 452
 453     if (s->chr) {
 454         qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
 455                               uart_event, s);
 456     }
 457
 458     return 0;
 459 }
 460
 461 static int cadence_uart_post_load(void *opaque, int version_id)
 462 {
 463     UartState *s = opaque;
 464
 465     uart_parameters_setup(s);
 466     uart_update_status(s);
 467     return 0;
 468 }
 469
 470 static const VMStateDescription vmstate_cadence_uart = {
 471     .name = "cadence_uart",
 472     .version_id = 1,
 473     .minimum_version_id = 1,
 474     .minimum_version_id_old = 1,
 475     .post_load = cadence_uart_post_load,
 476     .fields = (VMStateField[]) {
 477         VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
 478         VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
 479         VMSTATE_UINT32(rx_count, UartState),
 480         VMSTATE_UINT32(rx_wpos, UartState),
 481         VMSTATE_TIMER(fifo_trigger_handle, UartState),
 482         VMSTATE_TIMER(tx_time_handle, UartState),
 483         VMSTATE_END_OF_LIST()
 484     }
 485 };
 486
 487 static void cadence_uart_class_init(ObjectClass *klass, void *data)
 488 {
 489     DeviceClass *dc = DEVICE_CLASS(klass);
 490     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 491
 492     sdc->init = cadence_uart_init;
 493     dc->vmsd = &vmstate_cadence_uart;
 494     dc->reset = cadence_uart_reset;
 495 }
 496
 497 static const TypeInfo cadence_uart_info = {
 498     .name          = TYPE_CADENCE_UART,
 499     .parent        = TYPE_SYS_BUS_DEVICE,
 500     .instance_size = sizeof(UartState),
 501     .class_init    = cadence_uart_class_init,
 502 };
 503
 504 static void cadence_uart_register_types(void)
 505 {
 506     type_register_static(&cadence_uart_info);
 507 }
 508
 509 type_init(cadence_uart_register_types)