qtest.c

   1 /*
   2  * Test Server
   3  *
   4  * Copyright IBM, Corp. 2011
   5  *
   6  * Authors:
   7  *  Anthony Liguori   <aliguori@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "sysemu/qtest.h"
  15 #include "hw/qdev.h"
  16 #include "sysemu/char.h"
  17 #include "exec/ioport.h"
  18 #include "exec/memory.h"
  19 #include "hw/irq.h"
  20 #include "sysemu/accel.h"
  21 #include "sysemu/sysemu.h"
  22 #include "sysemu/cpus.h"
  23 #include "qemu/config-file.h"
  24 #include "qemu/option.h"
  25 #include "qemu/error-report.h"
  26
  27 #define MAX_IRQ 256
  28
  29 bool qtest_allowed;
  30
  31 static DeviceState *irq_intercept_dev;
  32 static FILE *qtest_log_fp;
  33 static CharDriverState *qtest_chr;
  34 static GString *inbuf;
  35 static int irq_levels[MAX_IRQ];
  36 static qemu_timeval start_time;
  37 static bool qtest_opened;
  38
  39 #define FMT_timeval "%ld.%06ld"
  40
  41 /**
  42  * QTest Protocol
  43  *
  44  * Line based protocol, request/response based.  Server can send async messages
  45  * so clients should always handle many async messages before the response
  46  * comes in.
  47  *
  48  * Valid requests
  49  *
  50  * Clock management:
  51  *
  52  * The qtest client is completely in charge of the QEMU_CLOCK_VIRTUAL.  qtest commands
  53  * let you adjust the value of the clock (monotonically).  All the commands
  54  * return the current value of the clock in nanoseconds.
  55  *
  56  *  > clock_step
  57  *  < OK VALUE
  58  *
  59  *     Advance the clock to the next deadline.  Useful when waiting for
  60  *     asynchronous events.
  61  *
  62  *  > clock_step NS
  63  *  < OK VALUE
  64  *
  65  *     Advance the clock by NS nanoseconds.
  66  *
  67  *  > clock_set NS
  68  *  < OK VALUE
  69  *
  70  *     Advance the clock to NS nanoseconds (do nothing if it's already past).
  71  *
  72  * PIO and memory access:
  73  *
  74  *  > outb ADDR VALUE
  75  *  < OK
  76  *
  77  *  > outw ADDR VALUE
  78  *  < OK
  79  *
  80  *  > outl ADDR VALUE
  81  *  < OK
  82  *
  83  *  > inb ADDR
  84  *  < OK VALUE
  85  *
  86  *  > inw ADDR
  87  *  < OK VALUE
  88  *
  89  *  > inl ADDR
  90  *  < OK VALUE
  91  *
  92  *  > writeb ADDR VALUE
  93  *  < OK
  94  *
  95  *  > writew ADDR VALUE
  96  *  < OK
  97  *
  98  *  > writel ADDR VALUE
  99  *  < OK
 100  *
 101  *  > writeq ADDR VALUE
 102  *  < OK
 103  *
 104  *  > readb ADDR
 105  *  < OK VALUE
 106  *
 107  *  > readw ADDR
 108  *  < OK VALUE
 109  *
 110  *  > readl ADDR
 111  *  < OK VALUE
 112  *
 113  *  > readq ADDR
 114  *  < OK VALUE
 115  *
 116  *  > read ADDR SIZE
 117  *  < OK DATA
 118  *
 119  *  > write ADDR SIZE DATA
 120  *  < OK
 121  *
 122  * ADDR, SIZE, VALUE are all integers parsed with strtoul() with a base of 0.
 123  *
 124  * DATA is an arbitrarily long hex number prefixed with '0x'.  If it's smaller
 125  * than the expected size, the value will be zero filled at the end of the data
 126  * sequence.
 127  *
 128  * IRQ management:
 129  *
 130  *  > irq_intercept_in QOM-PATH
 131  *  < OK
 132  *
 133  *  > irq_intercept_out QOM-PATH
 134  *  < OK
 135  *
 136  * Attach to the gpio-in (resp. gpio-out) pins exported by the device at
 137  * QOM-PATH.  When the pin is triggered, one of the following async messages
 138  * will be printed to the qtest stream:
 139  *
 140  *  IRQ raise NUM
 141  *  IRQ lower NUM
 142  *
 143  * where NUM is an IRQ number.  For the PC, interrupts can be intercepted
 144  * simply with "irq_intercept_in ioapic" (note that IRQ0 comes out with
 145  * NUM=0 even though it is remapped to GSI 2).
 146  */
 147
 148 static int hex2nib(char ch)
 149 {
 150     if (ch >= '0' && ch <= '9') {
 151         return ch - '0';
 152     } else if (ch >= 'a' && ch <= 'f') {
 153         return 10 + (ch - 'a');
 154     } else if (ch >= 'A' && ch <= 'F') {
 155         return 10 + (ch - 'A');
 156     } else {
 157         return -1;
 158     }
 159 }
 160
 161 static void qtest_get_time(qemu_timeval *tv)
 162 {
 163     qemu_gettimeofday(tv);
 164     tv->tv_sec -= start_time.tv_sec;
 165     tv->tv_usec -= start_time.tv_usec;
 166     if (tv->tv_usec < 0) {
 167         tv->tv_usec += 1000000;
 168         tv->tv_sec -= 1;
 169     }
 170 }
 171
 172 static void qtest_send_prefix(CharDriverState *chr)
 173 {
 174     qemu_timeval tv;
 175
 176     if (!qtest_log_fp || !qtest_opened) {
 177         return;
 178     }
 179
 180     qtest_get_time(&tv);
 181     fprintf(qtest_log_fp, "[S +" FMT_timeval "] ",
 182             (long) tv.tv_sec, (long) tv.tv_usec);
 183 }
 184
 185 static void GCC_FMT_ATTR(2, 3) qtest_send(CharDriverState *chr,
 186                                           const char *fmt, ...)
 187 {
 188     va_list ap;
 189     char buffer[1024];
 190     size_t len;
 191
 192     va_start(ap, fmt);
 193     len = vsnprintf(buffer, sizeof(buffer), fmt, ap);
 194     va_end(ap);
 195
 196     qemu_chr_fe_write_all(chr, (uint8_t *)buffer, len);
 197     if (qtest_log_fp && qtest_opened) {
 198         fprintf(qtest_log_fp, "%s", buffer);
 199     }
 200 }
 201
 202 static void qtest_irq_handler(void *opaque, int n, int level)
 203 {
 204     qemu_irq *old_irqs = opaque;
 205     qemu_set_irq(old_irqs[n], level);
 206
 207     if (irq_levels[n] != level) {
 208         CharDriverState *chr = qtest_chr;
 209         irq_levels[n] = level;
 210         qtest_send_prefix(chr);
 211         qtest_send(chr, "IRQ %s %d\n",
 212                    level ? "raise" : "lower", n);
 213     }
 214 }
 215
 216 static void qtest_process_command(CharDriverState *chr, gchar **words)
 217 {
 218     const gchar *command;
 219
 220     g_assert(words);
 221
 222     command = words[0];
 223
 224     if (qtest_log_fp) {
 225         qemu_timeval tv;
 226         int i;
 227
 228         qtest_get_time(&tv);
 229         fprintf(qtest_log_fp, "[R +" FMT_timeval "]",
 230                 (long) tv.tv_sec, (long) tv.tv_usec);
 231         for (i = 0; words[i]; i++) {
 232             fprintf(qtest_log_fp, " %s", words[i]);
 233         }
 234         fprintf(qtest_log_fp, "\n");
 235     }
 236
 237     g_assert(command);
 238     if (strcmp(words[0], "irq_intercept_out") == 0
 239         || strcmp(words[0], "irq_intercept_in") == 0) {
 240         DeviceState *dev;
 241         NamedGPIOList *ngl;
 242
 243         g_assert(words[1]);
 244         dev = DEVICE(object_resolve_path(words[1], NULL));
 245         if (!dev) {
 246             qtest_send_prefix(chr);
 247             qtest_send(chr, "FAIL Unknown device\n");
 248             return;
 249         }
 250
 251         if (irq_intercept_dev) {
 252             qtest_send_prefix(chr);
 253             if (irq_intercept_dev != dev) {
 254                 qtest_send(chr, "FAIL IRQ intercept already enabled\n");
 255             } else {
 256                 qtest_send(chr, "OK\n");
 257             }
 258             return;
 259         }
 260
 261         QLIST_FOREACH(ngl, &dev->gpios, node) {
 262             /* We don't support intercept of named GPIOs yet */
 263             if (ngl->name) {
 264                 continue;
 265             }
 266             if (words[0][14] == 'o') {
 267                 qemu_irq_intercept_out(&ngl->out, qtest_irq_handler,
 268                                        ngl->num_out);
 269             } else {
 270                 qemu_irq_intercept_in(ngl->in, qtest_irq_handler,
 271                                       ngl->num_in);
 272             }
 273         }
 274         irq_intercept_dev = dev;
 275         qtest_send_prefix(chr);
 276         qtest_send(chr, "OK\n");
 277
 278     } else if (strcmp(words[0], "outb") == 0 ||
 279                strcmp(words[0], "outw") == 0 ||
 280                strcmp(words[0], "outl") == 0) {
 281         uint16_t addr;
 282         uint32_t value;
 283
 284         g_assert(words[1] && words[2]);
 285         addr = strtoul(words[1], NULL, 0);
 286         value = strtoul(words[2], NULL, 0);
 287
 288         if (words[0][3] == 'b') {
 289             cpu_outb(addr, value);
 290         } else if (words[0][3] == 'w') {
 291             cpu_outw(addr, value);
 292         } else if (words[0][3] == 'l') {
 293             cpu_outl(addr, value);
 294         }
 295         qtest_send_prefix(chr);
 296         qtest_send(chr, "OK\n");
 297     } else if (strcmp(words[0], "inb") == 0 ||
 298         strcmp(words[0], "inw") == 0 ||
 299         strcmp(words[0], "inl") == 0) {
 300         uint16_t addr;
 301         uint32_t value = -1U;
 302
 303         g_assert(words[1]);
 304         addr = strtoul(words[1], NULL, 0);
 305
 306         if (words[0][2] == 'b') {
 307             value = cpu_inb(addr);
 308         } else if (words[0][2] == 'w') {
 309             value = cpu_inw(addr);
 310         } else if (words[0][2] == 'l') {
 311             value = cpu_inl(addr);
 312         }
 313         qtest_send_prefix(chr);
 314         qtest_send(chr, "OK 0x%04x\n", value);
 315     } else if (strcmp(words[0], "writeb") == 0 ||
 316                strcmp(words[0], "writew") == 0 ||
 317                strcmp(words[0], "writel") == 0 ||
 318                strcmp(words[0], "writeq") == 0) {
 319         uint64_t addr;
 320         uint64_t value;
 321
 322         g_assert(words[1] && words[2]);
 323         addr = strtoull(words[1], NULL, 0);
 324         value = strtoull(words[2], NULL, 0);
 325
 326         if (words[0][5] == 'b') {
 327             uint8_t data = value;
 328             cpu_physical_memory_write(addr, &data, 1);
 329         } else if (words[0][5] == 'w') {
 330             uint16_t data = value;
 331             tswap16s(&data);
 332             cpu_physical_memory_write(addr, &data, 2);
 333         } else if (words[0][5] == 'l') {
 334             uint32_t data = value;
 335             tswap32s(&data);
 336             cpu_physical_memory_write(addr, &data, 4);
 337         } else if (words[0][5] == 'q') {
 338             uint64_t data = value;
 339             tswap64s(&data);
 340             cpu_physical_memory_write(addr, &data, 8);
 341         }
 342         qtest_send_prefix(chr);
 343         qtest_send(chr, "OK\n");
 344     } else if (strcmp(words[0], "readb") == 0 ||
 345                strcmp(words[0], "readw") == 0 ||
 346                strcmp(words[0], "readl") == 0 ||
 347                strcmp(words[0], "readq") == 0) {
 348         uint64_t addr;
 349         uint64_t value = UINT64_C(-1);
 350
 351         g_assert(words[1]);
 352         addr = strtoull(words[1], NULL, 0);
 353
 354         if (words[0][4] == 'b') {
 355             uint8_t data;
 356             cpu_physical_memory_read(addr, &data, 1);
 357             value = data;
 358         } else if (words[0][4] == 'w') {
 359             uint16_t data;
 360             cpu_physical_memory_read(addr, &data, 2);
 361             value = tswap16(data);
 362         } else if (words[0][4] == 'l') {
 363             uint32_t data;
 364             cpu_physical_memory_read(addr, &data, 4);
 365             value = tswap32(data);
 366         } else if (words[0][4] == 'q') {
 367             cpu_physical_memory_read(addr, &value, 8);
 368             tswap64s(&value);
 369         }
 370         qtest_send_prefix(chr);
 371         qtest_send(chr, "OK 0x%016" PRIx64 "\n", value);
 372     } else if (strcmp(words[0], "read") == 0) {
 373         uint64_t addr, len, i;
 374         uint8_t *data;
 375
 376         g_assert(words[1] && words[2]);
 377         addr = strtoull(words[1], NULL, 0);
 378         len = strtoull(words[2], NULL, 0);
 379
 380         data = g_malloc(len);
 381         cpu_physical_memory_read(addr, data, len);
 382
 383         qtest_send_prefix(chr);
 384         qtest_send(chr, "OK 0x");
 385         for (i = 0; i < len; i++) {
 386             qtest_send(chr, "%02x", data[i]);
 387         }
 388         qtest_send(chr, "\n");
 389
 390         g_free(data);
 391     } else if (strcmp(words[0], "write") == 0) {
 392         uint64_t addr, len, i;
 393         uint8_t *data;
 394         size_t data_len;
 395
 396         g_assert(words[1] && words[2] && words[3]);
 397         addr = strtoull(words[1], NULL, 0);
 398         len = strtoull(words[2], NULL, 0);
 399
 400         data_len = strlen(words[3]);
 401         if (data_len < 3) {
 402             qtest_send(chr, "ERR invalid argument size\n");
 403             return;
 404         }
 405
 406         data = g_malloc(len);
 407         for (i = 0; i < len; i++) {
 408             if ((i * 2 + 4) <= data_len) {
 409                 data[i] = hex2nib(words[3][i * 2 + 2]) << 4;
 410                 data[i] |= hex2nib(words[3][i * 2 + 3]);
 411             } else {
 412                 data[i] = 0;
 413             }
 414         }
 415         cpu_physical_memory_write(addr, data, len);
 416         g_free(data);
 417
 418         qtest_send_prefix(chr);
 419         qtest_send(chr, "OK\n");
 420     } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) {
 421         int64_t ns;
 422
 423         if (words[1]) {
 424             ns = strtoll(words[1], NULL, 0);
 425         } else {
 426             ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
 427         }
 428         qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns);
 429         qtest_send_prefix(chr);
 430         qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 431     } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) {
 432         int64_t ns;
 433
 434         g_assert(words[1]);
 435         ns = strtoll(words[1], NULL, 0);
 436         qtest_clock_warp(ns);
 437         qtest_send_prefix(chr);
 438         qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 439     } else {
 440         qtest_send_prefix(chr);
 441         qtest_send(chr, "FAIL Unknown command `%s'\n", words[0]);
 442     }
 443 }
 444
 445 static void qtest_process_inbuf(CharDriverState *chr, GString *inbuf)
 446 {
 447     char *end;
 448
 449     while ((end = strchr(inbuf->str, '\n')) != NULL) {
 450         size_t offset;
 451         GString *cmd;
 452         gchar **words;
 453
 454         offset = end - inbuf->str;
 455
 456         cmd = g_string_new_len(inbuf->str, offset);
 457         g_string_erase(inbuf, 0, offset + 1);
 458
 459         words = g_strsplit(cmd->str, " ", 0);
 460         qtest_process_command(chr, words);
 461         g_strfreev(words);
 462
 463         g_string_free(cmd, TRUE);
 464     }
 465 }
 466
 467 static void qtest_read(void *opaque, const uint8_t *buf, int size)
 468 {
 469     CharDriverState *chr = opaque;
 470
 471     g_string_append_len(inbuf, (const gchar *)buf, size);
 472     qtest_process_inbuf(chr, inbuf);
 473 }
 474
 475 static int qtest_can_read(void *opaque)
 476 {
 477     return 1024;
 478 }
 479
 480 static void qtest_event(void *opaque, int event)
 481 {
 482     int i;
 483
 484     switch (event) {
 485     case CHR_EVENT_OPENED:
 486         /*
 487          * We used to call qemu_system_reset() here, hoping we could
 488          * use the same process for multiple tests that way.  Never
 489          * used.  Injects an extra reset even when it's not used, and
 490          * that can mess up tests, e.g. -boot once.
 491          */
 492         for (i = 0; i < ARRAY_SIZE(irq_levels); i++) {
 493             irq_levels[i] = 0;
 494         }
 495         qemu_gettimeofday(&start_time);
 496         qtest_opened = true;
 497         if (qtest_log_fp) {
 498             fprintf(qtest_log_fp, "[I " FMT_timeval "] OPENED\n",
 499                     (long) start_time.tv_sec, (long) start_time.tv_usec);
 500         }
 501         break;
 502     case CHR_EVENT_CLOSED:
 503         qtest_opened = false;
 504         if (qtest_log_fp) {
 505             qemu_timeval tv;
 506             qtest_get_time(&tv);
 507             fprintf(qtest_log_fp, "[I +" FMT_timeval "] CLOSED\n",
 508                     (long) tv.tv_sec, (long) tv.tv_usec);
 509         }
 510         break;
 511     default:
 512         break;
 513     }
 514 }
 515
 516 static void configure_qtest_icount(const char *options)
 517 {
 518     QemuOpts *opts  = qemu_opts_parse(qemu_find_opts("icount"), options, 1);
 519     configure_icount(opts, &error_abort);
 520     qemu_opts_del(opts);
 521 }
 522
 523 static int qtest_init_accel(MachineState *ms)
 524 {
 525     configure_qtest_icount("0");
 526     return 0;
 527 }
 528
 529 void qtest_init(const char *qtest_chrdev, const char *qtest_log, Error **errp)
 530 {
 531     CharDriverState *chr;
 532
 533     chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
 534
 535     if (chr == NULL) {
 536         error_setg(errp, "Failed to initialize device for qtest: \"%s\"",
 537                    qtest_chrdev);
 538         return;
 539     }
 540
 541     qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
 542     qemu_chr_fe_set_echo(chr, true);
 543
 544     inbuf = g_string_new("");
 545
 546     if (qtest_log) {
 547         if (strcmp(qtest_log, "none") != 0) {
 548             qtest_log_fp = fopen(qtest_log, "w+");
 549         }
 550     } else {
 551         qtest_log_fp = stderr;
 552     }
 553
 554     qtest_chr = chr;
 555 }
 556
 557 bool qtest_driver(void)
 558 {
 559     return qtest_chr;
 560 }
 561
 562 static void qtest_accel_class_init(ObjectClass *oc, void *data)
 563 {
 564     AccelClass *ac = ACCEL_CLASS(oc);
 565     ac->name = "QTest";
 566     ac->available = qtest_available;
 567     ac->init_machine = qtest_init_accel;
 568     ac->allowed = &qtest_allowed;
 569 }
 570
 571 #define TYPE_QTEST_ACCEL ACCEL_CLASS_NAME("qtest")
 572
 573 static const TypeInfo qtest_accel_type = {
 574     .name = TYPE_QTEST_ACCEL,
 575     .parent = TYPE_ACCEL,
 576     .class_init = qtest_accel_class_init,
 577 };
 578
 579 static void qtest_type_init(void)
 580 {
 581     type_register_static(&qtest_accel_type);
 582 }
 583
 584 type_init(qtest_type_init);