target/riscv/debug.c

   1 /*
   2  * QEMU RISC-V Native Debug Support
   3  *
   4  * Copyright (c) 2022 Wind River Systems, Inc.
   5  *
   6  * Author:
   7  *   Bin Meng <bin.meng@windriver.com>
   8  *
   9  * This provides the native debug support via the Trigger Module, as defined
  10  * in the RISC-V Debug Specification:
  11  * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
  12  *
  13  * This program is free software; you can redistribute it and/or modify it
  14  * under the terms and conditions of the GNU General Public License,
  15  * version 2 or later, as published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope it will be useful, but WITHOUT
  18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  20  * more details.
  21  *
  22  * You should have received a copy of the GNU General Public License along with
  23  * this program.  If not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu/log.h"
  28 #include "qapi/error.h"
  29 #include "cpu.h"
  30 #include "trace.h"
  31 #include "exec/exec-all.h"
  32
  33 /*
  34  * The following M-mode trigger CSRs are implemented:
  35  *
  36  * - tselect
  37  * - tdata1
  38  * - tdata2
  39  * - tdata3
  40  * - tinfo
  41  *
  42  * The following triggers are initialized by default:
  43  *
  44  * Index | Type |          tdata mapping | Description
  45  * ------+------+------------------------+------------
  46  *     0 |    2 |         tdata1, tdata2 | Address / Data Match
  47  *     1 |    2 |         tdata1, tdata2 | Address / Data Match
  48  */
  49
  50 /* tdata availability of a trigger */
  51 typedef bool tdata_avail[TDATA_NUM];
  52
  53 static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] = {
  54     [TRIGGER_TYPE_NO_EXIST] = { false, false, false },
  55     [TRIGGER_TYPE_AD_MATCH] = { true, true, true },
  56     [TRIGGER_TYPE_INST_CNT] = { true, false, true },
  57     [TRIGGER_TYPE_INT] = { true, true, true },
  58     [TRIGGER_TYPE_EXCP] = { true, true, true },
  59     [TRIGGER_TYPE_AD_MATCH6] = { true, true, true },
  60     [TRIGGER_TYPE_EXT_SRC] = { true, false, false },
  61     [TRIGGER_TYPE_UNAVAIL] = { true, true, true }
  62 };
  63
  64 /* only breakpoint size 1/2/4/8 supported */
  65 static int access_size[SIZE_NUM] = {
  66     [SIZE_ANY] = 0,
  67     [SIZE_1B]  = 1,
  68     [SIZE_2B]  = 2,
  69     [SIZE_4B]  = 4,
  70     [SIZE_6B]  = -1,
  71     [SIZE_8B]  = 8,
  72     [6 ... 15] = -1,
  73 };
  74
  75 static inline target_ulong extract_trigger_type(CPURISCVState *env,
  76                                                 target_ulong tdata1)
  77 {
  78     switch (riscv_cpu_mxl(env)) {
  79     case MXL_RV32:
  80         return extract32(tdata1, 28, 4);
  81     case MXL_RV64:
  82     case MXL_RV128:
  83         return extract64(tdata1, 60, 4);
  84     default:
  85         g_assert_not_reached();
  86     }
  87 }
  88
  89 static inline target_ulong get_trigger_type(CPURISCVState *env,
  90                                             target_ulong trigger_index)
  91 {
  92     return extract_trigger_type(env, env->tdata1[trigger_index]);
  93 }
  94
  95 static trigger_action_t get_trigger_action(CPURISCVState *env,
  96                                            target_ulong trigger_index)
  97 {
  98     target_ulong tdata1 = env->tdata1[trigger_index];
  99     int trigger_type = get_trigger_type(env, trigger_index);
 100     trigger_action_t action = DBG_ACTION_NONE;
 101
 102     switch (trigger_type) {
 103     case TRIGGER_TYPE_AD_MATCH:
 104         action = (tdata1 & TYPE2_ACTION) >> 12;
 105         break;
 106     case TRIGGER_TYPE_AD_MATCH6:
 107         action = (tdata1 & TYPE6_ACTION) >> 12;
 108         break;
 109     case TRIGGER_TYPE_INST_CNT:
 110     case TRIGGER_TYPE_INT:
 111     case TRIGGER_TYPE_EXCP:
 112     case TRIGGER_TYPE_EXT_SRC:
 113         qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
 114                       trigger_type);
 115         break;
 116     case TRIGGER_TYPE_NO_EXIST:
 117     case TRIGGER_TYPE_UNAVAIL:
 118         qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
 119                       trigger_type);
 120         break;
 121     default:
 122         g_assert_not_reached();
 123     }
 124
 125     return action;
 126 }
 127
 128 static inline target_ulong build_tdata1(CPURISCVState *env,
 129                                         trigger_type_t type,
 130                                         bool dmode, target_ulong data)
 131 {
 132     target_ulong tdata1;
 133
 134     switch (riscv_cpu_mxl(env)) {
 135     case MXL_RV32:
 136         tdata1 = RV32_TYPE(type) |
 137                  (dmode ? RV32_DMODE : 0) |
 138                  (data & RV32_DATA_MASK);
 139         break;
 140     case MXL_RV64:
 141     case MXL_RV128:
 142         tdata1 = RV64_TYPE(type) |
 143                  (dmode ? RV64_DMODE : 0) |
 144                  (data & RV64_DATA_MASK);
 145         break;
 146     default:
 147         g_assert_not_reached();
 148     }
 149
 150     return tdata1;
 151 }
 152
 153 bool tdata_available(CPURISCVState *env, int tdata_index)
 154 {
 155     int trigger_type = get_trigger_type(env, env->trigger_cur);
 156
 157     if (unlikely(tdata_index >= TDATA_NUM)) {
 158         return false;
 159     }
 160
 161     return tdata_mapping[trigger_type][tdata_index];
 162 }
 163
 164 target_ulong tselect_csr_read(CPURISCVState *env)
 165 {
 166     return env->trigger_cur;
 167 }
 168
 169 void tselect_csr_write(CPURISCVState *env, target_ulong val)
 170 {
 171     if (val < RV_MAX_TRIGGERS) {
 172         env->trigger_cur = val;
 173     }
 174 }
 175
 176 static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
 177                                     trigger_type_t t)
 178 {
 179     uint32_t type, dmode;
 180     target_ulong tdata1;
 181
 182     switch (riscv_cpu_mxl(env)) {
 183     case MXL_RV32:
 184         type = extract32(val, 28, 4);
 185         dmode = extract32(val, 27, 1);
 186         tdata1 = RV32_TYPE(t);
 187         break;
 188     case MXL_RV64:
 189     case MXL_RV128:
 190         type = extract64(val, 60, 4);
 191         dmode = extract64(val, 59, 1);
 192         tdata1 = RV64_TYPE(t);
 193         break;
 194     default:
 195         g_assert_not_reached();
 196     }
 197
 198     if (type != t) {
 199         qemu_log_mask(LOG_GUEST_ERROR,
 200                       "ignoring type write to tdata1 register\n");
 201     }
 202
 203     if (dmode != 0) {
 204         qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n");
 205     }
 206
 207     return tdata1;
 208 }
 209
 210 static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
 211                                         const char *msg)
 212 {
 213     if (val & mask) {
 214         qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg);
 215     }
 216 }
 217
 218 static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
 219 {
 220     trigger_action_t action = get_trigger_action(env, trigger_index);
 221
 222     switch (action) {
 223     case DBG_ACTION_NONE:
 224         break;
 225     case DBG_ACTION_BP:
 226         riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
 227         break;
 228     case DBG_ACTION_DBG_MODE:
 229     case DBG_ACTION_TRACE0:
 230     case DBG_ACTION_TRACE1:
 231     case DBG_ACTION_TRACE2:
 232     case DBG_ACTION_TRACE3:
 233     case DBG_ACTION_EXT_DBG0:
 234     case DBG_ACTION_EXT_DBG1:
 235         qemu_log_mask(LOG_UNIMP, "action: %d is not supported\n", action);
 236         break;
 237     default:
 238         g_assert_not_reached();
 239     }
 240 }
 241
 242 /* type 2 trigger */
 243
 244 static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
 245 {
 246     uint32_t sizelo, sizehi = 0;
 247
 248     if (riscv_cpu_mxl(env) == MXL_RV64) {
 249         sizehi = extract32(ctrl, 21, 2);
 250     }
 251     sizelo = extract32(ctrl, 16, 2);
 252     return (sizehi << 2) | sizelo;
 253 }
 254
 255 static inline bool type2_breakpoint_enabled(target_ulong ctrl)
 256 {
 257     bool mode = !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M));
 258     bool rwx = !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
 259
 260     return mode && rwx;
 261 }
 262
 263 static target_ulong type2_mcontrol_validate(CPURISCVState *env,
 264                                             target_ulong ctrl)
 265 {
 266     target_ulong val;
 267     uint32_t size;
 268
 269     /* validate the generic part first */
 270     val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);
 271
 272     /* validate unimplemented (always zero) bits */
 273     warn_always_zero_bit(ctrl, TYPE2_MATCH, "match");
 274     warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain");
 275     warn_always_zero_bit(ctrl, TYPE2_ACTION, "action");
 276     warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing");
 277     warn_always_zero_bit(ctrl, TYPE2_SELECT, "select");
 278     warn_always_zero_bit(ctrl, TYPE2_HIT, "hit");
 279
 280     /* validate size encoding */
 281     size = type2_breakpoint_size(env, ctrl);
 282     if (access_size[size] == -1) {
 283         qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
 284                       size);
 285     } else {
 286         val |= (ctrl & TYPE2_SIZELO);
 287         if (riscv_cpu_mxl(env) == MXL_RV64) {
 288             val |= (ctrl & TYPE2_SIZEHI);
 289         }
 290     }
 291
 292     /* keep the mode and attribute bits */
 293     val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M |
 294                     TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
 295
 296     return val;
 297 }
 298
 299 static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
 300 {
 301     target_ulong ctrl = env->tdata1[index];
 302     target_ulong addr = env->tdata2[index];
 303     bool enabled = type2_breakpoint_enabled(ctrl);
 304     CPUState *cs = env_cpu(env);
 305     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 306     uint32_t size;
 307
 308     if (!enabled) {
 309         return;
 310     }
 311
 312     if (ctrl & TYPE2_EXEC) {
 313         cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
 314     }
 315
 316     if (ctrl & TYPE2_LOAD) {
 317         flags |= BP_MEM_READ;
 318     }
 319     if (ctrl & TYPE2_STORE) {
 320         flags |= BP_MEM_WRITE;
 321     }
 322
 323     if (flags & BP_MEM_ACCESS) {
 324         size = type2_breakpoint_size(env, ctrl);
 325         if (size != 0) {
 326             cpu_watchpoint_insert(cs, addr, size, flags,
 327                                   &env->cpu_watchpoint[index]);
 328         } else {
 329             cpu_watchpoint_insert(cs, addr, 8, flags,
 330                                   &env->cpu_watchpoint[index]);
 331         }
 332     }
 333 }
 334
 335 static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index)
 336 {
 337     CPUState *cs = env_cpu(env);
 338
 339     if (env->cpu_breakpoint[index]) {
 340         cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
 341         env->cpu_breakpoint[index] = NULL;
 342     }
 343
 344     if (env->cpu_watchpoint[index]) {
 345         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
 346         env->cpu_watchpoint[index] = NULL;
 347     }
 348 }
 349
 350 static void type2_reg_write(CPURISCVState *env, target_ulong index,
 351                             int tdata_index, target_ulong val)
 352 {
 353     target_ulong new_val;
 354
 355     switch (tdata_index) {
 356     case TDATA1:
 357         new_val = type2_mcontrol_validate(env, val);
 358         if (new_val != env->tdata1[index]) {
 359             env->tdata1[index] = new_val;
 360             type2_breakpoint_remove(env, index);
 361             type2_breakpoint_insert(env, index);
 362         }
 363         break;
 364     case TDATA2:
 365         if (val != env->tdata2[index]) {
 366             env->tdata2[index] = val;
 367             type2_breakpoint_remove(env, index);
 368             type2_breakpoint_insert(env, index);
 369         }
 370         break;
 371     case TDATA3:
 372         qemu_log_mask(LOG_UNIMP,
 373                       "tdata3 is not supported for type 2 trigger\n");
 374         break;
 375     default:
 376         g_assert_not_reached();
 377     }
 378
 379     return;
 380 }
 381
 382 /* type 6 trigger */
 383
 384 static inline bool type6_breakpoint_enabled(target_ulong ctrl)
 385 {
 386     bool mode = !!(ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M));
 387     bool rwx = !!(ctrl & (TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
 388
 389     return mode && rwx;
 390 }
 391
 392 static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
 393                                              target_ulong ctrl)
 394 {
 395     target_ulong val;
 396     uint32_t size;
 397
 398     /* validate the generic part first */
 399     val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);
 400
 401     /* validate unimplemented (always zero) bits */
 402     warn_always_zero_bit(ctrl, TYPE6_MATCH, "match");
 403     warn_always_zero_bit(ctrl, TYPE6_CHAIN, "chain");
 404     warn_always_zero_bit(ctrl, TYPE6_ACTION, "action");
 405     warn_always_zero_bit(ctrl, TYPE6_TIMING, "timing");
 406     warn_always_zero_bit(ctrl, TYPE6_SELECT, "select");
 407     warn_always_zero_bit(ctrl, TYPE6_HIT, "hit");
 408
 409     /* validate size encoding */
 410     size = extract32(ctrl, 16, 4);
 411     if (access_size[size] == -1) {
 412         qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using SIZE_ANY\n",
 413                       size);
 414     } else {
 415         val |= (ctrl & TYPE6_SIZE);
 416     }
 417
 418     /* keep the mode and attribute bits */
 419     val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M |
 420                     TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
 421
 422     return val;
 423 }
 424
 425 static void type6_breakpoint_insert(CPURISCVState *env, target_ulong index)
 426 {
 427     target_ulong ctrl = env->tdata1[index];
 428     target_ulong addr = env->tdata2[index];
 429     bool enabled = type6_breakpoint_enabled(ctrl);
 430     CPUState *cs = env_cpu(env);
 431     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
 432     uint32_t size;
 433
 434     if (!enabled) {
 435         return;
 436     }
 437
 438     if (ctrl & TYPE6_EXEC) {
 439         cpu_breakpoint_insert(cs, addr, flags, &env->cpu_breakpoint[index]);
 440     }
 441
 442     if (ctrl & TYPE6_LOAD) {
 443         flags |= BP_MEM_READ;
 444     }
 445
 446     if (ctrl & TYPE6_STORE) {
 447         flags |= BP_MEM_WRITE;
 448     }
 449
 450     if (flags & BP_MEM_ACCESS) {
 451         size = extract32(ctrl, 16, 4);
 452         if (size != 0) {
 453             cpu_watchpoint_insert(cs, addr, size, flags,
 454                                   &env->cpu_watchpoint[index]);
 455         } else {
 456             cpu_watchpoint_insert(cs, addr, 8, flags,
 457                                   &env->cpu_watchpoint[index]);
 458         }
 459     }
 460 }
 461
 462 static void type6_breakpoint_remove(CPURISCVState *env, target_ulong index)
 463 {
 464     type2_breakpoint_remove(env, index);
 465 }
 466
 467 static void type6_reg_write(CPURISCVState *env, target_ulong index,
 468                             int tdata_index, target_ulong val)
 469 {
 470     target_ulong new_val;
 471
 472     switch (tdata_index) {
 473     case TDATA1:
 474         new_val = type6_mcontrol6_validate(env, val);
 475         if (new_val != env->tdata1[index]) {
 476             env->tdata1[index] = new_val;
 477             type6_breakpoint_remove(env, index);
 478             type6_breakpoint_insert(env, index);
 479         }
 480         break;
 481     case TDATA2:
 482         if (val != env->tdata2[index]) {
 483             env->tdata2[index] = val;
 484             type6_breakpoint_remove(env, index);
 485             type6_breakpoint_insert(env, index);
 486         }
 487         break;
 488     case TDATA3:
 489         qemu_log_mask(LOG_UNIMP,
 490                       "tdata3 is not supported for type 6 trigger\n");
 491         break;
 492     default:
 493         g_assert_not_reached();
 494     }
 495
 496     return;
 497 }
 498
 499 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index)
 500 {
 501     switch (tdata_index) {
 502     case TDATA1:
 503         return env->tdata1[env->trigger_cur];
 504     case TDATA2:
 505         return env->tdata2[env->trigger_cur];
 506     case TDATA3:
 507         return env->tdata3[env->trigger_cur];
 508     default:
 509         g_assert_not_reached();
 510     }
 511 }
 512
 513 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
 514 {
 515     int trigger_type;
 516
 517     if (tdata_index == TDATA1) {
 518         trigger_type = extract_trigger_type(env, val);
 519     } else {
 520         trigger_type = get_trigger_type(env, env->trigger_cur);
 521     }
 522
 523     switch (trigger_type) {
 524     case TRIGGER_TYPE_AD_MATCH:
 525         type2_reg_write(env, env->trigger_cur, tdata_index, val);
 526         break;
 527     case TRIGGER_TYPE_AD_MATCH6:
 528         type6_reg_write(env, env->trigger_cur, tdata_index, val);
 529         break;
 530     case TRIGGER_TYPE_INST_CNT:
 531     case TRIGGER_TYPE_INT:
 532     case TRIGGER_TYPE_EXCP:
 533     case TRIGGER_TYPE_EXT_SRC:
 534         qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n",
 535                       trigger_type);
 536         break;
 537     case TRIGGER_TYPE_NO_EXIST:
 538     case TRIGGER_TYPE_UNAVAIL:
 539         qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
 540                       trigger_type);
 541         break;
 542     default:
 543         g_assert_not_reached();
 544     }
 545 }
 546
 547 target_ulong tinfo_csr_read(CPURISCVState *env)
 548 {
 549     /* assume all triggers support the same types of triggers */
 550     return BIT(TRIGGER_TYPE_AD_MATCH) |
 551            BIT(TRIGGER_TYPE_AD_MATCH6);
 552 }
 553
 554 void riscv_cpu_debug_excp_handler(CPUState *cs)
 555 {
 556     RISCVCPU *cpu = RISCV_CPU(cs);
 557     CPURISCVState *env = &cpu->env;
 558
 559     if (cs->watchpoint_hit) {
 560         if (cs->watchpoint_hit->flags & BP_CPU) {
 561             cs->watchpoint_hit = NULL;
 562             do_trigger_action(env, DBG_ACTION_BP);
 563         }
 564     } else {
 565         if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
 566             do_trigger_action(env, DBG_ACTION_BP);
 567         }
 568     }
 569 }
 570
 571 bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
 572 {
 573     RISCVCPU *cpu = RISCV_CPU(cs);
 574     CPURISCVState *env = &cpu->env;
 575     CPUBreakpoint *bp;
 576     target_ulong ctrl;
 577     target_ulong pc;
 578     int trigger_type;
 579     int i;
 580
 581     QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 582         for (i = 0; i < RV_MAX_TRIGGERS; i++) {
 583             trigger_type = get_trigger_type(env, i);
 584
 585             switch (trigger_type) {
 586             case TRIGGER_TYPE_AD_MATCH:
 587                 /* type 2 trigger cannot be fired in VU/VS mode */
 588                 if (riscv_cpu_virt_enabled(env)) {
 589                     return false;
 590                 }
 591
 592                 ctrl = env->tdata1[i];
 593                 pc = env->tdata2[i];
 594
 595                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
 596                     /* check U/S/M bit against current privilege level */
 597                     if ((ctrl >> 3) & BIT(env->priv)) {
 598                         return true;
 599                     }
 600                 }
 601                 break;
 602             case TRIGGER_TYPE_AD_MATCH6:
 603                 ctrl = env->tdata1[i];
 604                 pc = env->tdata2[i];
 605
 606                 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
 607                     if (riscv_cpu_virt_enabled(env)) {
 608                         /* check VU/VS bit against current privilege level */
 609                         if ((ctrl >> 23) & BIT(env->priv)) {
 610                             return true;
 611                         }
 612                     } else {
 613                         /* check U/S/M bit against current privilege level */
 614                         if ((ctrl >> 3) & BIT(env->priv)) {
 615                             return true;
 616                         }
 617                     }
 618                 }
 619                 break;
 620             default:
 621                 /* other trigger types are not supported or irrelevant */
 622                 break;
 623             }
 624         }
 625     }
 626
 627     return false;
 628 }
 629
 630 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
 631 {
 632     RISCVCPU *cpu = RISCV_CPU(cs);
 633     CPURISCVState *env = &cpu->env;
 634     target_ulong ctrl;
 635     target_ulong addr;
 636     int trigger_type;
 637     int flags;
 638     int i;
 639
 640     for (i = 0; i < RV_MAX_TRIGGERS; i++) {
 641         trigger_type = get_trigger_type(env, i);
 642
 643         switch (trigger_type) {
 644         case TRIGGER_TYPE_AD_MATCH:
 645             /* type 2 trigger cannot be fired in VU/VS mode */
 646             if (riscv_cpu_virt_enabled(env)) {
 647                 return false;
 648             }
 649
 650             ctrl = env->tdata1[i];
 651             addr = env->tdata2[i];
 652             flags = 0;
 653
 654             if (ctrl & TYPE2_LOAD) {
 655                 flags |= BP_MEM_READ;
 656             }
 657             if (ctrl & TYPE2_STORE) {
 658                 flags |= BP_MEM_WRITE;
 659             }
 660
 661             if ((wp->flags & flags) && (wp->vaddr == addr)) {
 662                 /* check U/S/M bit against current privilege level */
 663                 if ((ctrl >> 3) & BIT(env->priv)) {
 664                     return true;
 665                 }
 666             }
 667             break;
 668         case TRIGGER_TYPE_AD_MATCH6:
 669             ctrl = env->tdata1[i];
 670             addr = env->tdata2[i];
 671             flags = 0;
 672
 673             if (ctrl & TYPE6_LOAD) {
 674                 flags |= BP_MEM_READ;
 675             }
 676             if (ctrl & TYPE6_STORE) {
 677                 flags |= BP_MEM_WRITE;
 678             }
 679
 680             if ((wp->flags & flags) && (wp->vaddr == addr)) {
 681                 if (riscv_cpu_virt_enabled(env)) {
 682                     /* check VU/VS bit against current privilege level */
 683                     if ((ctrl >> 23) & BIT(env->priv)) {
 684                         return true;
 685                     }
 686                 } else {
 687                     /* check U/S/M bit against current privilege level */
 688                     if ((ctrl >> 3) & BIT(env->priv)) {
 689                         return true;
 690                     }
 691                 }
 692             }
 693             break;
 694         default:
 695             /* other trigger types are not supported */
 696             break;
 697         }
 698     }
 699
 700     return false;
 701 }
 702
 703 void riscv_trigger_init(CPURISCVState *env)
 704 {
 705     target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
 706     int i;
 707
 708     /* init to type 2 triggers */
 709     for (i = 0; i < RV_MAX_TRIGGERS; i++) {
 710         /*
 711          * type = TRIGGER_TYPE_AD_MATCH
 712          * dmode = 0 (both debug and M-mode can write tdata)
 713          * maskmax = 0 (unimplemented, always 0)
 714          * sizehi = 0 (match against any size, RV64 only)
 715          * hit = 0 (unimplemented, always 0)
 716          * select = 0 (always 0, perform match on address)
 717          * timing = 0 (always 0, trigger before instruction)
 718          * sizelo = 0 (match against any size)
 719          * action = 0 (always 0, raise a breakpoint exception)
 720          * chain = 0 (unimplemented, always 0)
 721          * match = 0 (always 0, when any compare value equals tdata2)
 722          */
 723         env->tdata1[i] = tdata1;
 724         env->tdata2[i] = 0;
 725         env->tdata3[i] = 0;
 726         env->cpu_breakpoint[i] = NULL;
 727         env->cpu_watchpoint[i] = NULL;
 728     }
 729 }