target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "qemu-common.h"
  26 #include "exec/exec-all.h"
  27 #include "hw/qdev-properties.h"
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/loader.h"
  30 #endif
  31 #include "hw/arm/arm.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/kvm.h"
  34 #include "kvm_arm.h"
  35
  36 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  37 {
  38     ARMCPU *cpu = ARM_CPU(cs);
  39
  40     cpu->env.regs[15] = value;
  41 }
  42
  43 static bool arm_cpu_has_work(CPUState *cs)
  44 {
  45     ARMCPU *cpu = ARM_CPU(cs);
  46
  47     return !cpu->powered_off
  48         && cs->interrupt_request &
  49         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  50          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  51          | CPU_INTERRUPT_EXITTB);
  52 }
  53
  54 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  55 {
  56     /* Reset a single ARMCPRegInfo register */
  57     ARMCPRegInfo *ri = value;
  58     ARMCPU *cpu = opaque;
  59
  60     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  61         return;
  62     }
  63
  64     if (ri->resetfn) {
  65         ri->resetfn(&cpu->env, ri);
  66         return;
  67     }
  68
  69     /* A zero offset is never possible as it would be regs[0]
  70      * so we use it to indicate that reset is being handled elsewhere.
  71      * This is basically only used for fields in non-core coprocessors
  72      * (like the pxa2xx ones).
  73      */
  74     if (!ri->fieldoffset) {
  75         return;
  76     }
  77
  78     if (cpreg_field_is_64bit(ri)) {
  79         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  80     } else {
  81         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  82     }
  83 }
  84
  85 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  86 {
  87     /* Purely an assertion check: we've already done reset once,
  88      * so now check that running the reset for the cpreg doesn't
  89      * change its value. This traps bugs where two different cpregs
  90      * both try to reset the same state field but to different values.
  91      */
  92     ARMCPRegInfo *ri = value;
  93     ARMCPU *cpu = opaque;
  94     uint64_t oldvalue, newvalue;
  95
  96     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
  97         return;
  98     }
  99
 100     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 101     cp_reg_reset(key, value, opaque);
 102     newvalue = read_raw_cp_reg(&cpu->env, ri);
 103     assert(oldvalue == newvalue);
 104 }
 105
 106 /* CPUClass::reset() */
 107 static void arm_cpu_reset(CPUState *s)
 108 {
 109     ARMCPU *cpu = ARM_CPU(s);
 110     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 111     CPUARMState *env = &cpu->env;
 112
 113     acc->parent_reset(s);
 114
 115     memset(env, 0, offsetof(CPUARMState, features));
 116     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 117     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 118
 119     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 120     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 121     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 122     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 123
 124     cpu->powered_off = cpu->start_powered_off;
 125     s->halted = cpu->start_powered_off;
 126
 127     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 128         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 129     }
 130
 131     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 132         /* 64 bit CPUs always start in 64 bit mode */
 133         env->aarch64 = 1;
 134 #if defined(CONFIG_USER_ONLY)
 135         env->pstate = PSTATE_MODE_EL0t;
 136         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 137         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 138         /* and to the FP/Neon instructions */
 139         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 140 #else
 141         /* Reset into the highest available EL */
 142         if (arm_feature(env, ARM_FEATURE_EL3)) {
 143             env->pstate = PSTATE_MODE_EL3h;
 144         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 145             env->pstate = PSTATE_MODE_EL2h;
 146         } else {
 147             env->pstate = PSTATE_MODE_EL1h;
 148         }
 149         env->pc = cpu->rvbar;
 150 #endif
 151     } else {
 152 #if defined(CONFIG_USER_ONLY)
 153         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 154         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 155 #endif
 156     }
 157
 158 #if defined(CONFIG_USER_ONLY)
 159     env->uncached_cpsr = ARM_CPU_MODE_USR;
 160     /* For user mode we must enable access to coprocessors */
 161     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 162     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 163         env->cp15.c15_cpar = 3;
 164     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 165         env->cp15.c15_cpar = 1;
 166     }
 167 #else
 168     /* SVC mode with interrupts disabled.  */
 169     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 170     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 171     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 172      * clear at reset. Initial SP and PC are loaded from ROM.
 173      */
 174     if (IS_M(env)) {
 175         uint32_t initial_msp; /* Loaded from 0x0 */
 176         uint32_t initial_pc; /* Loaded from 0x4 */
 177         uint8_t *rom;
 178
 179         env->daif &= ~PSTATE_I;
 180         rom = rom_ptr(0);
 181         if (rom) {
 182             /* Address zero is covered by ROM which hasn't yet been
 183              * copied into physical memory.
 184              */
 185             initial_msp = ldl_p(rom);
 186             initial_pc = ldl_p(rom + 4);
 187         } else {
 188             /* Address zero not covered by a ROM blob, or the ROM blob
 189              * is in non-modifiable memory and this is a second reset after
 190              * it got copied into memory. In the latter case, rom_ptr
 191              * will return a NULL pointer and we should use ldl_phys instead.
 192              */
 193             initial_msp = ldl_phys(s->as, 0);
 194             initial_pc = ldl_phys(s->as, 4);
 195         }
 196
 197         env->regs[13] = initial_msp & 0xFFFFFFFC;
 198         env->regs[15] = initial_pc & ~1;
 199         env->thumb = initial_pc & 1;
 200     }
 201
 202     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 203      * executing as AArch32 then check if highvecs are enabled and
 204      * adjust the PC accordingly.
 205      */
 206     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 207         env->regs[15] = 0xFFFF0000;
 208     }
 209
 210     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 211 #endif
 212     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 213     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 214     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 215     set_float_detect_tininess(float_tininess_before_rounding,
 216                               &env->vfp.fp_status);
 217     set_float_detect_tininess(float_tininess_before_rounding,
 218                               &env->vfp.standard_fp_status);
 219     tlb_flush(s, 1);
 220
 221 #ifndef CONFIG_USER_ONLY
 222     if (kvm_enabled()) {
 223         kvm_arm_reset_vcpu(cpu);
 224     }
 225 #endif
 226
 227     hw_breakpoint_update_all(cpu);
 228     hw_watchpoint_update_all(cpu);
 229 }
 230
 231 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 232 {
 233     CPUClass *cc = CPU_GET_CLASS(cs);
 234     CPUARMState *env = cs->env_ptr;
 235     uint32_t cur_el = arm_current_el(env);
 236     bool secure = arm_is_secure(env);
 237     uint32_t target_el;
 238     uint32_t excp_idx;
 239     bool ret = false;
 240
 241     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 242         excp_idx = EXCP_FIQ;
 243         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 244         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 245             cs->exception_index = excp_idx;
 246             env->exception.target_el = target_el;
 247             cc->do_interrupt(cs);
 248             ret = true;
 249         }
 250     }
 251     if (interrupt_request & CPU_INTERRUPT_HARD) {
 252         excp_idx = EXCP_IRQ;
 253         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 254         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 255             cs->exception_index = excp_idx;
 256             env->exception.target_el = target_el;
 257             cc->do_interrupt(cs);
 258             ret = true;
 259         }
 260     }
 261     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 262         excp_idx = EXCP_VIRQ;
 263         target_el = 1;
 264         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 265             cs->exception_index = excp_idx;
 266             env->exception.target_el = target_el;
 267             cc->do_interrupt(cs);
 268             ret = true;
 269         }
 270     }
 271     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 272         excp_idx = EXCP_VFIQ;
 273         target_el = 1;
 274         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 275             cs->exception_index = excp_idx;
 276             env->exception.target_el = target_el;
 277             cc->do_interrupt(cs);
 278             ret = true;
 279         }
 280     }
 281
 282     return ret;
 283 }
 284
 285 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 286 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 287 {
 288     CPUClass *cc = CPU_GET_CLASS(cs);
 289     ARMCPU *cpu = ARM_CPU(cs);
 290     CPUARMState *env = &cpu->env;
 291     bool ret = false;
 292
 293
 294     if (interrupt_request & CPU_INTERRUPT_FIQ
 295         && !(env->daif & PSTATE_F)) {
 296         cs->exception_index = EXCP_FIQ;
 297         cc->do_interrupt(cs);
 298         ret = true;
 299     }
 300     /* ARMv7-M interrupt return works by loading a magic value
 301      * into the PC.  On real hardware the load causes the
 302      * return to occur.  The qemu implementation performs the
 303      * jump normally, then does the exception return when the
 304      * CPU tries to execute code at the magic address.
 305      * This will cause the magic PC value to be pushed to
 306      * the stack if an interrupt occurred at the wrong time.
 307      * We avoid this by disabling interrupts when
 308      * pc contains a magic address.
 309      */
 310     if (interrupt_request & CPU_INTERRUPT_HARD
 311         && !(env->daif & PSTATE_I)
 312         && (env->regs[15] < 0xfffffff0)) {
 313         cs->exception_index = EXCP_IRQ;
 314         cc->do_interrupt(cs);
 315         ret = true;
 316     }
 317     return ret;
 318 }
 319 #endif
 320
 321 #ifndef CONFIG_USER_ONLY
 322 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 323 {
 324     ARMCPU *cpu = opaque;
 325     CPUARMState *env = &cpu->env;
 326     CPUState *cs = CPU(cpu);
 327     static const int mask[] = {
 328         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 329         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 330         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 331         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 332     };
 333
 334     switch (irq) {
 335     case ARM_CPU_VIRQ:
 336     case ARM_CPU_VFIQ:
 337         assert(arm_feature(env, ARM_FEATURE_EL2));
 338         /* fall through */
 339     case ARM_CPU_IRQ:
 340     case ARM_CPU_FIQ:
 341         if (level) {
 342             cpu_interrupt(cs, mask[irq]);
 343         } else {
 344             cpu_reset_interrupt(cs, mask[irq]);
 345         }
 346         break;
 347     default:
 348         g_assert_not_reached();
 349     }
 350 }
 351
 352 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 353 {
 354 #ifdef CONFIG_KVM
 355     ARMCPU *cpu = opaque;
 356     CPUState *cs = CPU(cpu);
 357     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 358
 359     switch (irq) {
 360     case ARM_CPU_IRQ:
 361         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 362         break;
 363     case ARM_CPU_FIQ:
 364         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 365         break;
 366     default:
 367         g_assert_not_reached();
 368     }
 369     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 370     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 371 #endif
 372 }
 373
 374 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 375 {
 376     ARMCPU *cpu = ARM_CPU(cs);
 377     CPUARMState *env = &cpu->env;
 378
 379     cpu_synchronize_state(cs);
 380     return arm_cpu_data_is_big_endian(env);
 381 }
 382
 383 #endif
 384
 385 static inline void set_feature(CPUARMState *env, int feature)
 386 {
 387     env->features |= 1ULL << feature;
 388 }
 389
 390 static inline void unset_feature(CPUARMState *env, int feature)
 391 {
 392     env->features &= ~(1ULL << feature);
 393 }
 394
 395 static int
 396 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 397 {
 398   return print_insn_arm(pc | 1, info);
 399 }
 400
 401 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 402 {
 403     ARMCPU *ac = ARM_CPU(cpu);
 404     CPUARMState *env = &ac->env;
 405
 406     if (is_a64(env)) {
 407         /* We might not be compiled with the A64 disassembler
 408          * because it needs a C++ compiler. Leave print_insn
 409          * unset in this case to use the caller default behaviour.
 410          */
 411 #if defined(CONFIG_ARM_A64_DIS)
 412         info->print_insn = print_insn_arm_a64;
 413 #endif
 414     } else if (env->thumb) {
 415         info->print_insn = print_insn_thumb1;
 416     } else {
 417         info->print_insn = print_insn_arm;
 418     }
 419     if (bswap_code(arm_sctlr_b(env))) {
 420 #ifdef TARGET_WORDS_BIGENDIAN
 421         info->endian = BFD_ENDIAN_LITTLE;
 422 #else
 423         info->endian = BFD_ENDIAN_BIG;
 424 #endif
 425     }
 426 }
 427
 428 #define ARM_CPUS_PER_CLUSTER 8
 429
 430 static void arm_cpu_initfn(Object *obj)
 431 {
 432     CPUState *cs = CPU(obj);
 433     ARMCPU *cpu = ARM_CPU(obj);
 434     static bool inited;
 435     uint32_t Aff1, Aff0;
 436
 437     cs->env_ptr = &cpu->env;
 438     cpu_exec_init(cs, &error_abort);
 439     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 440                                          g_free, g_free);
 441
 442     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 443      * We don't support setting cluster ID ([16..23]) (known as Aff2
 444      * in later ARM ARM versions), or any of the higher affinity level fields,
 445      * so these bits always RAZ.
 446      */
 447     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 448     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 449     cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 450
 451 #ifndef CONFIG_USER_ONLY
 452     /* Our inbound IRQ and FIQ lines */
 453     if (kvm_enabled()) {
 454         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 455          * the same interface as non-KVM CPUs.
 456          */
 457         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 458     } else {
 459         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 460     }
 461
 462     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 463                                                 arm_gt_ptimer_cb, cpu);
 464     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 465                                                 arm_gt_vtimer_cb, cpu);
 466     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 467                                                 arm_gt_htimer_cb, cpu);
 468     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 469                                                 arm_gt_stimer_cb, cpu);
 470     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 471                        ARRAY_SIZE(cpu->gt_timer_outputs));
 472 #endif
 473
 474     /* DTB consumers generally don't in fact care what the 'compatible'
 475      * string is, so always provide some string and trust that a hypothetical
 476      * picky DTB consumer will also provide a helpful error message.
 477      */
 478     cpu->dtb_compatible = "qemu,unknown";
 479     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 480     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 481
 482     if (tcg_enabled()) {
 483         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 484         if (!inited) {
 485             inited = true;
 486             arm_translate_init();
 487         }
 488     }
 489 }
 490
 491 static Property arm_cpu_reset_cbar_property =
 492             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 493
 494 static Property arm_cpu_reset_hivecs_property =
 495             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 496
 497 static Property arm_cpu_rvbar_property =
 498             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 499
 500 static Property arm_cpu_has_el3_property =
 501             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 502
 503 static Property arm_cpu_has_mpu_property =
 504             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 505
 506 static Property arm_cpu_pmsav7_dregion_property =
 507             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 508
 509 static void arm_cpu_post_init(Object *obj)
 510 {
 511     ARMCPU *cpu = ARM_CPU(obj);
 512
 513     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 514         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 515         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 516                                  &error_abort);
 517     }
 518
 519     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 520         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 521                                  &error_abort);
 522     }
 523
 524     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 525         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 526                                  &error_abort);
 527     }
 528
 529     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 530         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 531          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 532          */
 533         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 534                                  &error_abort);
 535
 536 #ifndef CONFIG_USER_ONLY
 537         object_property_add_link(obj, "secure-memory",
 538                                  TYPE_MEMORY_REGION,
 539                                  (Object **)&cpu->secure_memory,
 540                                  qdev_prop_allow_set_link_before_realize,
 541                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 542                                  &error_abort);
 543 #endif
 544     }
 545
 546     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 547         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 548                                  &error_abort);
 549         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 550             qdev_property_add_static(DEVICE(obj),
 551                                      &arm_cpu_pmsav7_dregion_property,
 552                                      &error_abort);
 553         }
 554     }
 555
 556 }
 557
 558 static void arm_cpu_finalizefn(Object *obj)
 559 {
 560     ARMCPU *cpu = ARM_CPU(obj);
 561     g_hash_table_destroy(cpu->cp_regs);
 562 }
 563
 564 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 565 {
 566     CPUState *cs = CPU(dev);
 567     ARMCPU *cpu = ARM_CPU(dev);
 568     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 569     CPUARMState *env = &cpu->env;
 570
 571     /* Some features automatically imply others: */
 572     if (arm_feature(env, ARM_FEATURE_V8)) {
 573         set_feature(env, ARM_FEATURE_V7);
 574         set_feature(env, ARM_FEATURE_ARM_DIV);
 575         set_feature(env, ARM_FEATURE_LPAE);
 576     }
 577     if (arm_feature(env, ARM_FEATURE_V7)) {
 578         set_feature(env, ARM_FEATURE_VAPA);
 579         set_feature(env, ARM_FEATURE_THUMB2);
 580         set_feature(env, ARM_FEATURE_MPIDR);
 581         if (!arm_feature(env, ARM_FEATURE_M)) {
 582             set_feature(env, ARM_FEATURE_V6K);
 583         } else {
 584             set_feature(env, ARM_FEATURE_V6);
 585         }
 586     }
 587     if (arm_feature(env, ARM_FEATURE_V6K)) {
 588         set_feature(env, ARM_FEATURE_V6);
 589         set_feature(env, ARM_FEATURE_MVFR);
 590     }
 591     if (arm_feature(env, ARM_FEATURE_V6)) {
 592         set_feature(env, ARM_FEATURE_V5);
 593         if (!arm_feature(env, ARM_FEATURE_M)) {
 594             set_feature(env, ARM_FEATURE_AUXCR);
 595         }
 596     }
 597     if (arm_feature(env, ARM_FEATURE_V5)) {
 598         set_feature(env, ARM_FEATURE_V4T);
 599     }
 600     if (arm_feature(env, ARM_FEATURE_M)) {
 601         set_feature(env, ARM_FEATURE_THUMB_DIV);
 602     }
 603     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 604         set_feature(env, ARM_FEATURE_THUMB_DIV);
 605     }
 606     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 607         set_feature(env, ARM_FEATURE_VFP3);
 608         set_feature(env, ARM_FEATURE_VFP_FP16);
 609     }
 610     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 611         set_feature(env, ARM_FEATURE_VFP);
 612     }
 613     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 614         set_feature(env, ARM_FEATURE_V7MP);
 615         set_feature(env, ARM_FEATURE_PXN);
 616     }
 617     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 618         set_feature(env, ARM_FEATURE_CBAR);
 619     }
 620     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 621         !arm_feature(env, ARM_FEATURE_M)) {
 622         set_feature(env, ARM_FEATURE_THUMB_DSP);
 623     }
 624
 625     if (cpu->reset_hivecs) {
 626             cpu->reset_sctlr |= (1 << 13);
 627     }
 628
 629     if (!cpu->has_el3) {
 630         /* If the has_el3 CPU property is disabled then we need to disable the
 631          * feature.
 632          */
 633         unset_feature(env, ARM_FEATURE_EL3);
 634
 635         /* Disable the security extension feature bits in the processor feature
 636          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 637          */
 638         cpu->id_pfr1 &= ~0xf0;
 639         cpu->id_aa64pfr0 &= ~0xf000;
 640     }
 641
 642     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 643         /* Disable the hypervisor feature bits in the processor feature
 644          * registers if we don't have EL2. These are id_pfr1[15:12] and
 645          * id_aa64pfr0_el1[11:8].
 646          */
 647         cpu->id_aa64pfr0 &= ~0xf00;
 648         cpu->id_pfr1 &= ~0xf000;
 649     }
 650
 651     if (!cpu->has_mpu) {
 652         unset_feature(env, ARM_FEATURE_MPU);
 653     }
 654
 655     if (arm_feature(env, ARM_FEATURE_MPU) &&
 656         arm_feature(env, ARM_FEATURE_V7)) {
 657         uint32_t nr = cpu->pmsav7_dregion;
 658
 659         if (nr > 0xff) {
 660             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 661             return;
 662         }
 663
 664         if (nr) {
 665             env->pmsav7.drbar = g_new0(uint32_t, nr);
 666             env->pmsav7.drsr = g_new0(uint32_t, nr);
 667             env->pmsav7.dracr = g_new0(uint32_t, nr);
 668         }
 669     }
 670
 671     register_cp_regs_for_features(cpu);
 672     arm_cpu_register_gdb_regs_for_features(cpu);
 673
 674     init_cpreg_list(cpu);
 675
 676 #ifndef CONFIG_USER_ONLY
 677     if (cpu->has_el3) {
 678         cs->num_ases = 2;
 679     } else {
 680         cs->num_ases = 1;
 681     }
 682
 683     if (cpu->has_el3) {
 684         AddressSpace *as;
 685
 686         if (!cpu->secure_memory) {
 687             cpu->secure_memory = cs->memory;
 688         }
 689         as = address_space_init_shareable(cpu->secure_memory,
 690                                           "cpu-secure-memory");
 691         cpu_address_space_init(cs, as, ARMASIdx_S);
 692     }
 693     cpu_address_space_init(cs,
 694                            address_space_init_shareable(cs->memory,
 695                                                         "cpu-memory"),
 696                            ARMASIdx_NS);
 697 #endif
 698
 699     qemu_init_vcpu(cs);
 700     cpu_reset(cs);
 701
 702     acc->parent_realize(dev, errp);
 703 }
 704
 705 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 706 {
 707     ObjectClass *oc;
 708     char *typename;
 709     char **cpuname;
 710
 711     if (!cpu_model) {
 712         return NULL;
 713     }
 714
 715     cpuname = g_strsplit(cpu_model, ",", 1);
 716     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 717     oc = object_class_by_name(typename);
 718     g_strfreev(cpuname);
 719     g_free(typename);
 720     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 721         object_class_is_abstract(oc)) {
 722         return NULL;
 723     }
 724     return oc;
 725 }
 726
 727 /* CPU models. These are not needed for the AArch64 linux-user build. */
 728 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 729
 730 static void arm926_initfn(Object *obj)
 731 {
 732     ARMCPU *cpu = ARM_CPU(obj);
 733
 734     cpu->dtb_compatible = "arm,arm926";
 735     set_feature(&cpu->env, ARM_FEATURE_V5);
 736     set_feature(&cpu->env, ARM_FEATURE_VFP);
 737     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 738     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 739     cpu->midr = 0x41069265;
 740     cpu->reset_fpsid = 0x41011090;
 741     cpu->ctr = 0x1dd20d2;
 742     cpu->reset_sctlr = 0x00090078;
 743 }
 744
 745 static void arm946_initfn(Object *obj)
 746 {
 747     ARMCPU *cpu = ARM_CPU(obj);
 748
 749     cpu->dtb_compatible = "arm,arm946";
 750     set_feature(&cpu->env, ARM_FEATURE_V5);
 751     set_feature(&cpu->env, ARM_FEATURE_MPU);
 752     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 753     cpu->midr = 0x41059461;
 754     cpu->ctr = 0x0f004006;
 755     cpu->reset_sctlr = 0x00000078;
 756 }
 757
 758 static void arm1026_initfn(Object *obj)
 759 {
 760     ARMCPU *cpu = ARM_CPU(obj);
 761
 762     cpu->dtb_compatible = "arm,arm1026";
 763     set_feature(&cpu->env, ARM_FEATURE_V5);
 764     set_feature(&cpu->env, ARM_FEATURE_VFP);
 765     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 766     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 767     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 768     cpu->midr = 0x4106a262;
 769     cpu->reset_fpsid = 0x410110a0;
 770     cpu->ctr = 0x1dd20d2;
 771     cpu->reset_sctlr = 0x00090078;
 772     cpu->reset_auxcr = 1;
 773     {
 774         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 775         ARMCPRegInfo ifar = {
 776             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 777             .access = PL1_RW,
 778             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 779             .resetvalue = 0
 780         };
 781         define_one_arm_cp_reg(cpu, &ifar);
 782     }
 783 }
 784
 785 static void arm1136_r2_initfn(Object *obj)
 786 {
 787     ARMCPU *cpu = ARM_CPU(obj);
 788     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 789      * older core than plain "arm1136". In particular this does not
 790      * have the v6K features.
 791      * These ID register values are correct for 1136 but may be wrong
 792      * for 1136_r2 (in particular r0p2 does not actually implement most
 793      * of the ID registers).
 794      */
 795
 796     cpu->dtb_compatible = "arm,arm1136";
 797     set_feature(&cpu->env, ARM_FEATURE_V6);
 798     set_feature(&cpu->env, ARM_FEATURE_VFP);
 799     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 800     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 801     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 802     cpu->midr = 0x4107b362;
 803     cpu->reset_fpsid = 0x410120b4;
 804     cpu->mvfr0 = 0x11111111;
 805     cpu->mvfr1 = 0x00000000;
 806     cpu->ctr = 0x1dd20d2;
 807     cpu->reset_sctlr = 0x00050078;
 808     cpu->id_pfr0 = 0x111;
 809     cpu->id_pfr1 = 0x1;
 810     cpu->id_dfr0 = 0x2;
 811     cpu->id_afr0 = 0x3;
 812     cpu->id_mmfr0 = 0x01130003;
 813     cpu->id_mmfr1 = 0x10030302;
 814     cpu->id_mmfr2 = 0x01222110;
 815     cpu->id_isar0 = 0x00140011;
 816     cpu->id_isar1 = 0x12002111;
 817     cpu->id_isar2 = 0x11231111;
 818     cpu->id_isar3 = 0x01102131;
 819     cpu->id_isar4 = 0x141;
 820     cpu->reset_auxcr = 7;
 821 }
 822
 823 static void arm1136_initfn(Object *obj)
 824 {
 825     ARMCPU *cpu = ARM_CPU(obj);
 826
 827     cpu->dtb_compatible = "arm,arm1136";
 828     set_feature(&cpu->env, ARM_FEATURE_V6K);
 829     set_feature(&cpu->env, ARM_FEATURE_V6);
 830     set_feature(&cpu->env, ARM_FEATURE_VFP);
 831     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 832     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 833     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 834     cpu->midr = 0x4117b363;
 835     cpu->reset_fpsid = 0x410120b4;
 836     cpu->mvfr0 = 0x11111111;
 837     cpu->mvfr1 = 0x00000000;
 838     cpu->ctr = 0x1dd20d2;
 839     cpu->reset_sctlr = 0x00050078;
 840     cpu->id_pfr0 = 0x111;
 841     cpu->id_pfr1 = 0x1;
 842     cpu->id_dfr0 = 0x2;
 843     cpu->id_afr0 = 0x3;
 844     cpu->id_mmfr0 = 0x01130003;
 845     cpu->id_mmfr1 = 0x10030302;
 846     cpu->id_mmfr2 = 0x01222110;
 847     cpu->id_isar0 = 0x00140011;
 848     cpu->id_isar1 = 0x12002111;
 849     cpu->id_isar2 = 0x11231111;
 850     cpu->id_isar3 = 0x01102131;
 851     cpu->id_isar4 = 0x141;
 852     cpu->reset_auxcr = 7;
 853 }
 854
 855 static void arm1176_initfn(Object *obj)
 856 {
 857     ARMCPU *cpu = ARM_CPU(obj);
 858
 859     cpu->dtb_compatible = "arm,arm1176";
 860     set_feature(&cpu->env, ARM_FEATURE_V6K);
 861     set_feature(&cpu->env, ARM_FEATURE_VFP);
 862     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 863     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 864     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 865     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 866     set_feature(&cpu->env, ARM_FEATURE_EL3);
 867     cpu->midr = 0x410fb767;
 868     cpu->reset_fpsid = 0x410120b5;
 869     cpu->mvfr0 = 0x11111111;
 870     cpu->mvfr1 = 0x00000000;
 871     cpu->ctr = 0x1dd20d2;
 872     cpu->reset_sctlr = 0x00050078;
 873     cpu->id_pfr0 = 0x111;
 874     cpu->id_pfr1 = 0x11;
 875     cpu->id_dfr0 = 0x33;
 876     cpu->id_afr0 = 0;
 877     cpu->id_mmfr0 = 0x01130003;
 878     cpu->id_mmfr1 = 0x10030302;
 879     cpu->id_mmfr2 = 0x01222100;
 880     cpu->id_isar0 = 0x0140011;
 881     cpu->id_isar1 = 0x12002111;
 882     cpu->id_isar2 = 0x11231121;
 883     cpu->id_isar3 = 0x01102131;
 884     cpu->id_isar4 = 0x01141;
 885     cpu->reset_auxcr = 7;
 886 }
 887
 888 static void arm11mpcore_initfn(Object *obj)
 889 {
 890     ARMCPU *cpu = ARM_CPU(obj);
 891
 892     cpu->dtb_compatible = "arm,arm11mpcore";
 893     set_feature(&cpu->env, ARM_FEATURE_V6K);
 894     set_feature(&cpu->env, ARM_FEATURE_VFP);
 895     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 896     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 897     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 898     cpu->midr = 0x410fb022;
 899     cpu->reset_fpsid = 0x410120b4;
 900     cpu->mvfr0 = 0x11111111;
 901     cpu->mvfr1 = 0x00000000;
 902     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 903     cpu->id_pfr0 = 0x111;
 904     cpu->id_pfr1 = 0x1;
 905     cpu->id_dfr0 = 0;
 906     cpu->id_afr0 = 0x2;
 907     cpu->id_mmfr0 = 0x01100103;
 908     cpu->id_mmfr1 = 0x10020302;
 909     cpu->id_mmfr2 = 0x01222000;
 910     cpu->id_isar0 = 0x00100011;
 911     cpu->id_isar1 = 0x12002111;
 912     cpu->id_isar2 = 0x11221011;
 913     cpu->id_isar3 = 0x01102131;
 914     cpu->id_isar4 = 0x141;
 915     cpu->reset_auxcr = 1;
 916 }
 917
 918 static void cortex_m3_initfn(Object *obj)
 919 {
 920     ARMCPU *cpu = ARM_CPU(obj);
 921     set_feature(&cpu->env, ARM_FEATURE_V7);
 922     set_feature(&cpu->env, ARM_FEATURE_M);
 923     cpu->midr = 0x410fc231;
 924 }
 925
 926 static void cortex_m4_initfn(Object *obj)
 927 {
 928     ARMCPU *cpu = ARM_CPU(obj);
 929
 930     set_feature(&cpu->env, ARM_FEATURE_V7);
 931     set_feature(&cpu->env, ARM_FEATURE_M);
 932     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 933     cpu->midr = 0x410fc240; /* r0p0 */
 934 }
 935 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 936 {
 937     CPUClass *cc = CPU_CLASS(oc);
 938
 939 #ifndef CONFIG_USER_ONLY
 940     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 941 #endif
 942
 943     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 944 }
 945
 946 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 947     /* Dummy the TCM region regs for the moment */
 948     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 949       .access = PL1_RW, .type = ARM_CP_CONST },
 950     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 951       .access = PL1_RW, .type = ARM_CP_CONST },
 952     REGINFO_SENTINEL
 953 };
 954
 955 static void cortex_r5_initfn(Object *obj)
 956 {
 957     ARMCPU *cpu = ARM_CPU(obj);
 958
 959     set_feature(&cpu->env, ARM_FEATURE_V7);
 960     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 961     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 962     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 963     set_feature(&cpu->env, ARM_FEATURE_MPU);
 964     cpu->midr = 0x411fc153; /* r1p3 */
 965     cpu->id_pfr0 = 0x0131;
 966     cpu->id_pfr1 = 0x001;
 967     cpu->id_dfr0 = 0x010400;
 968     cpu->id_afr0 = 0x0;
 969     cpu->id_mmfr0 = 0x0210030;
 970     cpu->id_mmfr1 = 0x00000000;
 971     cpu->id_mmfr2 = 0x01200000;
 972     cpu->id_mmfr3 = 0x0211;
 973     cpu->id_isar0 = 0x2101111;
 974     cpu->id_isar1 = 0x13112111;
 975     cpu->id_isar2 = 0x21232141;
 976     cpu->id_isar3 = 0x01112131;
 977     cpu->id_isar4 = 0x0010142;
 978     cpu->id_isar5 = 0x0;
 979     cpu->mp_is_up = true;
 980     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 981 }
 982
 983 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 984     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 985       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 986     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 987       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 988     REGINFO_SENTINEL
 989 };
 990
 991 static void cortex_a8_initfn(Object *obj)
 992 {
 993     ARMCPU *cpu = ARM_CPU(obj);
 994
 995     cpu->dtb_compatible = "arm,cortex-a8";
 996     set_feature(&cpu->env, ARM_FEATURE_V7);
 997     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 998     set_feature(&cpu->env, ARM_FEATURE_NEON);
 999     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1000     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1001     set_feature(&cpu->env, ARM_FEATURE_EL3);
1002     cpu->midr = 0x410fc080;
1003     cpu->reset_fpsid = 0x410330c0;
1004     cpu->mvfr0 = 0x11110222;
1005     cpu->mvfr1 = 0x00011100;
1006     cpu->ctr = 0x82048004;
1007     cpu->reset_sctlr = 0x00c50078;
1008     cpu->id_pfr0 = 0x1031;
1009     cpu->id_pfr1 = 0x11;
1010     cpu->id_dfr0 = 0x400;
1011     cpu->id_afr0 = 0;
1012     cpu->id_mmfr0 = 0x31100003;
1013     cpu->id_mmfr1 = 0x20000000;
1014     cpu->id_mmfr2 = 0x01202000;
1015     cpu->id_mmfr3 = 0x11;
1016     cpu->id_isar0 = 0x00101111;
1017     cpu->id_isar1 = 0x12112111;
1018     cpu->id_isar2 = 0x21232031;
1019     cpu->id_isar3 = 0x11112131;
1020     cpu->id_isar4 = 0x00111142;
1021     cpu->dbgdidr = 0x15141000;
1022     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1023     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1024     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1025     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1026     cpu->reset_auxcr = 2;
1027     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1028 }
1029
1030 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1031     /* power_control should be set to maximum latency. Again,
1032      * default to 0 and set by private hook
1033      */
1034     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1035       .access = PL1_RW, .resetvalue = 0,
1036       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1037     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1038       .access = PL1_RW, .resetvalue = 0,
1039       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1040     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1041       .access = PL1_RW, .resetvalue = 0,
1042       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1043     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1044       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1045     /* TLB lockdown control */
1046     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1047       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1048     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1049       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1050     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1051       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1052     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1053       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1054     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1055       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1056     REGINFO_SENTINEL
1057 };
1058
1059 static void cortex_a9_initfn(Object *obj)
1060 {
1061     ARMCPU *cpu = ARM_CPU(obj);
1062
1063     cpu->dtb_compatible = "arm,cortex-a9";
1064     set_feature(&cpu->env, ARM_FEATURE_V7);
1065     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1066     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1067     set_feature(&cpu->env, ARM_FEATURE_NEON);
1068     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1069     set_feature(&cpu->env, ARM_FEATURE_EL3);
1070     /* Note that A9 supports the MP extensions even for
1071      * A9UP and single-core A9MP (which are both different
1072      * and valid configurations; we don't model A9UP).
1073      */
1074     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1075     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1076     cpu->midr = 0x410fc090;
1077     cpu->reset_fpsid = 0x41033090;
1078     cpu->mvfr0 = 0x11110222;
1079     cpu->mvfr1 = 0x01111111;
1080     cpu->ctr = 0x80038003;
1081     cpu->reset_sctlr = 0x00c50078;
1082     cpu->id_pfr0 = 0x1031;
1083     cpu->id_pfr1 = 0x11;
1084     cpu->id_dfr0 = 0x000;
1085     cpu->id_afr0 = 0;
1086     cpu->id_mmfr0 = 0x00100103;
1087     cpu->id_mmfr1 = 0x20000000;
1088     cpu->id_mmfr2 = 0x01230000;
1089     cpu->id_mmfr3 = 0x00002111;
1090     cpu->id_isar0 = 0x00101111;
1091     cpu->id_isar1 = 0x13112111;
1092     cpu->id_isar2 = 0x21232041;
1093     cpu->id_isar3 = 0x11112131;
1094     cpu->id_isar4 = 0x00111142;
1095     cpu->dbgdidr = 0x35141000;
1096     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1097     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1098     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1099     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1100 }
1101
1102 #ifndef CONFIG_USER_ONLY
1103 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1104 {
1105     /* Linux wants the number of processors from here.
1106      * Might as well set the interrupt-controller bit too.
1107      */
1108     return ((smp_cpus - 1) << 24) | (1 << 23);
1109 }
1110 #endif
1111
1112 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1113 #ifndef CONFIG_USER_ONLY
1114     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1115       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1116       .writefn = arm_cp_write_ignore, },
1117 #endif
1118     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1119       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1120     REGINFO_SENTINEL
1121 };
1122
1123 static void cortex_a15_initfn(Object *obj)
1124 {
1125     ARMCPU *cpu = ARM_CPU(obj);
1126
1127     cpu->dtb_compatible = "arm,cortex-a15";
1128     set_feature(&cpu->env, ARM_FEATURE_V7);
1129     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1130     set_feature(&cpu->env, ARM_FEATURE_NEON);
1131     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1132     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1133     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1134     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1135     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1136     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1137     set_feature(&cpu->env, ARM_FEATURE_EL3);
1138     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1139     cpu->midr = 0x412fc0f1;
1140     cpu->reset_fpsid = 0x410430f0;
1141     cpu->mvfr0 = 0x10110222;
1142     cpu->mvfr1 = 0x11111111;
1143     cpu->ctr = 0x8444c004;
1144     cpu->reset_sctlr = 0x00c50078;
1145     cpu->id_pfr0 = 0x00001131;
1146     cpu->id_pfr1 = 0x00011011;
1147     cpu->id_dfr0 = 0x02010555;
1148     cpu->pmceid0 = 0x0000000;
1149     cpu->pmceid1 = 0x00000000;
1150     cpu->id_afr0 = 0x00000000;
1151     cpu->id_mmfr0 = 0x10201105;
1152     cpu->id_mmfr1 = 0x20000000;
1153     cpu->id_mmfr2 = 0x01240000;
1154     cpu->id_mmfr3 = 0x02102211;
1155     cpu->id_isar0 = 0x02101110;
1156     cpu->id_isar1 = 0x13112111;
1157     cpu->id_isar2 = 0x21232041;
1158     cpu->id_isar3 = 0x11112131;
1159     cpu->id_isar4 = 0x10011142;
1160     cpu->dbgdidr = 0x3515f021;
1161     cpu->clidr = 0x0a200023;
1162     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1163     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1164     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1165     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1166 }
1167
1168 static void ti925t_initfn(Object *obj)
1169 {
1170     ARMCPU *cpu = ARM_CPU(obj);
1171     set_feature(&cpu->env, ARM_FEATURE_V4T);
1172     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1173     cpu->midr = ARM_CPUID_TI925T;
1174     cpu->ctr = 0x5109149;
1175     cpu->reset_sctlr = 0x00000070;
1176 }
1177
1178 static void sa1100_initfn(Object *obj)
1179 {
1180     ARMCPU *cpu = ARM_CPU(obj);
1181
1182     cpu->dtb_compatible = "intel,sa1100";
1183     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1184     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1185     cpu->midr = 0x4401A11B;
1186     cpu->reset_sctlr = 0x00000070;
1187 }
1188
1189 static void sa1110_initfn(Object *obj)
1190 {
1191     ARMCPU *cpu = ARM_CPU(obj);
1192     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1193     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1194     cpu->midr = 0x6901B119;
1195     cpu->reset_sctlr = 0x00000070;
1196 }
1197
1198 static void pxa250_initfn(Object *obj)
1199 {
1200     ARMCPU *cpu = ARM_CPU(obj);
1201
1202     cpu->dtb_compatible = "marvell,xscale";
1203     set_feature(&cpu->env, ARM_FEATURE_V5);
1204     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1205     cpu->midr = 0x69052100;
1206     cpu->ctr = 0xd172172;
1207     cpu->reset_sctlr = 0x00000078;
1208 }
1209
1210 static void pxa255_initfn(Object *obj)
1211 {
1212     ARMCPU *cpu = ARM_CPU(obj);
1213
1214     cpu->dtb_compatible = "marvell,xscale";
1215     set_feature(&cpu->env, ARM_FEATURE_V5);
1216     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1217     cpu->midr = 0x69052d00;
1218     cpu->ctr = 0xd172172;
1219     cpu->reset_sctlr = 0x00000078;
1220 }
1221
1222 static void pxa260_initfn(Object *obj)
1223 {
1224     ARMCPU *cpu = ARM_CPU(obj);
1225
1226     cpu->dtb_compatible = "marvell,xscale";
1227     set_feature(&cpu->env, ARM_FEATURE_V5);
1228     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1229     cpu->midr = 0x69052903;
1230     cpu->ctr = 0xd172172;
1231     cpu->reset_sctlr = 0x00000078;
1232 }
1233
1234 static void pxa261_initfn(Object *obj)
1235 {
1236     ARMCPU *cpu = ARM_CPU(obj);
1237
1238     cpu->dtb_compatible = "marvell,xscale";
1239     set_feature(&cpu->env, ARM_FEATURE_V5);
1240     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1241     cpu->midr = 0x69052d05;
1242     cpu->ctr = 0xd172172;
1243     cpu->reset_sctlr = 0x00000078;
1244 }
1245
1246 static void pxa262_initfn(Object *obj)
1247 {
1248     ARMCPU *cpu = ARM_CPU(obj);
1249
1250     cpu->dtb_compatible = "marvell,xscale";
1251     set_feature(&cpu->env, ARM_FEATURE_V5);
1252     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1253     cpu->midr = 0x69052d06;
1254     cpu->ctr = 0xd172172;
1255     cpu->reset_sctlr = 0x00000078;
1256 }
1257
1258 static void pxa270a0_initfn(Object *obj)
1259 {
1260     ARMCPU *cpu = ARM_CPU(obj);
1261
1262     cpu->dtb_compatible = "marvell,xscale";
1263     set_feature(&cpu->env, ARM_FEATURE_V5);
1264     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1265     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1266     cpu->midr = 0x69054110;
1267     cpu->ctr = 0xd172172;
1268     cpu->reset_sctlr = 0x00000078;
1269 }
1270
1271 static void pxa270a1_initfn(Object *obj)
1272 {
1273     ARMCPU *cpu = ARM_CPU(obj);
1274
1275     cpu->dtb_compatible = "marvell,xscale";
1276     set_feature(&cpu->env, ARM_FEATURE_V5);
1277     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1278     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1279     cpu->midr = 0x69054111;
1280     cpu->ctr = 0xd172172;
1281     cpu->reset_sctlr = 0x00000078;
1282 }
1283
1284 static void pxa270b0_initfn(Object *obj)
1285 {
1286     ARMCPU *cpu = ARM_CPU(obj);
1287
1288     cpu->dtb_compatible = "marvell,xscale";
1289     set_feature(&cpu->env, ARM_FEATURE_V5);
1290     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1291     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1292     cpu->midr = 0x69054112;
1293     cpu->ctr = 0xd172172;
1294     cpu->reset_sctlr = 0x00000078;
1295 }
1296
1297 static void pxa270b1_initfn(Object *obj)
1298 {
1299     ARMCPU *cpu = ARM_CPU(obj);
1300
1301     cpu->dtb_compatible = "marvell,xscale";
1302     set_feature(&cpu->env, ARM_FEATURE_V5);
1303     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1304     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1305     cpu->midr = 0x69054113;
1306     cpu->ctr = 0xd172172;
1307     cpu->reset_sctlr = 0x00000078;
1308 }
1309
1310 static void pxa270c0_initfn(Object *obj)
1311 {
1312     ARMCPU *cpu = ARM_CPU(obj);
1313
1314     cpu->dtb_compatible = "marvell,xscale";
1315     set_feature(&cpu->env, ARM_FEATURE_V5);
1316     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1317     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1318     cpu->midr = 0x69054114;
1319     cpu->ctr = 0xd172172;
1320     cpu->reset_sctlr = 0x00000078;
1321 }
1322
1323 static void pxa270c5_initfn(Object *obj)
1324 {
1325     ARMCPU *cpu = ARM_CPU(obj);
1326
1327     cpu->dtb_compatible = "marvell,xscale";
1328     set_feature(&cpu->env, ARM_FEATURE_V5);
1329     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1330     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1331     cpu->midr = 0x69054117;
1332     cpu->ctr = 0xd172172;
1333     cpu->reset_sctlr = 0x00000078;
1334 }
1335
1336 #ifdef CONFIG_USER_ONLY
1337 static void arm_any_initfn(Object *obj)
1338 {
1339     ARMCPU *cpu = ARM_CPU(obj);
1340     set_feature(&cpu->env, ARM_FEATURE_V8);
1341     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1342     set_feature(&cpu->env, ARM_FEATURE_NEON);
1343     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1344     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1345     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1346     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1347     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1348     set_feature(&cpu->env, ARM_FEATURE_CRC);
1349     cpu->midr = 0xffffffff;
1350 }
1351 #endif
1352
1353 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1354
1355 typedef struct ARMCPUInfo {
1356     const char *name;
1357     void (*initfn)(Object *obj);
1358     void (*class_init)(ObjectClass *oc, void *data);
1359 } ARMCPUInfo;
1360
1361 static const ARMCPUInfo arm_cpus[] = {
1362 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1363     { .name = "arm926",      .initfn = arm926_initfn },
1364     { .name = "arm946",      .initfn = arm946_initfn },
1365     { .name = "arm1026",     .initfn = arm1026_initfn },
1366     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1367      * older core than plain "arm1136". In particular this does not
1368      * have the v6K features.
1369      */
1370     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1371     { .name = "arm1136",     .initfn = arm1136_initfn },
1372     { .name = "arm1176",     .initfn = arm1176_initfn },
1373     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1374     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1375                              .class_init = arm_v7m_class_init },
1376     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1377                              .class_init = arm_v7m_class_init },
1378     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1379     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1380     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1381     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1382     { .name = "ti925t",      .initfn = ti925t_initfn },
1383     { .name = "sa1100",      .initfn = sa1100_initfn },
1384     { .name = "sa1110",      .initfn = sa1110_initfn },
1385     { .name = "pxa250",      .initfn = pxa250_initfn },
1386     { .name = "pxa255",      .initfn = pxa255_initfn },
1387     { .name = "pxa260",      .initfn = pxa260_initfn },
1388     { .name = "pxa261",      .initfn = pxa261_initfn },
1389     { .name = "pxa262",      .initfn = pxa262_initfn },
1390     /* "pxa270" is an alias for "pxa270-a0" */
1391     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1392     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1393     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1394     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1395     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1396     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1397     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1398 #ifdef CONFIG_USER_ONLY
1399     { .name = "any",         .initfn = arm_any_initfn },
1400 #endif
1401 #endif
1402     { .name = NULL }
1403 };
1404
1405 static Property arm_cpu_properties[] = {
1406     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1407     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1408     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1409     DEFINE_PROP_END_OF_LIST()
1410 };
1411
1412 #ifdef CONFIG_USER_ONLY
1413 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1414                                     int mmu_idx)
1415 {
1416     ARMCPU *cpu = ARM_CPU(cs);
1417     CPUARMState *env = &cpu->env;
1418
1419     env->exception.vaddress = address;
1420     if (rw == 2) {
1421         cs->exception_index = EXCP_PREFETCH_ABORT;
1422     } else {
1423         cs->exception_index = EXCP_DATA_ABORT;
1424     }
1425     return 1;
1426 }
1427 #endif
1428
1429 static gchar *arm_gdb_arch_name(CPUState *cs)
1430 {
1431     ARMCPU *cpu = ARM_CPU(cs);
1432     CPUARMState *env = &cpu->env;
1433
1434     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1435         return g_strdup("iwmmxt");
1436     }
1437     return g_strdup("arm");
1438 }
1439
1440 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1441 {
1442     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1443     CPUClass *cc = CPU_CLASS(acc);
1444     DeviceClass *dc = DEVICE_CLASS(oc);
1445
1446     acc->parent_realize = dc->realize;
1447     dc->realize = arm_cpu_realizefn;
1448     dc->props = arm_cpu_properties;
1449
1450     acc->parent_reset = cc->reset;
1451     cc->reset = arm_cpu_reset;
1452
1453     cc->class_by_name = arm_cpu_class_by_name;
1454     cc->has_work = arm_cpu_has_work;
1455     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1456     cc->dump_state = arm_cpu_dump_state;
1457     cc->set_pc = arm_cpu_set_pc;
1458     cc->gdb_read_register = arm_cpu_gdb_read_register;
1459     cc->gdb_write_register = arm_cpu_gdb_write_register;
1460 #ifdef CONFIG_USER_ONLY
1461     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1462 #else
1463     cc->do_interrupt = arm_cpu_do_interrupt;
1464     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1465     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1466     cc->asidx_from_attrs = arm_asidx_from_attrs;
1467     cc->vmsd = &vmstate_arm_cpu;
1468     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1469     cc->write_elf64_note = arm_cpu_write_elf64_note;
1470     cc->write_elf32_note = arm_cpu_write_elf32_note;
1471 #endif
1472     cc->gdb_num_core_regs = 26;
1473     cc->gdb_core_xml_file = "arm-core.xml";
1474     cc->gdb_arch_name = arm_gdb_arch_name;
1475     cc->gdb_stop_before_watchpoint = true;
1476     cc->debug_excp_handler = arm_debug_excp_handler;
1477     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1478
1479     cc->disas_set_info = arm_disas_set_info;
1480
1481     /*
1482      * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves
1483      * the object in cpus -> dangling pointer after final
1484      * object_unref().
1485      *
1486      * Once this is fixed, the devices that create ARM CPUs should be
1487      * updated not to set cannot_destroy_with_object_finalize_yet,
1488      * unless they still screw up something else.
1489      */
1490     dc->cannot_destroy_with_object_finalize_yet = true;
1491 }
1492
1493 static void cpu_register(const ARMCPUInfo *info)
1494 {
1495     TypeInfo type_info = {
1496         .parent = TYPE_ARM_CPU,
1497         .instance_size = sizeof(ARMCPU),
1498         .instance_init = info->initfn,
1499         .class_size = sizeof(ARMCPUClass),
1500         .class_init = info->class_init,
1501     };
1502
1503     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1504     type_register(&type_info);
1505     g_free((void *)type_info.name);
1506 }
1507
1508 static const TypeInfo arm_cpu_type_info = {
1509     .name = TYPE_ARM_CPU,
1510     .parent = TYPE_CPU,
1511     .instance_size = sizeof(ARMCPU),
1512     .instance_init = arm_cpu_initfn,
1513     .instance_post_init = arm_cpu_post_init,
1514     .instance_finalize = arm_cpu_finalizefn,
1515     .abstract = true,
1516     .class_size = sizeof(ARMCPUClass),
1517     .class_init = arm_cpu_class_init,
1518 };
1519
1520 static void arm_cpu_register_types(void)
1521 {
1522     const ARMCPUInfo *info = arm_cpus;
1523
1524     type_register_static(&arm_cpu_type_info);
1525
1526     while (info->name) {
1527         cpu_register(info);
1528         info++;
1529     }
1530 }
1531
1532 type_init(arm_cpu_register_types)