2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/isa/isa.h"
31 #include "hw/sysbus.h"
32 #include "qapi/error.h"
33 #include "qemu/range.h"
34 #include "hw/xen/xen.h"
35 #include "hw/pci-host/pam.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/i386/ioapic.h"
38 #include "qapi/visitor.h"
39 #include "qemu/error-report.h"
42 * I440FX chipset data sheet.
43 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
46 #define I440FX_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
49 typedef struct I440FXState
{
50 PCIHostState parent_obj
;
52 uint64_t pci_hole64_size
;
54 uint32_t short_root_bus
;
57 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
58 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
59 #define XEN_PIIX_NUM_PIRQS 128ULL
60 #define PIIX_PIRQC 0x60
62 typedef struct PIIX3State
{
66 * bitmap to track pic levels.
67 * The pic level is the logical OR of all the PCI irqs mapped to it
68 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
70 * PIRQ is mapped to PIC pins, we track it by
71 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
72 * pic_irq * PIIX_NUM_PIRQS + pirq
74 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
75 #error "unable to encode pic state in 64bit in pic_levels."
81 /* This member isn't used. Just for save/load compatibility */
82 int32_t pci_irq_levels_vmstate
[PIIX_NUM_PIRQS
];
84 /* Reset Control Register contents */
87 /* IO memory region for Reset Control Register (RCR_IOPORT) */
91 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
92 #define PIIX3_PCI_DEVICE(obj) \
93 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
95 #define I440FX_PCI_DEVICE(obj) \
96 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
98 struct PCII440FXState
{
100 PCIDevice parent_obj
;
103 MemoryRegion
*system_memory
;
104 MemoryRegion
*pci_address_space
;
105 MemoryRegion
*ram_memory
;
106 PAMMemoryRegion pam_regions
[13];
107 MemoryRegion smram_region
;
108 MemoryRegion smram
, low_smram
;
112 #define I440FX_PAM 0x59
113 #define I440FX_PAM_SIZE 7
114 #define I440FX_SMRAM 0x72
116 /* Keep it 2G to comply with older win32 guests */
117 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
119 /* Older coreboot versions (4.0 and older) read a config register that doesn't
120 * exist in real hardware, to get the RAM size from QEMU.
122 #define I440FX_COREBOOT_RAM_SIZE 0x57
124 static void piix3_set_irq(void *opaque
, int pirq
, int level
);
125 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pci_intx
);
126 static void piix3_write_config_xen(PCIDevice
*dev
,
127 uint32_t address
, uint32_t val
, int len
);
129 /* return the global irq number corresponding to a given device irq
130 pin. We could also use the bus number to have a more precise
132 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int pci_intx
)
135 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
136 return (pci_intx
+ slot_addend
) & 3;
139 static void i440fx_update_memory_mappings(PCII440FXState
*d
)
142 PCIDevice
*pd
= PCI_DEVICE(d
);
144 memory_region_transaction_begin();
145 for (i
= 0; i
< 13; i
++) {
146 pam_update(&d
->pam_regions
[i
], i
,
147 pd
->config
[I440FX_PAM
+ DIV_ROUND_UP(i
, 2)]);
149 memory_region_set_enabled(&d
->smram_region
,
150 !(pd
->config
[I440FX_SMRAM
] & SMRAM_D_OPEN
));
151 memory_region_set_enabled(&d
->smram
,
152 pd
->config
[I440FX_SMRAM
] & SMRAM_G_SMRAME
);
153 memory_region_transaction_commit();
157 static void i440fx_write_config(PCIDevice
*dev
,
158 uint32_t address
, uint32_t val
, int len
)
160 PCII440FXState
*d
= I440FX_PCI_DEVICE(dev
);
162 /* XXX: implement SMRAM.D_LOCK */
163 pci_default_write_config(dev
, address
, val
, len
);
164 if (ranges_overlap(address
, len
, I440FX_PAM
, I440FX_PAM_SIZE
) ||
165 range_covers_byte(address
, len
, I440FX_SMRAM
)) {
166 i440fx_update_memory_mappings(d
);
170 static int i440fx_load_old(QEMUFile
* f
, void *opaque
, int version_id
)
172 PCII440FXState
*d
= opaque
;
173 PCIDevice
*pd
= PCI_DEVICE(d
);
177 ret
= pci_device_load(pd
, f
);
180 i440fx_update_memory_mappings(d
);
181 qemu_get_8s(f
, &smm_enabled
);
183 if (version_id
== 2) {
184 for (i
= 0; i
< PIIX_NUM_PIRQS
; i
++) {
185 qemu_get_be32(f
); /* dummy load for compatibility */
192 static int i440fx_post_load(void *opaque
, int version_id
)
194 PCII440FXState
*d
= opaque
;
196 i440fx_update_memory_mappings(d
);
200 static const VMStateDescription vmstate_i440fx
= {
203 .minimum_version_id
= 3,
204 .minimum_version_id_old
= 1,
205 .load_state_old
= i440fx_load_old
,
206 .post_load
= i440fx_post_load
,
207 .fields
= (VMStateField
[]) {
208 VMSTATE_PCI_DEVICE(parent_obj
, PCII440FXState
),
209 /* Used to be smm_enabled, which was basically always zero because
210 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
213 VMSTATE_END_OF_LIST()
217 static void i440fx_pcihost_get_pci_hole_start(Object
*obj
, Visitor
*v
,
218 const char *name
, void *opaque
,
221 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
225 val64
= range_is_empty(&s
->pci_hole
) ? 0 : range_lob(&s
->pci_hole
);
227 assert(value
== val64
);
228 visit_type_uint32(v
, name
, &value
, errp
);
231 static void i440fx_pcihost_get_pci_hole_end(Object
*obj
, Visitor
*v
,
232 const char *name
, void *opaque
,
235 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
239 val64
= range_is_empty(&s
->pci_hole
) ? 0 : range_upb(&s
->pci_hole
) + 1;
241 assert(value
== val64
);
242 visit_type_uint32(v
, name
, &value
, errp
);
246 * The 64bit PCI hole start is set by the Guest firmware
247 * as the address of the first 64bit PCI MEM resource.
248 * If no PCI device has resources on the 64bit area,
249 * the 64bit PCI hole will start after "over 4G RAM" and the
250 * reserved space for memory hotplug if any.
252 static void i440fx_pcihost_get_pci_hole64_start(Object
*obj
, Visitor
*v
,
254 void *opaque
, Error
**errp
)
256 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
257 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
261 pci_bus_get_w64_range(h
->bus
, &w64
);
262 value
= range_is_empty(&w64
) ? 0 : range_lob(&w64
);
263 if (!value
&& s
->pci_hole64_fix
) {
264 value
= pc_pci_hole64_start();
266 visit_type_uint64(v
, name
, &value
, errp
);
270 * The 64bit PCI hole end is set by the Guest firmware
271 * as the address of the last 64bit PCI MEM resource.
272 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
273 * that can be configured by the user.
275 static void i440fx_pcihost_get_pci_hole64_end(Object
*obj
, Visitor
*v
,
276 const char *name
, void *opaque
,
279 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
280 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
281 uint64_t hole64_start
= pc_pci_hole64_start();
283 uint64_t value
, hole64_end
;
285 pci_bus_get_w64_range(h
->bus
, &w64
);
286 value
= range_is_empty(&w64
) ? 0 : range_upb(&w64
) + 1;
287 hole64_end
= ROUND_UP(hole64_start
+ s
->pci_hole64_size
, 1ULL << 30);
288 if (s
->pci_hole64_fix
&& value
< hole64_end
) {
291 visit_type_uint64(v
, name
, &value
, errp
);
294 static void i440fx_pcihost_initfn(Object
*obj
)
296 PCIHostState
*s
= PCI_HOST_BRIDGE(obj
);
298 memory_region_init_io(&s
->conf_mem
, obj
, &pci_host_conf_le_ops
, s
,
300 memory_region_init_io(&s
->data_mem
, obj
, &pci_host_data_le_ops
, s
,
303 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_START
, "uint32",
304 i440fx_pcihost_get_pci_hole_start
,
305 NULL
, NULL
, NULL
, NULL
);
307 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_END
, "uint32",
308 i440fx_pcihost_get_pci_hole_end
,
309 NULL
, NULL
, NULL
, NULL
);
311 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_START
, "uint64",
312 i440fx_pcihost_get_pci_hole64_start
,
313 NULL
, NULL
, NULL
, NULL
);
315 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_END
, "uint64",
316 i440fx_pcihost_get_pci_hole64_end
,
317 NULL
, NULL
, NULL
, NULL
);
320 static void i440fx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
322 PCIHostState
*s
= PCI_HOST_BRIDGE(dev
);
323 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
325 sysbus_add_io(sbd
, 0xcf8, &s
->conf_mem
);
326 sysbus_init_ioports(sbd
, 0xcf8, 4);
328 sysbus_add_io(sbd
, 0xcfc, &s
->data_mem
);
329 sysbus_init_ioports(sbd
, 0xcfc, 4);
331 /* register i440fx 0xcf8 port as coalesced pio */
332 memory_region_set_flush_coalesced(&s
->data_mem
);
333 memory_region_add_coalescing(&s
->conf_mem
, 0, 4);
336 static void i440fx_realize(PCIDevice
*dev
, Error
**errp
)
338 dev
->config
[I440FX_SMRAM
] = 0x02;
340 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL
)) {
341 warn_report("i440fx doesn't support emulated iommu");
345 PCIBus
*i440fx_init(const char *host_type
, const char *pci_type
,
346 PCII440FXState
**pi440fx_state
,
348 ISABus
**isa_bus
, qemu_irq
*pic
,
349 MemoryRegion
*address_space_mem
,
350 MemoryRegion
*address_space_io
,
352 ram_addr_t below_4g_mem_size
,
353 ram_addr_t above_4g_mem_size
,
354 MemoryRegion
*pci_address_space
,
355 MemoryRegion
*ram_memory
)
366 dev
= qdev_create(NULL
, host_type
);
367 s
= PCI_HOST_BRIDGE(dev
);
368 b
= pci_root_bus_new(dev
, NULL
, pci_address_space
,
369 address_space_io
, 0, TYPE_PCI_BUS
);
371 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev
), NULL
);
372 qdev_init_nofail(dev
);
374 d
= pci_create_simple(b
, 0, pci_type
);
375 *pi440fx_state
= I440FX_PCI_DEVICE(d
);
377 f
->system_memory
= address_space_mem
;
378 f
->pci_address_space
= pci_address_space
;
379 f
->ram_memory
= ram_memory
;
381 i440fx
= I440FX_PCI_HOST_BRIDGE(dev
);
382 range_set_bounds(&i440fx
->pci_hole
, below_4g_mem_size
,
383 IO_APIC_DEFAULT_ADDRESS
- 1);
385 /* setup pci memory mapping */
386 pc_pci_as_mapping_init(OBJECT(f
), f
->system_memory
,
387 f
->pci_address_space
);
389 /* if *disabled* show SMRAM to all CPUs */
390 memory_region_init_alias(&f
->smram_region
, OBJECT(d
), "smram-region",
391 f
->pci_address_space
, 0xa0000, 0x20000);
392 memory_region_add_subregion_overlap(f
->system_memory
, 0xa0000,
393 &f
->smram_region
, 1);
394 memory_region_set_enabled(&f
->smram_region
, true);
396 /* smram, as seen by SMM CPUs */
397 memory_region_init(&f
->smram
, OBJECT(d
), "smram", 1ull << 32);
398 memory_region_set_enabled(&f
->smram
, true);
399 memory_region_init_alias(&f
->low_smram
, OBJECT(d
), "smram-low",
400 f
->ram_memory
, 0xa0000, 0x20000);
401 memory_region_set_enabled(&f
->low_smram
, true);
402 memory_region_add_subregion(&f
->smram
, 0xa0000, &f
->low_smram
);
403 object_property_add_const_link(qdev_get_machine(), "smram",
404 OBJECT(&f
->smram
), &error_abort
);
406 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
407 &f
->pam_regions
[0], PAM_BIOS_BASE
, PAM_BIOS_SIZE
);
408 for (i
= 0; i
< 12; ++i
) {
409 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
410 &f
->pam_regions
[i
+1], PAM_EXPAN_BASE
+ i
* PAM_EXPAN_SIZE
,
414 /* Xen supports additional interrupt routes from the PCI devices to
415 * the IOAPIC: the four pins of each PCI device on the bus are also
416 * connected to the IOAPIC directly.
417 * These additional routes can be discovered through ACPI. */
419 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
420 -1, true, "PIIX3-xen");
421 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
422 pci_bus_irqs(b
, xen_piix3_set_irq
, xen_pci_slot_get_pirq
,
423 piix3
, XEN_PIIX_NUM_PIRQS
);
425 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
427 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
428 pci_bus_irqs(b
, piix3_set_irq
, pci_slot_get_pirq
, piix3
,
430 pci_bus_set_route_irq_fn(b
, piix3_route_intx_pin_to_irq
);
433 *isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(piix3
), "isa.0"));
435 *piix3_devfn
= piix3
->dev
.devfn
;
437 ram_size
= ram_size
/ 8 / 1024 / 1024;
438 if (ram_size
> 255) {
441 d
->config
[I440FX_COREBOOT_RAM_SIZE
] = ram_size
;
443 i440fx_update_memory_mappings(f
);
448 PCIBus
*find_i440fx(void)
450 PCIHostState
*s
= OBJECT_CHECK(PCIHostState
,
451 object_resolve_path("/machine/i440fx", NULL
),
452 TYPE_PCI_HOST_BRIDGE
);
453 return s
? s
->bus
: NULL
;
456 /* PIIX3 PCI to ISA bridge */
457 static void piix3_set_irq_pic(PIIX3State
*piix3
, int pic_irq
)
459 qemu_set_irq(piix3
->pic
[pic_irq
],
460 !!(piix3
->pic_levels
&
461 (((1ULL << PIIX_NUM_PIRQS
) - 1) <<
462 (pic_irq
* PIIX_NUM_PIRQS
))));
465 static void piix3_set_irq_level_internal(PIIX3State
*piix3
, int pirq
, int level
)
470 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
471 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
475 mask
= 1ULL << ((pic_irq
* PIIX_NUM_PIRQS
) + pirq
);
476 piix3
->pic_levels
&= ~mask
;
477 piix3
->pic_levels
|= mask
* !!level
;
480 static void piix3_set_irq_level(PIIX3State
*piix3
, int pirq
, int level
)
484 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
485 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
489 piix3_set_irq_level_internal(piix3
, pirq
, level
);
491 piix3_set_irq_pic(piix3
, pic_irq
);
494 static void piix3_set_irq(void *opaque
, int pirq
, int level
)
496 PIIX3State
*piix3
= opaque
;
497 piix3_set_irq_level(piix3
, pirq
, level
);
500 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pin
)
502 PIIX3State
*piix3
= opaque
;
503 int irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pin
];
506 if (irq
< PIIX_NUM_PIC_IRQS
) {
507 route
.mode
= PCI_INTX_ENABLED
;
510 route
.mode
= PCI_INTX_DISABLED
;
516 /* irq routing is changed. so rebuild bitmap */
517 static void piix3_update_irq_levels(PIIX3State
*piix3
)
519 PCIBus
*bus
= pci_get_bus(&piix3
->dev
);
522 piix3
->pic_levels
= 0;
523 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
524 piix3_set_irq_level(piix3
, pirq
, pci_bus_get_irq_level(bus
, pirq
));
528 static void piix3_write_config(PCIDevice
*dev
,
529 uint32_t address
, uint32_t val
, int len
)
531 pci_default_write_config(dev
, address
, val
, len
);
532 if (ranges_overlap(address
, len
, PIIX_PIRQC
, 4)) {
533 PIIX3State
*piix3
= PIIX3_PCI_DEVICE(dev
);
536 pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3
->dev
));
537 piix3_update_irq_levels(piix3
);
538 for (pic_irq
= 0; pic_irq
< PIIX_NUM_PIC_IRQS
; pic_irq
++) {
539 piix3_set_irq_pic(piix3
, pic_irq
);
544 static void piix3_write_config_xen(PCIDevice
*dev
,
545 uint32_t address
, uint32_t val
, int len
)
547 xen_piix_pci_write_config_client(address
, val
, len
);
548 piix3_write_config(dev
, address
, val
, len
);
551 static void piix3_reset(void *opaque
)
553 PIIX3State
*d
= opaque
;
554 uint8_t *pci_conf
= d
->dev
.config
;
556 pci_conf
[0x04] = 0x07; /* master, memory and I/O */
557 pci_conf
[0x05] = 0x00;
558 pci_conf
[0x06] = 0x00;
559 pci_conf
[0x07] = 0x02; /* PCI_status_devsel_medium */
560 pci_conf
[0x4c] = 0x4d;
561 pci_conf
[0x4e] = 0x03;
562 pci_conf
[0x4f] = 0x00;
563 pci_conf
[0x60] = 0x80;
564 pci_conf
[0x61] = 0x80;
565 pci_conf
[0x62] = 0x80;
566 pci_conf
[0x63] = 0x80;
567 pci_conf
[0x69] = 0x02;
568 pci_conf
[0x70] = 0x80;
569 pci_conf
[0x76] = 0x0c;
570 pci_conf
[0x77] = 0x0c;
571 pci_conf
[0x78] = 0x02;
572 pci_conf
[0x79] = 0x00;
573 pci_conf
[0x80] = 0x00;
574 pci_conf
[0x82] = 0x00;
575 pci_conf
[0xa0] = 0x08;
576 pci_conf
[0xa2] = 0x00;
577 pci_conf
[0xa3] = 0x00;
578 pci_conf
[0xa4] = 0x00;
579 pci_conf
[0xa5] = 0x00;
580 pci_conf
[0xa6] = 0x00;
581 pci_conf
[0xa7] = 0x00;
582 pci_conf
[0xa8] = 0x0f;
583 pci_conf
[0xaa] = 0x00;
584 pci_conf
[0xab] = 0x00;
585 pci_conf
[0xac] = 0x00;
586 pci_conf
[0xae] = 0x00;
592 static int piix3_post_load(void *opaque
, int version_id
)
594 PIIX3State
*piix3
= opaque
;
597 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
598 * might bring the system to a different state than the saved one;
599 * for example, the interrupt could be masked but the i8259 would
600 * not know that yet and would trigger an interrupt in the CPU.
602 * Here, we update irq levels without raising the interrupt.
603 * Interrupt state will be deserialized separately through the i8259.
605 piix3
->pic_levels
= 0;
606 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
607 piix3_set_irq_level_internal(piix3
, pirq
,
608 pci_bus_get_irq_level(pci_get_bus(&piix3
->dev
), pirq
));
613 static int piix3_pre_save(void *opaque
)
616 PIIX3State
*piix3
= opaque
;
618 for (i
= 0; i
< ARRAY_SIZE(piix3
->pci_irq_levels_vmstate
); i
++) {
619 piix3
->pci_irq_levels_vmstate
[i
] =
620 pci_bus_get_irq_level(pci_get_bus(&piix3
->dev
), i
);
626 static bool piix3_rcr_needed(void *opaque
)
628 PIIX3State
*piix3
= opaque
;
630 return (piix3
->rcr
!= 0);
633 static const VMStateDescription vmstate_piix3_rcr
= {
636 .minimum_version_id
= 1,
637 .needed
= piix3_rcr_needed
,
638 .fields
= (VMStateField
[]) {
639 VMSTATE_UINT8(rcr
, PIIX3State
),
640 VMSTATE_END_OF_LIST()
644 static const VMStateDescription vmstate_piix3
= {
647 .minimum_version_id
= 2,
648 .post_load
= piix3_post_load
,
649 .pre_save
= piix3_pre_save
,
650 .fields
= (VMStateField
[]) {
651 VMSTATE_PCI_DEVICE(dev
, PIIX3State
),
652 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate
, PIIX3State
,
654 VMSTATE_END_OF_LIST()
656 .subsections
= (const VMStateDescription
*[]) {
663 static void rcr_write(void *opaque
, hwaddr addr
, uint64_t val
, unsigned len
)
665 PIIX3State
*d
= opaque
;
668 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
671 d
->rcr
= val
& 2; /* keep System Reset type only */
674 static uint64_t rcr_read(void *opaque
, hwaddr addr
, unsigned len
)
676 PIIX3State
*d
= opaque
;
681 static const MemoryRegionOps rcr_ops
= {
684 .endianness
= DEVICE_LITTLE_ENDIAN
687 static void piix3_realize(PCIDevice
*dev
, Error
**errp
)
689 PIIX3State
*d
= PIIX3_PCI_DEVICE(dev
);
691 if (!isa_bus_new(DEVICE(d
), get_system_memory(),
692 pci_address_space_io(dev
), errp
)) {
696 memory_region_init_io(&d
->rcr_mem
, OBJECT(dev
), &rcr_ops
, d
,
697 "piix3-reset-control", 1);
698 memory_region_add_subregion_overlap(pci_address_space_io(dev
), RCR_IOPORT
,
701 qemu_register_reset(piix3_reset
, d
);
704 static void pci_piix3_class_init(ObjectClass
*klass
, void *data
)
706 DeviceClass
*dc
= DEVICE_CLASS(klass
);
707 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
709 dc
->desc
= "ISA bridge";
710 dc
->vmsd
= &vmstate_piix3
;
711 dc
->hotpluggable
= false;
712 k
->realize
= piix3_realize
;
713 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
714 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
715 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
716 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
718 * Reason: part of PIIX3 southbridge, needs to be wired up by
719 * pc_piix.c's pc_init1()
721 dc
->user_creatable
= false;
724 static const TypeInfo piix3_pci_type_info
= {
725 .name
= TYPE_PIIX3_PCI_DEVICE
,
726 .parent
= TYPE_PCI_DEVICE
,
727 .instance_size
= sizeof(PIIX3State
),
729 .class_init
= pci_piix3_class_init
,
730 .interfaces
= (InterfaceInfo
[]) {
731 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
736 static void piix3_class_init(ObjectClass
*klass
, void *data
)
738 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
740 k
->config_write
= piix3_write_config
;
743 static const TypeInfo piix3_info
= {
745 .parent
= TYPE_PIIX3_PCI_DEVICE
,
746 .class_init
= piix3_class_init
,
749 static void piix3_xen_class_init(ObjectClass
*klass
, void *data
)
751 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
753 k
->config_write
= piix3_write_config_xen
;
756 static const TypeInfo piix3_xen_info
= {
758 .parent
= TYPE_PIIX3_PCI_DEVICE
,
759 .class_init
= piix3_xen_class_init
,
762 static void i440fx_class_init(ObjectClass
*klass
, void *data
)
764 DeviceClass
*dc
= DEVICE_CLASS(klass
);
765 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
767 k
->realize
= i440fx_realize
;
768 k
->config_write
= i440fx_write_config
;
769 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
770 k
->device_id
= PCI_DEVICE_ID_INTEL_82441
;
772 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
773 dc
->desc
= "Host bridge";
774 dc
->vmsd
= &vmstate_i440fx
;
776 * PCI-facing part of the host bridge, not usable without the
777 * host-facing part, which can't be device_add'ed, yet.
779 dc
->user_creatable
= false;
780 dc
->hotpluggable
= false;
783 static const TypeInfo i440fx_info
= {
784 .name
= TYPE_I440FX_PCI_DEVICE
,
785 .parent
= TYPE_PCI_DEVICE
,
786 .instance_size
= sizeof(PCII440FXState
),
787 .class_init
= i440fx_class_init
,
788 .interfaces
= (InterfaceInfo
[]) {
789 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
794 /* IGD Passthrough Host Bridge. */
800 /* Here we just expose minimal host bridge offset subset. */
801 static const IGDHostInfo igd_host_bridge_infos
[] = {
802 {0x08, 2}, /* revision id */
803 {0x2c, 2}, /* sybsystem vendor id */
804 {0x2e, 2}, /* sybsystem id */
805 {0x50, 2}, /* SNB: processor graphics control register */
806 {0x52, 2}, /* processor graphics control register */
807 {0xa4, 4}, /* SNB: graphics base of stolen memory */
808 {0xa8, 4}, /* SNB: base of GTT stolen memory */
811 static void host_pci_config_read(int pos
, int len
, uint32_t *val
, Error
**errp
)
814 /* Access real host bridge. */
815 char *path
= g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
816 0, 0, 0, 0, "config");
818 config_fd
= open(path
, O_RDWR
);
820 error_setg_errno(errp
, errno
, "Failed to open: %s", path
);
824 if (lseek(config_fd
, pos
, SEEK_SET
) != pos
) {
825 error_setg_errno(errp
, errno
, "Failed to seek: %s", path
);
830 rc
= read(config_fd
, (uint8_t *)val
, len
);
831 } while (rc
< 0 && (errno
== EINTR
|| errno
== EAGAIN
));
833 error_setg_errno(errp
, errno
, "Failed to read: %s", path
);
842 static void igd_pt_i440fx_realize(PCIDevice
*pci_dev
, Error
**errp
)
847 Error
*local_err
= NULL
;
849 num
= ARRAY_SIZE(igd_host_bridge_infos
);
850 for (i
= 0; i
< num
; i
++) {
851 pos
= igd_host_bridge_infos
[i
].offset
;
852 len
= igd_host_bridge_infos
[i
].len
;
853 host_pci_config_read(pos
, len
, &val
, &local_err
);
855 error_propagate(errp
, local_err
);
858 pci_default_write_config(pci_dev
, pos
, val
, len
);
862 static void igd_passthrough_i440fx_class_init(ObjectClass
*klass
, void *data
)
864 DeviceClass
*dc
= DEVICE_CLASS(klass
);
865 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
867 k
->realize
= igd_pt_i440fx_realize
;
868 dc
->desc
= "IGD Passthrough Host bridge";
871 static const TypeInfo igd_passthrough_i440fx_info
= {
872 .name
= TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
,
873 .parent
= TYPE_I440FX_PCI_DEVICE
,
874 .instance_size
= sizeof(PCII440FXState
),
875 .class_init
= igd_passthrough_i440fx_class_init
,
878 static const char *i440fx_pcihost_root_bus_path(PCIHostState
*host_bridge
,
881 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(host_bridge
);
883 /* For backwards compat with old device paths */
884 if (s
->short_root_bus
) {
890 static Property i440fx_props
[] = {
891 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE
, I440FXState
,
892 pci_hole64_size
, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT
),
893 DEFINE_PROP_UINT32("short_root_bus", I440FXState
, short_root_bus
, 0),
894 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState
, pci_hole64_fix
, true),
895 DEFINE_PROP_END_OF_LIST(),
898 static void i440fx_pcihost_class_init(ObjectClass
*klass
, void *data
)
900 DeviceClass
*dc
= DEVICE_CLASS(klass
);
901 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
903 hc
->root_bus_path
= i440fx_pcihost_root_bus_path
;
904 dc
->realize
= i440fx_pcihost_realize
;
906 dc
->props
= i440fx_props
;
907 /* Reason: needs to be wired up by pc_init1 */
908 dc
->user_creatable
= false;
911 static const TypeInfo i440fx_pcihost_info
= {
912 .name
= TYPE_I440FX_PCI_HOST_BRIDGE
,
913 .parent
= TYPE_PCI_HOST_BRIDGE
,
914 .instance_size
= sizeof(I440FXState
),
915 .instance_init
= i440fx_pcihost_initfn
,
916 .class_init
= i440fx_pcihost_class_init
,
919 static void i440fx_register_types(void)
921 type_register_static(&i440fx_info
);
922 type_register_static(&igd_passthrough_i440fx_info
);
923 type_register_static(&piix3_pci_type_info
);
924 type_register_static(&piix3_info
);
925 type_register_static(&piix3_xen_info
);
926 type_register_static(&i440fx_pcihost_info
);
929 type_init(i440fx_register_types
)