hw/intc/arm_gic_kvm.c

   1 /*
   2  * ARM Generic Interrupt Controller using KVM in-kernel support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  * Save/Restore logic added by Christoffer Dall.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw/sysbus.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_arm.h"
  25 #include "gic_internal.h"
  26
  27 //#define DEBUG_GIC_KVM
  28
  29 #ifdef DEBUG_GIC_KVM
  30 static const int debug_gic_kvm = 1;
  31 #else
  32 static const int debug_gic_kvm = 0;
  33 #endif
  34
  35 #define DPRINTF(fmt, ...) do { \
  36         if (debug_gic_kvm) { \
  37             printf("arm_gic: " fmt , ## __VA_ARGS__); \
  38         } \
  39     } while (0)
  40
  41 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
  42 #define KVM_ARM_GIC(obj) \
  43      OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
  44 #define KVM_ARM_GIC_CLASS(klass) \
  45      OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
  46 #define KVM_ARM_GIC_GET_CLASS(obj) \
  47      OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
  48
  49 typedef struct KVMARMGICClass {
  50     ARMGICCommonClass parent_class;
  51     DeviceRealize parent_realize;
  52     void (*parent_reset)(DeviceState *dev);
  53 } KVMARMGICClass;
  54
  55 static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
  56 {
  57     /* Meaning of the 'irq' parameter:
  58      *  [0..N-1] : external interrupts
  59      *  [N..N+31] : PPI (internal) interrupts for CPU 0
  60      *  [N+32..N+63] : PPI (internal interrupts for CPU 1
  61      *  ...
  62      * Convert this to the kernel's desired encoding, which
  63      * has separate fields in the irq number for type,
  64      * CPU number and interrupt number.
  65      */
  66     GICState *s = (GICState *)opaque;
  67     int kvm_irq, irqtype, cpu;
  68
  69     if (irq < (s->num_irq - GIC_INTERNAL)) {
  70         /* External interrupt. The kernel numbers these like the GIC
  71          * hardware, with external interrupt IDs starting after the
  72          * internal ones.
  73          */
  74         irqtype = KVM_ARM_IRQ_TYPE_SPI;
  75         cpu = 0;
  76         irq += GIC_INTERNAL;
  77     } else {
  78         /* Internal interrupt: decode into (cpu, interrupt id) */
  79         irqtype = KVM_ARM_IRQ_TYPE_PPI;
  80         irq -= (s->num_irq - GIC_INTERNAL);
  81         cpu = irq / GIC_INTERNAL;
  82         irq %= GIC_INTERNAL;
  83     }
  84     kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
  85         | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
  86
  87     kvm_set_irq(kvm_state, kvm_irq, !!level);
  88 }
  89
  90 static bool kvm_arm_gic_can_save_restore(GICState *s)
  91 {
  92     return s->dev_fd >= 0;
  93 }
  94
  95 static bool kvm_gic_supports_attr(GICState *s, int group, int attrnum)
  96 {
  97     struct kvm_device_attr attr = {
  98         .group = group,
  99         .attr = attrnum,
 100         .flags = 0,
 101     };
 102
 103     if (s->dev_fd == -1) {
 104         return false;
 105     }
 106
 107     return kvm_device_ioctl(s->dev_fd, KVM_HAS_DEVICE_ATTR, &attr) == 0;
 108 }
 109
 110 static void kvm_gic_access(GICState *s, int group, int offset,
 111                                    int cpu, uint32_t *val, bool write)
 112 {
 113     struct kvm_device_attr attr;
 114     int type;
 115     int err;
 116
 117     cpu = cpu & 0xff;
 118
 119     attr.flags = 0;
 120     attr.group = group;
 121     attr.attr = (((uint64_t)cpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &
 122                  KVM_DEV_ARM_VGIC_CPUID_MASK) |
 123                 (((uint64_t)offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) &
 124                  KVM_DEV_ARM_VGIC_OFFSET_MASK);
 125     attr.addr = (uintptr_t)val;
 126
 127     if (write) {
 128         type = KVM_SET_DEVICE_ATTR;
 129     } else {
 130         type = KVM_GET_DEVICE_ATTR;
 131     }
 132
 133     err = kvm_device_ioctl(s->dev_fd, type, &attr);
 134     if (err < 0) {
 135         fprintf(stderr, "KVM_{SET/GET}_DEVICE_ATTR failed: %s\n",
 136                 strerror(-err));
 137         abort();
 138     }
 139 }
 140
 141 static void kvm_gicd_access(GICState *s, int offset, int cpu,
 142                             uint32_t *val, bool write)
 143 {
 144     kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
 145                    offset, cpu, val, write);
 146 }
 147
 148 static void kvm_gicc_access(GICState *s, int offset, int cpu,
 149                             uint32_t *val, bool write)
 150 {
 151     kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
 152                    offset, cpu, val, write);
 153 }
 154
 155 #define for_each_irq_reg(_ctr, _max_irq, _field_width) \
 156     for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
 157
 158 /*
 159  * Translate from the in-kernel field for an IRQ value to/from the qemu
 160  * representation.
 161  */
 162 typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
 163                                   uint32_t *field, bool to_kernel);
 164
 165 /* synthetic translate function used for clear/set registers to completely
 166  * clear a setting using a clear-register before setting the remaining bits
 167  * using a set-register */
 168 static void translate_clear(GICState *s, int irq, int cpu,
 169                             uint32_t *field, bool to_kernel)
 170 {
 171     if (to_kernel) {
 172         *field = ~0;
 173     } else {
 174         /* does not make sense: qemu model doesn't use set/clear regs */
 175         abort();
 176     }
 177 }
 178
 179 static void translate_group(GICState *s, int irq, int cpu,
 180                             uint32_t *field, bool to_kernel)
 181 {
 182     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 183
 184     if (to_kernel) {
 185         *field = GIC_TEST_GROUP(irq, cm);
 186     } else {
 187         if (*field & 1) {
 188             GIC_SET_GROUP(irq, cm);
 189         }
 190     }
 191 }
 192
 193 static void translate_enabled(GICState *s, int irq, int cpu,
 194                               uint32_t *field, bool to_kernel)
 195 {
 196     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 197
 198     if (to_kernel) {
 199         *field = GIC_TEST_ENABLED(irq, cm);
 200     } else {
 201         if (*field & 1) {
 202             GIC_SET_ENABLED(irq, cm);
 203         }
 204     }
 205 }
 206
 207 static void translate_pending(GICState *s, int irq, int cpu,
 208                               uint32_t *field, bool to_kernel)
 209 {
 210     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 211
 212     if (to_kernel) {
 213         *field = gic_test_pending(s, irq, cm);
 214     } else {
 215         if (*field & 1) {
 216             GIC_SET_PENDING(irq, cm);
 217             /* TODO: Capture is level-line is held high in the kernel */
 218         }
 219     }
 220 }
 221
 222 static void translate_active(GICState *s, int irq, int cpu,
 223                              uint32_t *field, bool to_kernel)
 224 {
 225     int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
 226
 227     if (to_kernel) {
 228         *field = GIC_TEST_ACTIVE(irq, cm);
 229     } else {
 230         if (*field & 1) {
 231             GIC_SET_ACTIVE(irq, cm);
 232         }
 233     }
 234 }
 235
 236 static void translate_trigger(GICState *s, int irq, int cpu,
 237                               uint32_t *field, bool to_kernel)
 238 {
 239     if (to_kernel) {
 240         *field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
 241     } else {
 242         if (*field & 0x2) {
 243             GIC_SET_EDGE_TRIGGER(irq);
 244         }
 245     }
 246 }
 247
 248 static void translate_priority(GICState *s, int irq, int cpu,
 249                                uint32_t *field, bool to_kernel)
 250 {
 251     if (to_kernel) {
 252         *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
 253     } else {
 254         gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIED);
 255     }
 256 }
 257
 258 static void translate_targets(GICState *s, int irq, int cpu,
 259                               uint32_t *field, bool to_kernel)
 260 {
 261     if (to_kernel) {
 262         *field = s->irq_target[irq] & 0xff;
 263     } else {
 264         s->irq_target[irq] = *field & 0xff;
 265     }
 266 }
 267
 268 static void translate_sgisource(GICState *s, int irq, int cpu,
 269                                 uint32_t *field, bool to_kernel)
 270 {
 271     if (to_kernel) {
 272         *field = s->sgi_pending[irq][cpu] & 0xff;
 273     } else {
 274         s->sgi_pending[irq][cpu] = *field & 0xff;
 275     }
 276 }
 277
 278 /* Read a register group from the kernel VGIC */
 279 static void kvm_dist_get(GICState *s, uint32_t offset, int width,
 280                          int maxirq, vgic_translate_fn translate_fn)
 281 {
 282     uint32_t reg;
 283     int i;
 284     int j;
 285     int irq;
 286     int cpu;
 287     int regsz = 32 / width; /* irqs per kernel register */
 288     uint32_t field;
 289
 290     for_each_irq_reg(i, maxirq, width) {
 291         irq = i * regsz;
 292         cpu = 0;
 293         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 294             kvm_gicd_access(s, offset, cpu, &reg, false);
 295             for (j = 0; j < regsz; j++) {
 296                 field = extract32(reg, j * width, width);
 297                 translate_fn(s, irq + j, cpu, &field, false);
 298             }
 299
 300             cpu++;
 301         }
 302         offset += 4;
 303     }
 304 }
 305
 306 /* Write a register group to the kernel VGIC */
 307 static void kvm_dist_put(GICState *s, uint32_t offset, int width,
 308                          int maxirq, vgic_translate_fn translate_fn)
 309 {
 310     uint32_t reg;
 311     int i;
 312     int j;
 313     int irq;
 314     int cpu;
 315     int regsz = 32 / width; /* irqs per kernel register */
 316     uint32_t field;
 317
 318     for_each_irq_reg(i, maxirq, width) {
 319         irq = i * regsz;
 320         cpu = 0;
 321         while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
 322             reg = 0;
 323             for (j = 0; j < regsz; j++) {
 324                 translate_fn(s, irq + j, cpu, &field, true);
 325                 reg = deposit32(reg, j * width, width, field);
 326             }
 327             kvm_gicd_access(s, offset, cpu, &reg, true);
 328
 329             cpu++;
 330         }
 331         offset += 4;
 332     }
 333 }
 334
 335 static void kvm_arm_gic_put(GICState *s)
 336 {
 337     uint32_t reg;
 338     int i;
 339     int cpu;
 340     int num_cpu;
 341     int num_irq;
 342
 343     if (!kvm_arm_gic_can_save_restore(s)) {
 344             DPRINTF("Cannot put kernel gic state, no kernel interface");
 345             return;
 346     }
 347
 348     /* Note: We do the restore in a slightly different order than the save
 349      * (where the order doesn't matter and is simply ordered according to the
 350      * register offset values */
 351
 352     /*****************************************************************
 353      * Distributor State
 354      */
 355
 356     /* s->ctlr -> GICD_CTLR */
 357     reg = s->ctlr;
 358     kvm_gicd_access(s, 0x0, 0, &reg, true);
 359
 360     /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
 361     kvm_gicd_access(s, 0x4, 0, &reg, false);
 362     num_irq = ((reg & 0x1f) + 1) * 32;
 363     num_cpu = ((reg & 0xe0) >> 5) + 1;
 364
 365     if (num_irq < s->num_irq) {
 366             fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
 367                     s->num_irq, num_irq);
 368             abort();
 369     } else if (num_cpu != s->num_cpu) {
 370             fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
 371                     s->num_cpu, num_cpu);
 372             /* Did we not create the VCPUs in the kernel yet? */
 373             abort();
 374     }
 375
 376     /* TODO: Consider checking compatibility with the IIDR ? */
 377
 378     /* irq_state[n].enabled -> GICD_ISENABLERn */
 379     kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
 380     kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
 381
 382     /* irq_state[n].group -> GICD_IGROUPRn */
 383     kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
 384
 385     /* s->irq_target[irq] -> GICD_ITARGETSRn
 386      * (restore targets before pending to ensure the pending state is set on
 387      * the appropriate CPU interfaces in the kernel) */
 388     kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
 389
 390     /* irq_state[n].trigger -> GICD_ICFGRn
 391      * (restore configuration registers before pending IRQs so we treat
 392      * level/edge correctly) */
 393     kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
 394
 395     /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
 396     kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
 397     kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
 398
 399     /* irq_state[n].active -> GICD_ISACTIVERn */
 400     kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
 401     kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
 402
 403
 404     /* s->priorityX[irq] -> ICD_IPRIORITYRn */
 405     kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
 406
 407     /* s->sgi_pending -> ICD_CPENDSGIRn */
 408     kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
 409     kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
 410
 411
 412     /*****************************************************************
 413      * CPU Interface(s) State
 414      */
 415
 416     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 417         /* s->cpu_ctlr[cpu] -> GICC_CTLR */
 418         reg = s->cpu_ctlr[cpu];
 419         kvm_gicc_access(s, 0x00, cpu, &reg, true);
 420
 421         /* s->priority_mask[cpu] -> GICC_PMR */
 422         reg = (s->priority_mask[cpu] & 0xff);
 423         kvm_gicc_access(s, 0x04, cpu, &reg, true);
 424
 425         /* s->bpr[cpu] -> GICC_BPR */
 426         reg = (s->bpr[cpu] & 0x7);
 427         kvm_gicc_access(s, 0x08, cpu, &reg, true);
 428
 429         /* s->abpr[cpu] -> GICC_ABPR */
 430         reg = (s->abpr[cpu] & 0x7);
 431         kvm_gicc_access(s, 0x1c, cpu, &reg, true);
 432
 433         /* s->apr[n][cpu] -> GICC_APRn */
 434         for (i = 0; i < 4; i++) {
 435             reg = s->apr[i][cpu];
 436             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, true);
 437         }
 438     }
 439 }
 440
 441 static void kvm_arm_gic_get(GICState *s)
 442 {
 443     uint32_t reg;
 444     int i;
 445     int cpu;
 446
 447     if (!kvm_arm_gic_can_save_restore(s)) {
 448             DPRINTF("Cannot get kernel gic state, no kernel interface");
 449             return;
 450     }
 451
 452     /*****************************************************************
 453      * Distributor State
 454      */
 455
 456     /* GICD_CTLR -> s->ctlr */
 457     kvm_gicd_access(s, 0x0, 0, &reg, false);
 458     s->ctlr = reg;
 459
 460     /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
 461     kvm_gicd_access(s, 0x4, 0, &reg, false);
 462     s->num_irq = ((reg & 0x1f) + 1) * 32;
 463     s->num_cpu = ((reg & 0xe0) >> 5) + 1;
 464
 465     if (s->num_irq > GIC_MAXIRQ) {
 466             fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
 467                     s->num_irq);
 468             abort();
 469     }
 470
 471     /* GICD_IIDR -> ? */
 472     kvm_gicd_access(s, 0x8, 0, &reg, false);
 473
 474     /* Clear all the IRQ settings */
 475     for (i = 0; i < s->num_irq; i++) {
 476         memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
 477     }
 478
 479     /* GICD_IGROUPRn -> irq_state[n].group */
 480     kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
 481
 482     /* GICD_ISENABLERn -> irq_state[n].enabled */
 483     kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
 484
 485     /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
 486     kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
 487
 488     /* GICD_ISACTIVERn -> irq_state[n].active */
 489     kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
 490
 491     /* GICD_ICFRn -> irq_state[n].trigger */
 492     kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
 493
 494     /* GICD_IPRIORITYRn -> s->priorityX[irq] */
 495     kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
 496
 497     /* GICD_ITARGETSRn -> s->irq_target[irq] */
 498     kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
 499
 500     /* GICD_CPENDSGIRn -> s->sgi_pending */
 501     kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
 502
 503
 504     /*****************************************************************
 505      * CPU Interface(s) State
 506      */
 507
 508     for (cpu = 0; cpu < s->num_cpu; cpu++) {
 509         /* GICC_CTLR -> s->cpu_ctlr[cpu] */
 510         kvm_gicc_access(s, 0x00, cpu, &reg, false);
 511         s->cpu_ctlr[cpu] = reg;
 512
 513         /* GICC_PMR -> s->priority_mask[cpu] */
 514         kvm_gicc_access(s, 0x04, cpu, &reg, false);
 515         s->priority_mask[cpu] = (reg & 0xff);
 516
 517         /* GICC_BPR -> s->bpr[cpu] */
 518         kvm_gicc_access(s, 0x08, cpu, &reg, false);
 519         s->bpr[cpu] = (reg & 0x7);
 520
 521         /* GICC_ABPR -> s->abpr[cpu] */
 522         kvm_gicc_access(s, 0x1c, cpu, &reg, false);
 523         s->abpr[cpu] = (reg & 0x7);
 524
 525         /* GICC_APRn -> s->apr[n][cpu] */
 526         for (i = 0; i < 4; i++) {
 527             kvm_gicc_access(s, 0xd0 + i * 4, cpu, &reg, false);
 528             s->apr[i][cpu] = reg;
 529         }
 530     }
 531 }
 532
 533 static void kvm_arm_gic_reset(DeviceState *dev)
 534 {
 535     GICState *s = ARM_GIC_COMMON(dev);
 536     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 537
 538     kgc->parent_reset(dev);
 539     kvm_arm_gic_put(s);
 540 }
 541
 542 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
 543 {
 544     int i;
 545     GICState *s = KVM_ARM_GIC(dev);
 546     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 547     KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
 548     Error *local_err = NULL;
 549     int ret;
 550
 551     kgc->parent_realize(dev, &local_err);
 552     if (local_err) {
 553         error_propagate(errp, local_err);
 554         return;
 555     }
 556
 557     if (s->security_extn) {
 558         error_setg(errp, "the in-kernel VGIC does not implement the "
 559                    "security extensions");
 560         return;
 561     }
 562
 563     i = s->num_irq - GIC_INTERNAL;
 564     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
 565      * GPIO array layout is thus:
 566      *  [0..N-1] SPIs
 567      *  [N..N+31] PPIs for CPU 0
 568      *  [N+32..N+63] PPIs for CPU 1
 569      *   ...
 570      */
 571     i += (GIC_INTERNAL * s->num_cpu);
 572     qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i);
 573
 574     for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
 575         qemu_irq irq = qdev_get_gpio_in(dev, i);
 576         kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
 577     }
 578
 579     /* We never use our outbound IRQ/FIQ lines but provide them so that
 580      * we maintain the same interface as the non-KVM GIC.
 581      */
 582     for (i = 0; i < s->num_cpu; i++) {
 583         sysbus_init_irq(sbd, &s->parent_irq[i]);
 584     }
 585     for (i = 0; i < s->num_cpu; i++) {
 586         sysbus_init_irq(sbd, &s->parent_fiq[i]);
 587     }
 588
 589     /* Try to create the device via the device control API */
 590     s->dev_fd = -1;
 591     ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
 592     if (ret >= 0) {
 593         s->dev_fd = ret;
 594     } else if (ret != -ENODEV && ret != -ENOTSUP) {
 595         error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
 596         return;
 597     }
 598
 599     if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
 600         uint32_t numirqs = s->num_irq;
 601         kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0, 0, &numirqs, 1);
 602     }
 603
 604     /* Tell the kernel to complete VGIC initialization now */
 605     if (kvm_gic_supports_attr(s, KVM_DEV_ARM_VGIC_GRP_CTRL,
 606                               KVM_DEV_ARM_VGIC_CTRL_INIT)) {
 607         kvm_gic_access(s, KVM_DEV_ARM_VGIC_GRP_CTRL,
 608                           KVM_DEV_ARM_VGIC_CTRL_INIT, 0, 0, 1);
 609     }
 610
 611     /* Distributor */
 612     memory_region_init_reservation(&s->iomem, OBJECT(s),
 613                                    "kvm-gic_dist", 0x1000);
 614     sysbus_init_mmio(sbd, &s->iomem);
 615     kvm_arm_register_device(&s->iomem,
 616                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 617                             | KVM_VGIC_V2_ADDR_TYPE_DIST,
 618                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 619                             KVM_VGIC_V2_ADDR_TYPE_DIST,
 620                             s->dev_fd);
 621     /* CPU interface for current core. Unlike arm_gic, we don't
 622      * provide the "interface for core #N" memory regions, because
 623      * cores with a VGIC don't have those.
 624      */
 625     memory_region_init_reservation(&s->cpuiomem[0], OBJECT(s),
 626                                    "kvm-gic_cpu", 0x1000);
 627     sysbus_init_mmio(sbd, &s->cpuiomem[0]);
 628     kvm_arm_register_device(&s->cpuiomem[0],
 629                             (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
 630                             | KVM_VGIC_V2_ADDR_TYPE_CPU,
 631                             KVM_DEV_ARM_VGIC_GRP_ADDR,
 632                             KVM_VGIC_V2_ADDR_TYPE_CPU,
 633                             s->dev_fd);
 634 }
 635
 636 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
 637 {
 638     DeviceClass *dc = DEVICE_CLASS(klass);
 639     ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
 640     KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
 641
 642     agcc->pre_save = kvm_arm_gic_get;
 643     agcc->post_load = kvm_arm_gic_put;
 644     kgc->parent_realize = dc->realize;
 645     kgc->parent_reset = dc->reset;
 646     dc->realize = kvm_arm_gic_realize;
 647     dc->reset = kvm_arm_gic_reset;
 648 }
 649
 650 static const TypeInfo kvm_arm_gic_info = {
 651     .name = TYPE_KVM_ARM_GIC,
 652     .parent = TYPE_ARM_GIC_COMMON,
 653     .instance_size = sizeof(GICState),
 654     .class_init = kvm_arm_gic_class_init,
 655     .class_size = sizeof(KVMARMGICClass),
 656 };
 657
 658 static void kvm_arm_gic_register_types(void)
 659 {
 660     type_register_static(&kvm_arm_gic_info);
 661 }
 662
 663 type_init(kvm_arm_gic_register_types)