target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "sysemu/sysemu.h"
  23
  24 int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  25                               int mmu_idx)
  26 {
  27     LM32CPU *cpu = LM32_CPU(cs);
  28     CPULM32State *env = &cpu->env;
  29     int prot;
  30
  31     address &= TARGET_PAGE_MASK;
  32     prot = PAGE_BITS;
  33     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  34         tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
  35                      TARGET_PAGE_SIZE);
  36     } else {
  37         tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  38     }
  39
  40     return 0;
  41 }
  42
  43 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
  44 {
  45     LM32CPU *cpu = LM32_CPU(cs);
  46
  47     addr &= TARGET_PAGE_MASK;
  48     if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
  49         return addr & 0x7fffffff;
  50     } else {
  51         return addr;
  52     }
  53 }
  54
  55 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
  56 {
  57     LM32CPU *cpu = lm32_env_get_cpu(env);
  58
  59     cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
  60                           &env->cpu_breakpoint[idx]);
  61 }
  62
  63 void lm32_breakpoint_remove(CPULM32State *env, int idx)
  64 {
  65     LM32CPU *cpu = lm32_env_get_cpu(env);
  66
  67     if (!env->cpu_breakpoint[idx]) {
  68         return;
  69     }
  70
  71     cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
  72     env->cpu_breakpoint[idx] = NULL;
  73 }
  74
  75 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
  76                             lm32_wp_t wp_type)
  77 {
  78     LM32CPU *cpu = lm32_env_get_cpu(env);
  79     int flags = 0;
  80
  81     switch (wp_type) {
  82     case LM32_WP_DISABLED:
  83         /* nothing to to */
  84         break;
  85     case LM32_WP_READ:
  86         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
  87         break;
  88     case LM32_WP_WRITE:
  89         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
  90         break;
  91     case LM32_WP_READ_WRITE:
  92         flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
  93         break;
  94     }
  95
  96     if (flags != 0) {
  97         cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
  98                 &env->cpu_watchpoint[idx]);
  99     }
 100 }
 101
 102 void lm32_watchpoint_remove(CPULM32State *env, int idx)
 103 {
 104     LM32CPU *cpu = lm32_env_get_cpu(env);
 105
 106     if (!env->cpu_watchpoint[idx]) {
 107         return;
 108     }
 109
 110     cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
 111     env->cpu_watchpoint[idx] = NULL;
 112 }
 113
 114 static bool check_watchpoints(CPULM32State *env)
 115 {
 116     LM32CPU *cpu = lm32_env_get_cpu(env);
 117     int i;
 118
 119     for (i = 0; i < cpu->num_watchpoints; i++) {
 120         if (env->cpu_watchpoint[i] &&
 121                 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
 122             return true;
 123         }
 124     }
 125     return false;
 126 }
 127
 128 void lm32_debug_excp_handler(CPUState *cs)
 129 {
 130     LM32CPU *cpu = LM32_CPU(cs);
 131     CPULM32State *env = &cpu->env;
 132     CPUBreakpoint *bp;
 133
 134     if (cs->watchpoint_hit) {
 135         if (cs->watchpoint_hit->flags & BP_CPU) {
 136             cs->watchpoint_hit = NULL;
 137             if (check_watchpoints(env)) {
 138                 raise_exception(env, EXCP_WATCHPOINT);
 139             } else {
 140                 cpu_resume_from_signal(cs, NULL);
 141             }
 142         }
 143     } else {
 144         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 145             if (bp->pc == env->pc) {
 146                 if (bp->flags & BP_CPU) {
 147                     raise_exception(env, EXCP_BREAKPOINT);
 148                 }
 149                 break;
 150             }
 151         }
 152     }
 153 }
 154
 155 void lm32_cpu_do_interrupt(CPUState *cs)
 156 {
 157     LM32CPU *cpu = LM32_CPU(cs);
 158     CPULM32State *env = &cpu->env;
 159
 160     qemu_log_mask(CPU_LOG_INT,
 161             "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
 162
 163     switch (cs->exception_index) {
 164     case EXCP_SYSTEMCALL:
 165         if (unlikely(semihosting_enabled)) {
 166             /* do_semicall() returns true if call was handled. Otherwise
 167              * do the normal exception handling. */
 168             if (lm32_cpu_do_semihosting(cs)) {
 169                 env->pc += 4;
 170                 break;
 171             }
 172         }
 173         /* fall through */
 174     case EXCP_INSN_BUS_ERROR:
 175     case EXCP_DATA_BUS_ERROR:
 176     case EXCP_DIVIDE_BY_ZERO:
 177     case EXCP_IRQ:
 178         /* non-debug exceptions */
 179         env->regs[R_EA] = env->pc;
 180         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
 181         env->ie &= ~IE_IE;
 182         if (env->dc & DC_RE) {
 183             env->pc = env->deba + (cs->exception_index * 32);
 184         } else {
 185             env->pc = env->eba + (cs->exception_index * 32);
 186         }
 187         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 188         break;
 189     case EXCP_BREAKPOINT:
 190     case EXCP_WATCHPOINT:
 191         /* debug exceptions */
 192         env->regs[R_BA] = env->pc;
 193         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
 194         env->ie &= ~IE_IE;
 195         env->pc = env->deba + (cs->exception_index * 32);
 196         log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 197         break;
 198     default:
 199         cpu_abort(cs, "unhandled exception type=%d\n",
 200                   cs->exception_index);
 201         break;
 202     }
 203 }
 204
 205 bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 206 {
 207     LM32CPU *cpu = LM32_CPU(cs);
 208     CPULM32State *env = &cpu->env;
 209
 210     if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
 211         cs->exception_index = EXCP_IRQ;
 212         lm32_cpu_do_interrupt(cs);
 213         return true;
 214     }
 215     return false;
 216 }
 217
 218 LM32CPU *cpu_lm32_init(const char *cpu_model)
 219 {
 220     return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
 221 }
 222
 223 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 224  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 225  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 226 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 227 {
 228     if (value) {
 229         env->flags |= LM32_FLAG_IGNORE_MSB;
 230     } else {
 231         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 232     }
 233 }