2 * ASPEED SDRAM Memory Controller
4 * Copyright (C) 2016 IBM Corp.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
12 #include "hw/sysbus.h"
13 #include "qom/object.h"
15 #define TYPE_ASPEED_SDMC "aspeed.sdmc"
16 OBJECT_DECLARE_TYPE(AspeedSDMCState
, AspeedSDMCClass
, ASPEED_SDMC
)
17 #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
18 #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
19 #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
22 * SDMC has 174 documented registers. In addition the u-boot device tree
23 * describes the following regions:
24 * - PHY status regs at offset 0x400, length 0x200
25 * - PHY setting regs at offset 0x100, length 0x300
27 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
28 * system: one is in the SDRAM MC (memory controller) which is used in run
29 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
32 #define ASPEED_SDMC_NR_REGS (0x500 >> 2)
34 struct AspeedSDMCState
{
36 SysBusDevice parent_obj
;
41 uint32_t regs
[ASPEED_SDMC_NR_REGS
];
43 uint64_t max_ram_size
;
47 struct AspeedSDMCClass
{
48 SysBusDeviceClass parent_class
;
50 uint64_t max_ram_size
;
51 const uint64_t *valid_ram_sizes
;
52 uint32_t (*compute_conf
)(AspeedSDMCState
*s
, uint32_t data
);
53 void (*write
)(AspeedSDMCState
*s
, uint32_t reg
, uint32_t data
);
56 #endif /* ASPEED_SDMC_H */