target/arm: Fix decode for VDOT (indexed)
[qemu.git] / include / hw / char / avr_usart.h
blob62eaa1528efffbac8b90ccde0de1bc6614780dbc
1 /*
2 * AVR USART
4 * Copyright (c) 2018 University of Kent
5 * Author: Sarah Harris
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 #ifndef HW_CHAR_AVR_USART_H
23 #define HW_CHAR_AVR_USART_H
25 #include "hw/sysbus.h"
26 #include "chardev/char-fe.h"
27 #include "qom/object.h"
29 /* Offsets of registers. */
30 #define USART_DR 0x06
31 #define USART_CSRA 0x00
32 #define USART_CSRB 0x01
33 #define USART_CSRC 0x02
34 #define USART_BRRH 0x05
35 #define USART_BRRL 0x04
37 /* Relevant bits in regiters. */
38 #define USART_CSRA_RXC (1 << 7)
39 #define USART_CSRA_TXC (1 << 6)
40 #define USART_CSRA_DRE (1 << 5)
41 #define USART_CSRA_MPCM (1 << 0)
43 #define USART_CSRB_RXCIE (1 << 7)
44 #define USART_CSRB_TXCIE (1 << 6)
45 #define USART_CSRB_DREIE (1 << 5)
46 #define USART_CSRB_RXEN (1 << 4)
47 #define USART_CSRB_TXEN (1 << 3)
48 #define USART_CSRB_CSZ2 (1 << 2)
49 #define USART_CSRB_RXB8 (1 << 1)
50 #define USART_CSRB_TXB8 (1 << 0)
52 #define USART_CSRC_MSEL1 (1 << 7)
53 #define USART_CSRC_MSEL0 (1 << 6)
54 #define USART_CSRC_PM1 (1 << 5)
55 #define USART_CSRC_PM0 (1 << 4)
56 #define USART_CSRC_CSZ1 (1 << 2)
57 #define USART_CSRC_CSZ0 (1 << 1)
59 #define TYPE_AVR_USART "avr-usart"
60 OBJECT_DECLARE_SIMPLE_TYPE(AVRUsartState, AVR_USART)
62 struct AVRUsartState {
63 /* <private> */
64 SysBusDevice parent_obj;
66 /* <public> */
67 MemoryRegion mmio;
69 CharBackend chr;
71 bool enabled;
73 uint8_t data;
74 bool data_valid;
75 uint8_t char_mask;
76 /* Control and Status Registers */
77 uint8_t csra;
78 uint8_t csrb;
79 uint8_t csrc;
80 /* Baud Rate Registers (low/high byte) */
81 uint8_t brrh;
82 uint8_t brrl;
84 /* Receive Complete */
85 qemu_irq rxc_irq;
86 /* Transmit Complete */
87 qemu_irq txc_irq;
88 /* Data Register Empty */
89 qemu_irq dre_irq;
92 #endif /* HW_CHAR_AVR_USART_H */