target/sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "qemu-common.h"
  27 #include "migration/vmstate.h"
  28 #include "exec/exec-all.h"
  29 #include "fpu/softfloat.h"
  30
  31
  32 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     SuperHCPU *cpu = SUPERH_CPU(cs);
  35
  36     cpu->env.pc = value;
  37 }
  38
  39 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  40 {
  41     SuperHCPU *cpu = SUPERH_CPU(cs);
  42
  43     cpu->env.pc = tb->pc;
  44     cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
  45 }
  46
  47 static bool superh_cpu_has_work(CPUState *cs)
  48 {
  49     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  50 }
  51
  52 /* CPUClass::reset() */
  53 static void superh_cpu_reset(CPUState *s)
  54 {
  55     SuperHCPU *cpu = SUPERH_CPU(s);
  56     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  57     CPUSH4State *env = &cpu->env;
  58
  59     scc->parent_reset(s);
  60
  61     memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
  62
  63     env->pc = 0xA0000000;
  64 #if defined(CONFIG_USER_ONLY)
  65     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  66     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  67 #else
  68     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  69               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  70     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  71     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  72     set_flush_to_zero(1, &env->fp_status);
  73 #endif
  74     set_default_nan_mode(1, &env->fp_status);
  75 }
  76
  77 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  78 {
  79     info->mach = bfd_mach_sh4;
  80     info->print_insn = print_insn_sh;
  81 }
  82
  83 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  84 {
  85     const char *typename = object_class_get_name(OBJECT_CLASS(data));
  86     int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
  87
  88     qemu_printf("%.*s\n", len, typename);
  89 }
  90
  91 void sh4_cpu_list(void)
  92 {
  93     GSList *list;
  94
  95     list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false);
  96     g_slist_foreach(list, superh_cpu_list_entry, NULL);
  97     g_slist_free(list);
  98 }
  99
 100 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 101 {
 102     ObjectClass *oc;
 103     char *s, *typename = NULL;
 104
 105     s = g_ascii_strdown(cpu_model, -1);
 106     if (strcmp(s, "any") == 0) {
 107         oc = object_class_by_name(TYPE_SH7750R_CPU);
 108         goto out;
 109     }
 110
 111     typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
 112     oc = object_class_by_name(typename);
 113     if (oc != NULL && object_class_is_abstract(oc)) {
 114         oc = NULL;
 115     }
 116
 117 out:
 118     g_free(s);
 119     g_free(typename);
 120     return oc;
 121 }
 122
 123 static void sh7750r_cpu_initfn(Object *obj)
 124 {
 125     SuperHCPU *cpu = SUPERH_CPU(obj);
 126     CPUSH4State *env = &cpu->env;
 127
 128     env->id = SH_CPU_SH7750R;
 129     env->features = SH_FEATURE_BCR3_AND_BCR4;
 130 }
 131
 132 static void sh7750r_class_init(ObjectClass *oc, void *data)
 133 {
 134     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 135
 136     scc->pvr = 0x00050000;
 137     scc->prr = 0x00000100;
 138     scc->cvr = 0x00110000;
 139 }
 140
 141 static void sh7751r_cpu_initfn(Object *obj)
 142 {
 143     SuperHCPU *cpu = SUPERH_CPU(obj);
 144     CPUSH4State *env = &cpu->env;
 145
 146     env->id = SH_CPU_SH7751R;
 147     env->features = SH_FEATURE_BCR3_AND_BCR4;
 148 }
 149
 150 static void sh7751r_class_init(ObjectClass *oc, void *data)
 151 {
 152     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 153
 154     scc->pvr = 0x04050005;
 155     scc->prr = 0x00000113;
 156     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 157 }
 158
 159 static void sh7785_cpu_initfn(Object *obj)
 160 {
 161     SuperHCPU *cpu = SUPERH_CPU(obj);
 162     CPUSH4State *env = &cpu->env;
 163
 164     env->id = SH_CPU_SH7785;
 165     env->features = SH_FEATURE_SH4A;
 166 }
 167
 168 static void sh7785_class_init(ObjectClass *oc, void *data)
 169 {
 170     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 171
 172     scc->pvr = 0x10300700;
 173     scc->prr = 0x00000200;
 174     scc->cvr = 0x71440211;
 175 }
 176
 177 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 178 {
 179     CPUState *cs = CPU(dev);
 180     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 181     Error *local_err = NULL;
 182
 183     cpu_exec_realizefn(cs, &local_err);
 184     if (local_err != NULL) {
 185         error_propagate(errp, local_err);
 186         return;
 187     }
 188
 189     cpu_reset(cs);
 190     qemu_init_vcpu(cs);
 191
 192     scc->parent_realize(dev, errp);
 193 }
 194
 195 static void superh_cpu_initfn(Object *obj)
 196 {
 197     CPUState *cs = CPU(obj);
 198     SuperHCPU *cpu = SUPERH_CPU(obj);
 199     CPUSH4State *env = &cpu->env;
 200
 201     cs->env_ptr = env;
 202
 203     env->movcal_backup_tail = &(env->movcal_backup);
 204 }
 205
 206 static const VMStateDescription vmstate_sh_cpu = {
 207     .name = "cpu",
 208     .unmigratable = 1,
 209 };
 210
 211 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 212 {
 213     DeviceClass *dc = DEVICE_CLASS(oc);
 214     CPUClass *cc = CPU_CLASS(oc);
 215     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 216
 217     device_class_set_parent_realize(dc, superh_cpu_realizefn,
 218                                     &scc->parent_realize);
 219
 220     scc->parent_reset = cc->reset;
 221     cc->reset = superh_cpu_reset;
 222
 223     cc->class_by_name = superh_cpu_class_by_name;
 224     cc->has_work = superh_cpu_has_work;
 225     cc->do_interrupt = superh_cpu_do_interrupt;
 226     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 227     cc->dump_state = superh_cpu_dump_state;
 228     cc->set_pc = superh_cpu_set_pc;
 229     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 230     cc->gdb_read_register = superh_cpu_gdb_read_register;
 231     cc->gdb_write_register = superh_cpu_gdb_write_register;
 232 #ifdef CONFIG_USER_ONLY
 233     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 234 #else
 235     cc->do_unaligned_access = superh_cpu_do_unaligned_access;
 236     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 237 #endif
 238     cc->disas_set_info = superh_cpu_disas_set_info;
 239     cc->tcg_initialize = sh4_translate_init;
 240
 241     cc->gdb_num_core_regs = 59;
 242
 243     dc->vmsd = &vmstate_sh_cpu;
 244 }
 245
 246 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
 247     {                                                    \
 248         .name = type_name,                               \
 249         .parent = TYPE_SUPERH_CPU,                       \
 250         .class_init = cinit,                             \
 251         .instance_init = initfn,                         \
 252     }
 253 static const TypeInfo superh_cpu_type_infos[] = {
 254     {
 255         .name = TYPE_SUPERH_CPU,
 256         .parent = TYPE_CPU,
 257         .instance_size = sizeof(SuperHCPU),
 258         .instance_init = superh_cpu_initfn,
 259         .abstract = true,
 260         .class_size = sizeof(SuperHCPUClass),
 261         .class_init = superh_cpu_class_init,
 262     },
 263     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
 264                            sh7750r_cpu_initfn),
 265     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
 266                            sh7751r_cpu_initfn),
 267     DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
 268                            sh7785_cpu_initfn),
 269
 270 };
 271
 272 DEFINE_TYPES(superh_cpu_type_infos)