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Fix typos in comments (accessable -> accessible, priveleged -> privileged)
[qemu.git] / hw / usb-musb.c
blobb30caeb4e8c4b2332c3c220e7f53ed33cca1a3af
1 /*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "usb.h"
26 #include "irq.h"
27 #include "hw.h"
28
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46 /* EP FIFOs */
47 #define MUSB_HDRC_FIFO 0x20
48
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
68
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
83
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
105
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
109
110 /*
111 * MUSBHDRC Register bit masks
112 */
113
114 /* POWER */
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
123
124 /* INTRUSB */
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136 /* DEVCTL */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
145
146 /* TESTMODE */
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
155
156 /* CSR0 */
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
160
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
179
180 /* CONFIGDATA */
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
214
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
240
241 /* HUBADDR */
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
243
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
251
252 /* #define MUSB_DEBUG */
253
254 #ifdef MUSB_DEBUG
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257 #else
258 #define TRACE(...)
259 #endif
260
261
262 static void musb_attach(USBPort *port);
263 static void musb_detach(USBPort *port);
264 static void musb_schedule_cb(USBDevice *dev, USBPacket *p);
265
266 static USBPortOps musb_port_ops = {
267 .attach = musb_attach,
268 .detach = musb_detach,
269 .complete = musb_schedule_cb,
270 };
271
272 typedef struct MUSBPacket MUSBPacket;
273 typedef struct MUSBEndPoint MUSBEndPoint;
274
275 struct MUSBPacket {
276 USBPacket p;
277 MUSBEndPoint *ep;
278 int dir;
279 };
280
281 struct MUSBEndPoint {
282 uint16_t faddr[2];
283 uint8_t haddr[2];
284 uint8_t hport[2];
285 uint16_t csr[2];
286 uint16_t maxp[2];
287 uint16_t rxcount;
288 uint8_t type[2];
289 uint8_t interval[2];
290 uint8_t config;
291 uint8_t fifosize;
292 int timeout[2]; /* Always in microframes */
293
294 uint8_t *buf[2];
295 int fifolen[2];
296 int fifostart[2];
297 int fifoaddr[2];
298 MUSBPacket packey[2];
299 int status[2];
300 int ext_size[2];
301
302 /* For callbacks' use */
303 int epnum;
304 int interrupt[2];
305 MUSBState *musb;
306 USBCallback *delayed_cb[2];
307 QEMUTimer *intv_timer[2];
308 };
309
310 struct MUSBState {
311 qemu_irq *irqs;
312 USBBus bus;
313 USBPort port;
314
315 int idx;
316 uint8_t devctl;
317 uint8_t power;
318 uint8_t faddr;
319
320 uint8_t intr;
321 uint8_t mask;
322 uint16_t tx_intr;
323 uint16_t tx_mask;
324 uint16_t rx_intr;
325 uint16_t rx_mask;
326
327 int setup_len;
328 int session;
329
330 uint8_t buf[0x8000];
331
332 /* Duplicating the world since 2008!... probably we should have 32
333 * logical, single endpoints instead. */
334 MUSBEndPoint ep[16];
335 };
336
337 struct MUSBState *musb_init(qemu_irq *irqs)
338 {
339 MUSBState *s = qemu_mallocz(sizeof(*s));
340 int i;
341
342 s->irqs = irqs;
343
344 s->faddr = 0x00;
345 s->power = MGC_M_POWER_HSENAB;
346 s->tx_intr = 0x0000;
347 s->rx_intr = 0x0000;
348 s->tx_mask = 0xffff;
349 s->rx_mask = 0xffff;
350 s->intr = 0x00;
351 s->mask = 0x06;
352 s->idx = 0;
353
354 /* TODO: _DW */
355 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
356 for (i = 0; i < 16; i ++) {
357 s->ep[i].fifosize = 64;
358 s->ep[i].maxp[0] = 0x40;
359 s->ep[i].maxp[1] = 0x40;
360 s->ep[i].musb = s;
361 s->ep[i].epnum = i;
362 }
363
364 usb_bus_new(&s->bus, NULL /* FIXME */);
365 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
366 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
367 usb_port_location(&s->port, NULL, 1);
368
369 return s;
370 }
371
372 static void musb_vbus_set(MUSBState *s, int level)
373 {
374 if (level)
375 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
376 else
377 s->devctl &= ~MGC_M_DEVCTL_VBUS;
378
379 qemu_set_irq(s->irqs[musb_set_vbus], level);
380 }
381
382 static void musb_intr_set(MUSBState *s, int line, int level)
383 {
384 if (!level) {
385 s->intr &= ~(1 << line);
386 qemu_irq_lower(s->irqs[line]);
387 } else if (s->mask & (1 << line)) {
388 s->intr |= 1 << line;
389 qemu_irq_raise(s->irqs[line]);
390 }
391 }
392
393 static void musb_tx_intr_set(MUSBState *s, int line, int level)
394 {
395 if (!level) {
396 s->tx_intr &= ~(1 << line);
397 if (!s->tx_intr)
398 qemu_irq_lower(s->irqs[musb_irq_tx]);
399 } else if (s->tx_mask & (1 << line)) {
400 s->tx_intr |= 1 << line;
401 qemu_irq_raise(s->irqs[musb_irq_tx]);
402 }
403 }
404
405 static void musb_rx_intr_set(MUSBState *s, int line, int level)
406 {
407 if (line) {
408 if (!level) {
409 s->rx_intr &= ~(1 << line);
410 if (!s->rx_intr)
411 qemu_irq_lower(s->irqs[musb_irq_rx]);
412 } else if (s->rx_mask & (1 << line)) {
413 s->rx_intr |= 1 << line;
414 qemu_irq_raise(s->irqs[musb_irq_rx]);
415 }
416 } else
417 musb_tx_intr_set(s, line, level);
418 }
419
420 uint32_t musb_core_intr_get(MUSBState *s)
421 {
422 return (s->rx_intr << 15) | s->tx_intr;
423 }
424
425 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
426 {
427 if (s->rx_intr) {
428 s->rx_intr &= mask >> 15;
429 if (!s->rx_intr)
430 qemu_irq_lower(s->irqs[musb_irq_rx]);
431 }
432
433 if (s->tx_intr) {
434 s->tx_intr &= mask & 0xffff;
435 if (!s->tx_intr)
436 qemu_irq_lower(s->irqs[musb_irq_tx]);
437 }
438 }
439
440 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
441 {
442 s->ep[epnum].ext_size[!is_tx] = size;
443 s->ep[epnum].fifostart[0] = 0;
444 s->ep[epnum].fifostart[1] = 0;
445 s->ep[epnum].fifolen[0] = 0;
446 s->ep[epnum].fifolen[1] = 0;
447 }
448
449 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
450 {
451 int detect_prev = prev_dev && prev_sess;
452 int detect = !!s->port.dev && s->session;
453
454 if (detect && !detect_prev) {
455 /* Let's skip the ID pin sense and VBUS sense formalities and
456 * and signal a successful SRP directly. This should work at least
457 * for the Linux driver stack. */
458 musb_intr_set(s, musb_irq_connect, 1);
459
460 if (s->port.dev->speed == USB_SPEED_LOW) {
461 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
462 s->devctl |= MGC_M_DEVCTL_LSDEV;
463 } else {
464 s->devctl |= MGC_M_DEVCTL_FSDEV;
465 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
466 }
467
468 /* A-mode? */
469 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
470
471 /* Host-mode bit? */
472 s->devctl |= MGC_M_DEVCTL_HM;
473 #if 1
474 musb_vbus_set(s, 1);
475 #endif
476 } else if (!detect && detect_prev) {
477 #if 1
478 musb_vbus_set(s, 0);
479 #endif
480 }
481 }
482
483 /* Attach or detach a device on our only port. */
484 static void musb_attach(USBPort *port)
485 {
486 MUSBState *s = (MUSBState *) port->opaque;
487
488 musb_intr_set(s, musb_irq_vbus_request, 1);
489 musb_session_update(s, 0, s->session);
490 }
491
492 static void musb_detach(USBPort *port)
493 {
494 MUSBState *s = (MUSBState *) port->opaque;
495
496 musb_intr_set(s, musb_irq_disconnect, 1);
497 musb_session_update(s, 1, s->session);
498 }
499
500 static inline void musb_cb_tick0(void *opaque)
501 {
502 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
503
504 ep->delayed_cb[0](&ep->packey[0].p, opaque);
505 }
506
507 static inline void musb_cb_tick1(void *opaque)
508 {
509 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
510
511 ep->delayed_cb[1](&ep->packey[1].p, opaque);
512 }
513
514 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
515
516 static inline void musb_schedule_cb(USBDevice *dev, USBPacket *packey)
517 {
518 MUSBPacket *p = container_of(packey, MUSBPacket, p);
519 MUSBEndPoint *ep = p->ep;
520 int dir = p->dir;
521 int timeout = 0;
522
523 if (ep->status[dir] == USB_RET_NAK)
524 timeout = ep->timeout[dir];
525 else if (ep->interrupt[dir])
526 timeout = 8;
527 else
528 return musb_cb_tick(ep);
529
530 if (!ep->intv_timer[dir])
531 ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, ep);
532
533 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
534 muldiv64(timeout, get_ticks_per_sec(), 8000));
535 }
536
537 static int musb_timeout(int ttype, int speed, int val)
538 {
539 #if 1
540 return val << 3;
541 #endif
542
543 switch (ttype) {
544 case USB_ENDPOINT_XFER_CONTROL:
545 if (val < 2)
546 return 0;
547 else if (speed == USB_SPEED_HIGH)
548 return 1 << (val - 1);
549 else
550 return 8 << (val - 1);
551
552 case USB_ENDPOINT_XFER_INT:
553 if (speed == USB_SPEED_HIGH)
554 if (val < 2)
555 return 0;
556 else
557 return 1 << (val - 1);
558 else
559 return val << 3;
560
561 case USB_ENDPOINT_XFER_BULK:
562 case USB_ENDPOINT_XFER_ISOC:
563 if (val < 2)
564 return 0;
565 else if (speed == USB_SPEED_HIGH)
566 return 1 << (val - 1);
567 else
568 return 8 << (val - 1);
569 /* TODO: what with low-speed Bulk and Isochronous? */
570 }
571
572 hw_error("bad interval\n");
573 }
574
575 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
576 int epnum, int pid, int len, USBCallback cb, int dir)
577 {
578 int ret;
579 int idx = epnum && dir;
580 int ttype;
581
582 /* ep->type[0,1] contains:
583 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
584 * in bits 5:4 the transfer type (BULK / INT)
585 * in bits 3:0 the EP num
586 */
587 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
588
589 ep->timeout[dir] = musb_timeout(ttype,
590 ep->type[idx] >> 6, ep->interval[idx]);
591 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
592 ep->delayed_cb[dir] = cb;
593
594 ep->packey[dir].p.pid = pid;
595 /* A wild guess on the FADDR semantics... */
596 ep->packey[dir].p.devaddr = ep->faddr[idx];
597 ep->packey[dir].p.devep = ep->type[idx] & 0xf;
598 ep->packey[dir].p.data = (void *) ep->buf[idx];
599 ep->packey[dir].p.len = len;
600 ep->packey[dir].ep = ep;
601 ep->packey[dir].dir = dir;
602
603 if (s->port.dev)
604 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir].p);
605 else
606 ret = USB_RET_NODEV;
607
608 if (ret == USB_RET_ASYNC) {
609 ep->status[dir] = len;
610 return;
611 }
612
613 ep->status[dir] = ret;
614 usb_packet_complete(s->port.dev, &ep->packey[dir].p);
615 }
616
617 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
618 {
619 /* Unfortunately we can't use packey->devep because that's the remote
620 * endpoint number and may be different than our local. */
621 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
622 int epnum = ep->epnum;
623 MUSBState *s = ep->musb;
624
625 ep->fifostart[0] = 0;
626 ep->fifolen[0] = 0;
627 #ifdef CLEAR_NAK
628 if (ep->status[0] != USB_RET_NAK) {
629 #endif
630 if (epnum)
631 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
632 else
633 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
634 #ifdef CLEAR_NAK
635 }
636 #endif
637
638 /* Clear all of the error bits first */
639 if (epnum)
640 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
641 MGC_M_TXCSR_H_NAKTIMEOUT);
642 else
643 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
644 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
645
646 if (ep->status[0] == USB_RET_STALL) {
647 /* Command not supported by target! */
648 ep->status[0] = 0;
649
650 if (epnum)
651 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
652 else
653 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
654 }
655
656 if (ep->status[0] == USB_RET_NAK) {
657 ep->status[0] = 0;
658
659 /* NAK timeouts are only generated in Bulk transfers and
660 * Data-errors in Isochronous. */
661 if (ep->interrupt[0]) {
662 return;
663 }
664
665 if (epnum)
666 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
667 else
668 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
669 }
670
671 if (ep->status[0] < 0) {
672 if (ep->status[0] == USB_RET_BABBLE)
673 musb_intr_set(s, musb_irq_rst_babble, 1);
674
675 /* Pretend we've tried three times already and failed (in
676 * case of USB_TOKEN_SETUP). */
677 if (epnum)
678 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
679 else
680 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
681
682 musb_tx_intr_set(s, epnum, 1);
683 return;
684 }
685 /* TODO: check len for over/underruns of an OUT packet? */
686
687 #ifdef SETUPLEN_HACK
688 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
689 s->setup_len = ep->packey[0].data[6];
690 #endif
691
692 /* In DMA mode: if no error, assert DMA request for this EP,
693 * and skip the interrupt. */
694 musb_tx_intr_set(s, epnum, 1);
695 }
696
697 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
698 {
699 /* Unfortunately we can't use packey->devep because that's the remote
700 * endpoint number and may be different than our local. */
701 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
702 int epnum = ep->epnum;
703 MUSBState *s = ep->musb;
704
705 ep->fifostart[1] = 0;
706 ep->fifolen[1] = 0;
707
708 #ifdef CLEAR_NAK
709 if (ep->status[1] != USB_RET_NAK) {
710 #endif
711 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
712 if (!epnum)
713 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
714 #ifdef CLEAR_NAK
715 }
716 #endif
717
718 /* Clear all of the imaginable error bits first */
719 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
720 MGC_M_RXCSR_DATAERROR);
721 if (!epnum)
722 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
723 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
724
725 if (ep->status[1] == USB_RET_STALL) {
726 ep->status[1] = 0;
727 packey->len = 0;
728
729 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
730 if (!epnum)
731 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
732 }
733
734 if (ep->status[1] == USB_RET_NAK) {
735 ep->status[1] = 0;
736
737 /* NAK timeouts are only generated in Bulk transfers and
738 * Data-errors in Isochronous. */
739 if (ep->interrupt[1])
740 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
741 packey->len, musb_rx_packet_complete, 1);
742
743 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
744 if (!epnum)
745 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
746 }
747
748 if (ep->status[1] < 0) {
749 if (ep->status[1] == USB_RET_BABBLE) {
750 musb_intr_set(s, musb_irq_rst_babble, 1);
751 return;
752 }
753
754 /* Pretend we've tried three times already and failed (in
755 * case of a control transfer). */
756 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
757 if (!epnum)
758 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
759
760 musb_rx_intr_set(s, epnum, 1);
761 return;
762 }
763 /* TODO: check len for over/underruns of an OUT packet? */
764 /* TODO: perhaps make use of e->ext_size[1] here. */
765
766 packey->len = ep->status[1];
767
768 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
769 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
770 if (!epnum)
771 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
772
773 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
774 /* In DMA mode: assert DMA request for this EP */
775 }
776
777 /* Only if DMA has not been asserted */
778 musb_rx_intr_set(s, epnum, 1);
779 }
780
781 static void musb_tx_rdy(MUSBState *s, int epnum)
782 {
783 MUSBEndPoint *ep = s->ep + epnum;
784 int pid;
785 int total, valid = 0;
786 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
787 ep->fifostart[0] += ep->fifolen[0];
788 ep->fifolen[0] = 0;
789
790 /* XXX: how's the total size of the packet retrieved exactly in
791 * the generic case? */
792 total = ep->maxp[0] & 0x3ff;
793
794 if (ep->ext_size[0]) {
795 total = ep->ext_size[0];
796 ep->ext_size[0] = 0;
797 valid = 1;
798 }
799
800 /* If the packet is not fully ready yet, wait for a next segment. */
801 if (epnum && (ep->fifostart[0]) < total)
802 return;
803
804 if (!valid)
805 total = ep->fifostart[0];
806
807 pid = USB_TOKEN_OUT;
808 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
809 pid = USB_TOKEN_SETUP;
810 if (total != 8) {
811 TRACE("illegal SETUPPKT length of %i bytes", total);
812 }
813 /* Controller should retry SETUP packets three times on errors
814 * but it doesn't make sense for us to do that. */
815 }
816
817 return musb_packet(s, ep, epnum, pid,
818 total, musb_tx_packet_complete, 0);
819 }
820
821 static void musb_rx_req(MUSBState *s, int epnum)
822 {
823 MUSBEndPoint *ep = s->ep + epnum;
824 int total;
825
826 /* If we already have a packet, which didn't fit into the
827 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
828 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
829 (ep->fifostart[1]) + ep->rxcount <
830 ep->packey[1].p.len) {
831 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
832 ep->fifostart[1] += ep->rxcount;
833 ep->fifolen[1] = 0;
834
835 ep->rxcount = MIN(ep->packey[0].p.len - (ep->fifostart[1]),
836 ep->maxp[1]);
837
838 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
839 if (!epnum)
840 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
841
842 /* Clear all of the error bits first */
843 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
844 MGC_M_RXCSR_DATAERROR);
845 if (!epnum)
846 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
847 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
848
849 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
850 if (!epnum)
851 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
852 musb_rx_intr_set(s, epnum, 1);
853 return;
854 }
855
856 /* The driver sets maxp[1] to 64 or less because it knows the hardware
857 * FIFO is this deep. Bigger packets get split in
858 * usb_generic_handle_packet but we can also do the splitting locally
859 * for performance. It turns out we can also have a bigger FIFO and
860 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
861 * OK with single packets of even 32KB and we avoid splitting, however
862 * usb_msd.c sometimes sends a packet bigger than what Linux expects
863 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
864 * hides this overrun from Linux. Up to 4096 everything is fine
865 * though. Currently this is disabled.
866 *
867 * XXX: mind ep->fifosize. */
868 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
869
870 #ifdef SETUPLEN_HACK
871 /* Why should *we* do that instead of Linux? */
872 if (!epnum) {
873 if (ep->packey[0].p.devaddr == 2) {
874 total = MIN(s->setup_len, 8);
875 } else {
876 total = MIN(s->setup_len, 64);
877 }
878 s->setup_len -= total;
879 }
880 #endif
881
882 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
883 total, musb_rx_packet_complete, 1);
884 }
885
886 static uint8_t musb_read_fifo(MUSBEndPoint *ep)
887 {
888 uint8_t value;
889 if (ep->fifolen[1] >= 64) {
890 /* We have a FIFO underrun */
891 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
892 return 0x00000000;
893 }
894 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
895 * (if AUTOREQ is set) */
896
897 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
898 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
899 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
900 return value;
901 }
902
903 static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
904 {
905 TRACE("EP%d = %02x", ep->epnum, value);
906 if (ep->fifolen[0] >= 64) {
907 /* We have a FIFO overrun */
908 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
909 return;
910 }
911
912 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
913 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
914 }
915
916 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
917 {
918 if (ep->intv_timer[dir])
919 qemu_del_timer(ep->intv_timer[dir]);
920 }
921
922 /* Bus control */
923 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
924 {
925 MUSBState *s = (MUSBState *) opaque;
926
927 switch (addr) {
928 /* For USB2.0 HS hubs only */
929 case MUSB_HDRC_TXHUBADDR:
930 return s->ep[ep].haddr[0];
931 case MUSB_HDRC_TXHUBPORT:
932 return s->ep[ep].hport[0];
933 case MUSB_HDRC_RXHUBADDR:
934 return s->ep[ep].haddr[1];
935 case MUSB_HDRC_RXHUBPORT:
936 return s->ep[ep].hport[1];
937
938 default:
939 TRACE("unknown register 0x%02x", addr);
940 return 0x00;
941 };
942 }
943
944 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
945 {
946 MUSBState *s = (MUSBState *) opaque;
947
948 switch (addr) {
949 case MUSB_HDRC_TXFUNCADDR:
950 s->ep[ep].faddr[0] = value;
951 break;
952 case MUSB_HDRC_RXFUNCADDR:
953 s->ep[ep].faddr[1] = value;
954 break;
955 case MUSB_HDRC_TXHUBADDR:
956 s->ep[ep].haddr[0] = value;
957 break;
958 case MUSB_HDRC_TXHUBPORT:
959 s->ep[ep].hport[0] = value;
960 break;
961 case MUSB_HDRC_RXHUBADDR:
962 s->ep[ep].haddr[1] = value;
963 break;
964 case MUSB_HDRC_RXHUBPORT:
965 s->ep[ep].hport[1] = value;
966 break;
967
968 default:
969 TRACE("unknown register 0x%02x", addr);
970 break;
971 };
972 }
973
974 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
975 {
976 MUSBState *s = (MUSBState *) opaque;
977
978 switch (addr) {
979 case MUSB_HDRC_TXFUNCADDR:
980 return s->ep[ep].faddr[0];
981 case MUSB_HDRC_RXFUNCADDR:
982 return s->ep[ep].faddr[1];
983
984 default:
985 return musb_busctl_readb(s, ep, addr) |
986 (musb_busctl_readb(s, ep, addr | 1) << 8);
987 };
988 }
989
990 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
991 {
992 MUSBState *s = (MUSBState *) opaque;
993
994 switch (addr) {
995 case MUSB_HDRC_TXFUNCADDR:
996 s->ep[ep].faddr[0] = value;
997 break;
998 case MUSB_HDRC_RXFUNCADDR:
999 s->ep[ep].faddr[1] = value;
1000 break;
1001
1002 default:
1003 musb_busctl_writeb(s, ep, addr, value & 0xff);
1004 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1005 };
1006 }
1007
1008 /* Endpoint control */
1009 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1010 {
1011 MUSBState *s = (MUSBState *) opaque;
1012
1013 switch (addr) {
1014 case MUSB_HDRC_TXTYPE:
1015 return s->ep[ep].type[0];
1016 case MUSB_HDRC_TXINTERVAL:
1017 return s->ep[ep].interval[0];
1018 case MUSB_HDRC_RXTYPE:
1019 return s->ep[ep].type[1];
1020 case MUSB_HDRC_RXINTERVAL:
1021 return s->ep[ep].interval[1];
1022 case (MUSB_HDRC_FIFOSIZE & ~1):
1023 return 0x00;
1024 case MUSB_HDRC_FIFOSIZE:
1025 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
1026 case MUSB_HDRC_RXCOUNT:
1027 return s->ep[ep].rxcount;
1028
1029 default:
1030 TRACE("unknown register 0x%02x", addr);
1031 return 0x00;
1032 };
1033 }
1034
1035 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1036 {
1037 MUSBState *s = (MUSBState *) opaque;
1038
1039 switch (addr) {
1040 case MUSB_HDRC_TXTYPE:
1041 s->ep[ep].type[0] = value;
1042 break;
1043 case MUSB_HDRC_TXINTERVAL:
1044 s->ep[ep].interval[0] = value;
1045 musb_ep_frame_cancel(&s->ep[ep], 0);
1046 break;
1047 case MUSB_HDRC_RXTYPE:
1048 s->ep[ep].type[1] = value;
1049 break;
1050 case MUSB_HDRC_RXINTERVAL:
1051 s->ep[ep].interval[1] = value;
1052 musb_ep_frame_cancel(&s->ep[ep], 1);
1053 break;
1054 case (MUSB_HDRC_FIFOSIZE & ~1):
1055 break;
1056 case MUSB_HDRC_FIFOSIZE:
1057 TRACE("somebody messes with fifosize (now %i bytes)", value);
1058 s->ep[ep].fifosize = value;
1059 break;
1060 default:
1061 TRACE("unknown register 0x%02x", addr);
1062 break;
1063 };
1064 }
1065
1066 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1067 {
1068 MUSBState *s = (MUSBState *) opaque;
1069 uint16_t ret;
1070
1071 switch (addr) {
1072 case MUSB_HDRC_TXMAXP:
1073 return s->ep[ep].maxp[0];
1074 case MUSB_HDRC_TXCSR:
1075 return s->ep[ep].csr[0];
1076 case MUSB_HDRC_RXMAXP:
1077 return s->ep[ep].maxp[1];
1078 case MUSB_HDRC_RXCSR:
1079 ret = s->ep[ep].csr[1];
1080
1081 /* TODO: This and other bits probably depend on
1082 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1083 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1084 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1085
1086 return ret;
1087 case MUSB_HDRC_RXCOUNT:
1088 return s->ep[ep].rxcount;
1089
1090 default:
1091 return musb_ep_readb(s, ep, addr) |
1092 (musb_ep_readb(s, ep, addr | 1) << 8);
1093 };
1094 }
1095
1096 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1097 {
1098 MUSBState *s = (MUSBState *) opaque;
1099
1100 switch (addr) {
1101 case MUSB_HDRC_TXMAXP:
1102 s->ep[ep].maxp[0] = value;
1103 break;
1104 case MUSB_HDRC_TXCSR:
1105 if (ep) {
1106 s->ep[ep].csr[0] &= value & 0xa6;
1107 s->ep[ep].csr[0] |= value & 0xff59;
1108 } else {
1109 s->ep[ep].csr[0] &= value & 0x85;
1110 s->ep[ep].csr[0] |= value & 0xf7a;
1111 }
1112
1113 musb_ep_frame_cancel(&s->ep[ep], 0);
1114
1115 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1116 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1117 s->ep[ep].fifolen[0] = 0;
1118 s->ep[ep].fifostart[0] = 0;
1119 if (ep)
1120 s->ep[ep].csr[0] &=
1121 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1122 else
1123 s->ep[ep].csr[0] &=
1124 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1125 }
1126 if (
1127 (ep &&
1128 #ifdef CLEAR_NAK
1129 (value & MGC_M_TXCSR_TXPKTRDY) &&
1130 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1131 #else
1132 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1133 #endif
1134 (!ep &&
1135 #ifdef CLEAR_NAK
1136 (value & MGC_M_CSR0_TXPKTRDY) &&
1137 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1138 #else
1139 (value & MGC_M_CSR0_TXPKTRDY)))
1140 #endif
1141 musb_tx_rdy(s, ep);
1142 if (!ep &&
1143 (value & MGC_M_CSR0_H_REQPKT) &&
1144 #ifdef CLEAR_NAK
1145 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1146 MGC_M_CSR0_RXPKTRDY)))
1147 #else
1148 !(value & MGC_M_CSR0_RXPKTRDY))
1149 #endif
1150 musb_rx_req(s, ep);
1151 break;
1152
1153 case MUSB_HDRC_RXMAXP:
1154 s->ep[ep].maxp[1] = value;
1155 break;
1156 case MUSB_HDRC_RXCSR:
1157 /* (DMA mode only) */
1158 if (
1159 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1160 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1161 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1162 value |= MGC_M_RXCSR_H_REQPKT;
1163
1164 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1165 s->ep[ep].csr[1] |= value & 0xfeb0;
1166
1167 musb_ep_frame_cancel(&s->ep[ep], 1);
1168
1169 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1170 s->ep[ep].fifolen[1] = 0;
1171 s->ep[ep].fifostart[1] = 0;
1172 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1173 /* If double buffering and we have two packets ready, flush
1174 * only the first one and set up the fifo at the second packet. */
1175 }
1176 #ifdef CLEAR_NAK
1177 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1178 #else
1179 if (value & MGC_M_RXCSR_H_REQPKT)
1180 #endif
1181 musb_rx_req(s, ep);
1182 break;
1183 case MUSB_HDRC_RXCOUNT:
1184 s->ep[ep].rxcount = value;
1185 break;
1186
1187 default:
1188 musb_ep_writeb(s, ep, addr, value & 0xff);
1189 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1190 };
1191 }
1192
1193 /* Generic control */
1194 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1195 {
1196 MUSBState *s = (MUSBState *) opaque;
1197 int ep, i;
1198 uint8_t ret;
1199
1200 switch (addr) {
1201 case MUSB_HDRC_FADDR:
1202 return s->faddr;
1203 case MUSB_HDRC_POWER:
1204 return s->power;
1205 case MUSB_HDRC_INTRUSB:
1206 ret = s->intr;
1207 for (i = 0; i < sizeof(ret) * 8; i ++)
1208 if (ret & (1 << i))
1209 musb_intr_set(s, i, 0);
1210 return ret;
1211 case MUSB_HDRC_INTRUSBE:
1212 return s->mask;
1213 case MUSB_HDRC_INDEX:
1214 return s->idx;
1215 case MUSB_HDRC_TESTMODE:
1216 return 0x00;
1217
1218 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1219 return musb_ep_readb(s, s->idx, addr & 0xf);
1220
1221 case MUSB_HDRC_DEVCTL:
1222 return s->devctl;
1223
1224 case MUSB_HDRC_TXFIFOSZ:
1225 case MUSB_HDRC_RXFIFOSZ:
1226 case MUSB_HDRC_VCTRL:
1227 /* TODO */
1228 return 0x00;
1229
1230 case MUSB_HDRC_HWVERS:
1231 return (1 << 10) | 400;
1232
1233 case (MUSB_HDRC_VCTRL | 1):
1234 case (MUSB_HDRC_HWVERS | 1):
1235 case (MUSB_HDRC_DEVCTL | 1):
1236 return 0x00;
1237
1238 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1239 ep = (addr >> 3) & 0xf;
1240 return musb_busctl_readb(s, ep, addr & 0x7);
1241
1242 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1243 ep = (addr >> 4) & 0xf;
1244 return musb_ep_readb(s, ep, addr & 0xf);
1245
1246 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1247 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1248 return musb_read_fifo(s->ep + ep);
1249
1250 default:
1251 TRACE("unknown register 0x%02x", (int) addr);
1252 return 0x00;
1253 };
1254 }
1255
1256 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1257 {
1258 MUSBState *s = (MUSBState *) opaque;
1259 int ep;
1260
1261 switch (addr) {
1262 case MUSB_HDRC_FADDR:
1263 s->faddr = value & 0x7f;
1264 break;
1265 case MUSB_HDRC_POWER:
1266 s->power = (value & 0xef) | (s->power & 0x10);
1267 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1268 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1269 usb_send_msg(s->port.dev, USB_MSG_RESET);
1270 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1271 if ((value & MGC_M_POWER_HSENAB) &&
1272 s->port.dev->speed == USB_SPEED_HIGH)
1273 s->power |= MGC_M_POWER_HSMODE; /* Success */
1274 /* Restart frame counting. */
1275 }
1276 if (value & MGC_M_POWER_SUSPENDM) {
1277 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1278 * is set, also go into low power mode. Frame counting stops. */
1279 /* XXX: Cleared when the interrupt register is read */
1280 }
1281 if (value & MGC_M_POWER_RESUME) {
1282 /* Wait 20ms and signal resuming on the bus. Frame counting
1283 * restarts. */
1284 }
1285 break;
1286 case MUSB_HDRC_INTRUSB:
1287 break;
1288 case MUSB_HDRC_INTRUSBE:
1289 s->mask = value & 0xff;
1290 break;
1291 case MUSB_HDRC_INDEX:
1292 s->idx = value & 0xf;
1293 break;
1294 case MUSB_HDRC_TESTMODE:
1295 break;
1296
1297 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1298 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1299 break;
1300
1301 case MUSB_HDRC_DEVCTL:
1302 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1303 musb_session_update(s,
1304 !!s->port.dev,
1305 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1306
1307 /* It seems this is the only R/W bit in this register? */
1308 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1309 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1310 break;
1311
1312 case MUSB_HDRC_TXFIFOSZ:
1313 case MUSB_HDRC_RXFIFOSZ:
1314 case MUSB_HDRC_VCTRL:
1315 /* TODO */
1316 break;
1317
1318 case (MUSB_HDRC_VCTRL | 1):
1319 case (MUSB_HDRC_DEVCTL | 1):
1320 break;
1321
1322 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1323 ep = (addr >> 3) & 0xf;
1324 musb_busctl_writeb(s, ep, addr & 0x7, value);
1325 break;
1326
1327 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1328 ep = (addr >> 4) & 0xf;
1329 musb_ep_writeb(s, ep, addr & 0xf, value);
1330 break;
1331
1332 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1333 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1334 musb_write_fifo(s->ep + ep, value & 0xff);
1335 break;
1336
1337 default:
1338 TRACE("unknown register 0x%02x", (int) addr);
1339 break;
1340 };
1341 }
1342
1343 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1344 {
1345 MUSBState *s = (MUSBState *) opaque;
1346 int ep, i;
1347 uint16_t ret;
1348
1349 switch (addr) {
1350 case MUSB_HDRC_INTRTX:
1351 ret = s->tx_intr;
1352 /* Auto clear */
1353 for (i = 0; i < sizeof(ret) * 8; i ++)
1354 if (ret & (1 << i))
1355 musb_tx_intr_set(s, i, 0);
1356 return ret;
1357 case MUSB_HDRC_INTRRX:
1358 ret = s->rx_intr;
1359 /* Auto clear */
1360 for (i = 0; i < sizeof(ret) * 8; i ++)
1361 if (ret & (1 << i))
1362 musb_rx_intr_set(s, i, 0);
1363 return ret;
1364 case MUSB_HDRC_INTRTXE:
1365 return s->tx_mask;
1366 case MUSB_HDRC_INTRRXE:
1367 return s->rx_mask;
1368
1369 case MUSB_HDRC_FRAME:
1370 /* TODO */
1371 return 0x0000;
1372 case MUSB_HDRC_TXFIFOADDR:
1373 return s->ep[s->idx].fifoaddr[0];
1374 case MUSB_HDRC_RXFIFOADDR:
1375 return s->ep[s->idx].fifoaddr[1];
1376
1377 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1378 return musb_ep_readh(s, s->idx, addr & 0xf);
1379
1380 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1381 ep = (addr >> 3) & 0xf;
1382 return musb_busctl_readh(s, ep, addr & 0x7);
1383
1384 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1385 ep = (addr >> 4) & 0xf;
1386 return musb_ep_readh(s, ep, addr & 0xf);
1387
1388 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1389 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1390 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1391
1392 default:
1393 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1394 };
1395 }
1396
1397 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1398 {
1399 MUSBState *s = (MUSBState *) opaque;
1400 int ep;
1401
1402 switch (addr) {
1403 case MUSB_HDRC_INTRTXE:
1404 s->tx_mask = value;
1405 /* XXX: the masks seem to apply on the raising edge like with
1406 * edge-triggered interrupts, thus no need to update. I may be
1407 * wrong though. */
1408 break;
1409 case MUSB_HDRC_INTRRXE:
1410 s->rx_mask = value;
1411 break;
1412
1413 case MUSB_HDRC_FRAME:
1414 /* TODO */
1415 break;
1416 case MUSB_HDRC_TXFIFOADDR:
1417 s->ep[s->idx].fifoaddr[0] = value;
1418 s->ep[s->idx].buf[0] =
1419 s->buf + ((value << 3) & 0x7ff );
1420 break;
1421 case MUSB_HDRC_RXFIFOADDR:
1422 s->ep[s->idx].fifoaddr[1] = value;
1423 s->ep[s->idx].buf[1] =
1424 s->buf + ((value << 3) & 0x7ff);
1425 break;
1426
1427 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1428 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1429 break;
1430
1431 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1432 ep = (addr >> 3) & 0xf;
1433 musb_busctl_writeh(s, ep, addr & 0x7, value);
1434 break;
1435
1436 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1437 ep = (addr >> 4) & 0xf;
1438 musb_ep_writeh(s, ep, addr & 0xf, value);
1439 break;
1440
1441 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1442 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1443 musb_write_fifo(s->ep + ep, value & 0xff);
1444 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1445 break;
1446
1447 default:
1448 musb_writeb(s, addr, value & 0xff);
1449 musb_writeb(s, addr | 1, value >> 8);
1450 };
1451 }
1452
1453 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1454 {
1455 MUSBState *s = (MUSBState *) opaque;
1456 int ep;
1457
1458 switch (addr) {
1459 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1460 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1461 return ( musb_read_fifo(s->ep + ep) |
1462 musb_read_fifo(s->ep + ep) << 8 |
1463 musb_read_fifo(s->ep + ep) << 16 |
1464 musb_read_fifo(s->ep + ep) << 24 );
1465 default:
1466 TRACE("unknown register 0x%02x", (int) addr);
1467 return 0x00000000;
1468 };
1469 }
1470
1471 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1472 {
1473 MUSBState *s = (MUSBState *) opaque;
1474 int ep;
1475
1476 switch (addr) {
1477 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1478 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1479 musb_write_fifo(s->ep + ep, value & 0xff);
1480 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1481 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1482 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
1483 break;
1484 default:
1485 TRACE("unknown register 0x%02x", (int) addr);
1486 break;
1487 };
1488 }
1489
1490 CPUReadMemoryFunc * const musb_read[] = {
1491 musb_readb,
1492 musb_readh,
1493 musb_readw,
1494 };
1495
1496 CPUWriteMemoryFunc * const musb_write[] = {
1497 musb_writeb,
1498 musb_writeh,
1499 musb_writew,
1500 };
QEmu