?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Fix typos in comments (accessable -> accessible, priveleged -> privileged)
[qemu.git] / hw / ppc405_uc.c
blob2ce79ee053d72c9aec2ece5c3a2841f2cc21cc34
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++) {
72 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
73 }
74 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
75 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
76 for (i = 0; i < 6; i++)
77 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
78 n = 0x6A;
79 if (flags & 0x00000001) {
80 for (i = 0; i < 6; i++)
81 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
82 }
83 stl_phys(bdloc + n, bd->bi_opbfreq);
84 n += 4;
85 for (i = 0; i < 2; i++) {
86 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
87 n += 4;
88 }
89
90 return bdloc;
91 }
92
93 /*****************************************************************************/
94 /* Shared peripherals */
95
96 /*****************************************************************************/
97 /* Peripheral local bus arbitrer */
98 enum {
99 PLB0_BESR = 0x084,
100 PLB0_BEAR = 0x086,
101 PLB0_ACR = 0x087,
102 };
103
104 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
105 struct ppc4xx_plb_t {
106 uint32_t acr;
107 uint32_t bear;
108 uint32_t besr;
109 };
110
111 static uint32_t dcr_read_plb (void *opaque, int dcrn)
112 {
113 ppc4xx_plb_t *plb;
114 uint32_t ret;
115
116 plb = opaque;
117 switch (dcrn) {
118 case PLB0_ACR:
119 ret = plb->acr;
120 break;
121 case PLB0_BEAR:
122 ret = plb->bear;
123 break;
124 case PLB0_BESR:
125 ret = plb->besr;
126 break;
127 default:
128 /* Avoid gcc warning */
129 ret = 0;
130 break;
131 }
132
133 return ret;
134 }
135
136 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
137 {
138 ppc4xx_plb_t *plb;
139
140 plb = opaque;
141 switch (dcrn) {
142 case PLB0_ACR:
143 /* We don't care about the actual parameters written as
144 * we don't manage any priorities on the bus
145 */
146 plb->acr = val & 0xF8000000;
147 break;
148 case PLB0_BEAR:
149 /* Read only */
150 break;
151 case PLB0_BESR:
152 /* Write-clear */
153 plb->besr &= ~val;
154 break;
155 }
156 }
157
158 static void ppc4xx_plb_reset (void *opaque)
159 {
160 ppc4xx_plb_t *plb;
161
162 plb = opaque;
163 plb->acr = 0x00000000;
164 plb->bear = 0x00000000;
165 plb->besr = 0x00000000;
166 }
167
168 static void ppc4xx_plb_init(CPUState *env)
169 {
170 ppc4xx_plb_t *plb;
171
172 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
173 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
175 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
176 qemu_register_reset(ppc4xx_plb_reset, plb);
177 }
178
179 /*****************************************************************************/
180 /* PLB to OPB bridge */
181 enum {
182 POB0_BESR0 = 0x0A0,
183 POB0_BESR1 = 0x0A2,
184 POB0_BEAR = 0x0A4,
185 };
186
187 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
188 struct ppc4xx_pob_t {
189 uint32_t bear;
190 uint32_t besr[2];
191 };
192
193 static uint32_t dcr_read_pob (void *opaque, int dcrn)
194 {
195 ppc4xx_pob_t *pob;
196 uint32_t ret;
197
198 pob = opaque;
199 switch (dcrn) {
200 case POB0_BEAR:
201 ret = pob->bear;
202 break;
203 case POB0_BESR0:
204 case POB0_BESR1:
205 ret = pob->besr[dcrn - POB0_BESR0];
206 break;
207 default:
208 /* Avoid gcc warning */
209 ret = 0;
210 break;
211 }
212
213 return ret;
214 }
215
216 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
217 {
218 ppc4xx_pob_t *pob;
219
220 pob = opaque;
221 switch (dcrn) {
222 case POB0_BEAR:
223 /* Read only */
224 break;
225 case POB0_BESR0:
226 case POB0_BESR1:
227 /* Write-clear */
228 pob->besr[dcrn - POB0_BESR0] &= ~val;
229 break;
230 }
231 }
232
233 static void ppc4xx_pob_reset (void *opaque)
234 {
235 ppc4xx_pob_t *pob;
236
237 pob = opaque;
238 /* No error */
239 pob->bear = 0x00000000;
240 pob->besr[0] = 0x0000000;
241 pob->besr[1] = 0x0000000;
242 }
243
244 static void ppc4xx_pob_init(CPUState *env)
245 {
246 ppc4xx_pob_t *pob;
247
248 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
249 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
251 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
252 qemu_register_reset(ppc4xx_pob_reset, pob);
253 }
254
255 /*****************************************************************************/
256 /* OPB arbitrer */
257 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
258 struct ppc4xx_opba_t {
259 uint8_t cr;
260 uint8_t pr;
261 };
262
263 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
264 {
265 ppc4xx_opba_t *opba;
266 uint32_t ret;
267
268 #ifdef DEBUG_OPBA
269 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
270 #endif
271 opba = opaque;
272 switch (addr) {
273 case 0x00:
274 ret = opba->cr;
275 break;
276 case 0x01:
277 ret = opba->pr;
278 break;
279 default:
280 ret = 0x00;
281 break;
282 }
283
284 return ret;
285 }
286
287 static void opba_writeb (void *opaque,
288 target_phys_addr_t addr, uint32_t value)
289 {
290 ppc4xx_opba_t *opba;
291
292 #ifdef DEBUG_OPBA
293 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
294 value);
295 #endif
296 opba = opaque;
297 switch (addr) {
298 case 0x00:
299 opba->cr = value & 0xF8;
300 break;
301 case 0x01:
302 opba->pr = value & 0xFF;
303 break;
304 default:
305 break;
306 }
307 }
308
309 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
310 {
311 uint32_t ret;
312
313 #ifdef DEBUG_OPBA
314 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
315 #endif
316 ret = opba_readb(opaque, addr) << 8;
317 ret |= opba_readb(opaque, addr + 1);
318
319 return ret;
320 }
321
322 static void opba_writew (void *opaque,
323 target_phys_addr_t addr, uint32_t value)
324 {
325 #ifdef DEBUG_OPBA
326 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
327 value);
328 #endif
329 opba_writeb(opaque, addr, value >> 8);
330 opba_writeb(opaque, addr + 1, value);
331 }
332
333 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
334 {
335 uint32_t ret;
336
337 #ifdef DEBUG_OPBA
338 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
339 #endif
340 ret = opba_readb(opaque, addr) << 24;
341 ret |= opba_readb(opaque, addr + 1) << 16;
342
343 return ret;
344 }
345
346 static void opba_writel (void *opaque,
347 target_phys_addr_t addr, uint32_t value)
348 {
349 #ifdef DEBUG_OPBA
350 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
351 value);
352 #endif
353 opba_writeb(opaque, addr, value >> 24);
354 opba_writeb(opaque, addr + 1, value >> 16);
355 }
356
357 static CPUReadMemoryFunc * const opba_read[] = {
358 &opba_readb,
359 &opba_readw,
360 &opba_readl,
361 };
362
363 static CPUWriteMemoryFunc * const opba_write[] = {
364 &opba_writeb,
365 &opba_writew,
366 &opba_writel,
367 };
368
369 static void ppc4xx_opba_reset (void *opaque)
370 {
371 ppc4xx_opba_t *opba;
372
373 opba = opaque;
374 opba->cr = 0x00; /* No dynamic priorities - park disabled */
375 opba->pr = 0x11;
376 }
377
378 static void ppc4xx_opba_init(target_phys_addr_t base)
379 {
380 ppc4xx_opba_t *opba;
381 int io;
382
383 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
384 #ifdef DEBUG_OPBA
385 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
386 #endif
387 io = cpu_register_io_memory(opba_read, opba_write, opba,
388 DEVICE_NATIVE_ENDIAN);
389 cpu_register_physical_memory(base, 0x002, io);
390 qemu_register_reset(ppc4xx_opba_reset, opba);
391 }
392
393 /*****************************************************************************/
394 /* Code decompression controller */
395 /* XXX: TODO */
396
397 /*****************************************************************************/
398 /* Peripheral controller */
399 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
400 struct ppc4xx_ebc_t {
401 uint32_t addr;
402 uint32_t bcr[8];
403 uint32_t bap[8];
404 uint32_t bear;
405 uint32_t besr0;
406 uint32_t besr1;
407 uint32_t cfg;
408 };
409
410 enum {
411 EBC0_CFGADDR = 0x012,
412 EBC0_CFGDATA = 0x013,
413 };
414
415 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
416 {
417 ppc4xx_ebc_t *ebc;
418 uint32_t ret;
419
420 ebc = opaque;
421 switch (dcrn) {
422 case EBC0_CFGADDR:
423 ret = ebc->addr;
424 break;
425 case EBC0_CFGDATA:
426 switch (ebc->addr) {
427 case 0x00: /* B0CR */
428 ret = ebc->bcr[0];
429 break;
430 case 0x01: /* B1CR */
431 ret = ebc->bcr[1];
432 break;
433 case 0x02: /* B2CR */
434 ret = ebc->bcr[2];
435 break;
436 case 0x03: /* B3CR */
437 ret = ebc->bcr[3];
438 break;
439 case 0x04: /* B4CR */
440 ret = ebc->bcr[4];
441 break;
442 case 0x05: /* B5CR */
443 ret = ebc->bcr[5];
444 break;
445 case 0x06: /* B6CR */
446 ret = ebc->bcr[6];
447 break;
448 case 0x07: /* B7CR */
449 ret = ebc->bcr[7];
450 break;
451 case 0x10: /* B0AP */
452 ret = ebc->bap[0];
453 break;
454 case 0x11: /* B1AP */
455 ret = ebc->bap[1];
456 break;
457 case 0x12: /* B2AP */
458 ret = ebc->bap[2];
459 break;
460 case 0x13: /* B3AP */
461 ret = ebc->bap[3];
462 break;
463 case 0x14: /* B4AP */
464 ret = ebc->bap[4];
465 break;
466 case 0x15: /* B5AP */
467 ret = ebc->bap[5];
468 break;
469 case 0x16: /* B6AP */
470 ret = ebc->bap[6];
471 break;
472 case 0x17: /* B7AP */
473 ret = ebc->bap[7];
474 break;
475 case 0x20: /* BEAR */
476 ret = ebc->bear;
477 break;
478 case 0x21: /* BESR0 */
479 ret = ebc->besr0;
480 break;
481 case 0x22: /* BESR1 */
482 ret = ebc->besr1;
483 break;
484 case 0x23: /* CFG */
485 ret = ebc->cfg;
486 break;
487 default:
488 ret = 0x00000000;
489 break;
490 }
491 break;
492 default:
493 ret = 0x00000000;
494 break;
495 }
496
497 return ret;
498 }
499
500 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
501 {
502 ppc4xx_ebc_t *ebc;
503
504 ebc = opaque;
505 switch (dcrn) {
506 case EBC0_CFGADDR:
507 ebc->addr = val;
508 break;
509 case EBC0_CFGDATA:
510 switch (ebc->addr) {
511 case 0x00: /* B0CR */
512 break;
513 case 0x01: /* B1CR */
514 break;
515 case 0x02: /* B2CR */
516 break;
517 case 0x03: /* B3CR */
518 break;
519 case 0x04: /* B4CR */
520 break;
521 case 0x05: /* B5CR */
522 break;
523 case 0x06: /* B6CR */
524 break;
525 case 0x07: /* B7CR */
526 break;
527 case 0x10: /* B0AP */
528 break;
529 case 0x11: /* B1AP */
530 break;
531 case 0x12: /* B2AP */
532 break;
533 case 0x13: /* B3AP */
534 break;
535 case 0x14: /* B4AP */
536 break;
537 case 0x15: /* B5AP */
538 break;
539 case 0x16: /* B6AP */
540 break;
541 case 0x17: /* B7AP */
542 break;
543 case 0x20: /* BEAR */
544 break;
545 case 0x21: /* BESR0 */
546 break;
547 case 0x22: /* BESR1 */
548 break;
549 case 0x23: /* CFG */
550 break;
551 default:
552 break;
553 }
554 break;
555 default:
556 break;
557 }
558 }
559
560 static void ebc_reset (void *opaque)
561 {
562 ppc4xx_ebc_t *ebc;
563 int i;
564
565 ebc = opaque;
566 ebc->addr = 0x00000000;
567 ebc->bap[0] = 0x7F8FFE80;
568 ebc->bcr[0] = 0xFFE28000;
569 for (i = 0; i < 8; i++) {
570 ebc->bap[i] = 0x00000000;
571 ebc->bcr[i] = 0x00000000;
572 }
573 ebc->besr0 = 0x00000000;
574 ebc->besr1 = 0x00000000;
575 ebc->cfg = 0x80400000;
576 }
577
578 static void ppc405_ebc_init(CPUState *env)
579 {
580 ppc4xx_ebc_t *ebc;
581
582 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
583 qemu_register_reset(&ebc_reset, ebc);
584 ppc_dcr_register(env, EBC0_CFGADDR,
585 ebc, &dcr_read_ebc, &dcr_write_ebc);
586 ppc_dcr_register(env, EBC0_CFGDATA,
587 ebc, &dcr_read_ebc, &dcr_write_ebc);
588 }
589
590 /*****************************************************************************/
591 /* DMA controller */
592 enum {
593 DMA0_CR0 = 0x100,
594 DMA0_CT0 = 0x101,
595 DMA0_DA0 = 0x102,
596 DMA0_SA0 = 0x103,
597 DMA0_SG0 = 0x104,
598 DMA0_CR1 = 0x108,
599 DMA0_CT1 = 0x109,
600 DMA0_DA1 = 0x10A,
601 DMA0_SA1 = 0x10B,
602 DMA0_SG1 = 0x10C,
603 DMA0_CR2 = 0x110,
604 DMA0_CT2 = 0x111,
605 DMA0_DA2 = 0x112,
606 DMA0_SA2 = 0x113,
607 DMA0_SG2 = 0x114,
608 DMA0_CR3 = 0x118,
609 DMA0_CT3 = 0x119,
610 DMA0_DA3 = 0x11A,
611 DMA0_SA3 = 0x11B,
612 DMA0_SG3 = 0x11C,
613 DMA0_SR = 0x120,
614 DMA0_SGC = 0x123,
615 DMA0_SLP = 0x125,
616 DMA0_POL = 0x126,
617 };
618
619 typedef struct ppc405_dma_t ppc405_dma_t;
620 struct ppc405_dma_t {
621 qemu_irq irqs[4];
622 uint32_t cr[4];
623 uint32_t ct[4];
624 uint32_t da[4];
625 uint32_t sa[4];
626 uint32_t sg[4];
627 uint32_t sr;
628 uint32_t sgc;
629 uint32_t slp;
630 uint32_t pol;
631 };
632
633 static uint32_t dcr_read_dma (void *opaque, int dcrn)
634 {
635 return 0;
636 }
637
638 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
639 {
640 }
641
642 static void ppc405_dma_reset (void *opaque)
643 {
644 ppc405_dma_t *dma;
645 int i;
646
647 dma = opaque;
648 for (i = 0; i < 4; i++) {
649 dma->cr[i] = 0x00000000;
650 dma->ct[i] = 0x00000000;
651 dma->da[i] = 0x00000000;
652 dma->sa[i] = 0x00000000;
653 dma->sg[i] = 0x00000000;
654 }
655 dma->sr = 0x00000000;
656 dma->sgc = 0x00000000;
657 dma->slp = 0x7C000000;
658 dma->pol = 0x00000000;
659 }
660
661 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
662 {
663 ppc405_dma_t *dma;
664
665 dma = qemu_mallocz(sizeof(ppc405_dma_t));
666 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
667 qemu_register_reset(&ppc405_dma_reset, dma);
668 ppc_dcr_register(env, DMA0_CR0,
669 dma, &dcr_read_dma, &dcr_write_dma);
670 ppc_dcr_register(env, DMA0_CT0,
671 dma, &dcr_read_dma, &dcr_write_dma);
672 ppc_dcr_register(env, DMA0_DA0,
673 dma, &dcr_read_dma, &dcr_write_dma);
674 ppc_dcr_register(env, DMA0_SA0,
675 dma, &dcr_read_dma, &dcr_write_dma);
676 ppc_dcr_register(env, DMA0_SG0,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_CR1,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_CT1,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_DA1,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_SA1,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_SG1,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_CR2,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_CT2,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_DA2,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_SA2,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_SG2,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_CR3,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_CT3,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_DA3,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SA3,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_SG3,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_SR,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_SGC,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_SLP,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_POL,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 }
717
718 /*****************************************************************************/
719 /* GPIO */
720 typedef struct ppc405_gpio_t ppc405_gpio_t;
721 struct ppc405_gpio_t {
722 uint32_t or;
723 uint32_t tcr;
724 uint32_t osrh;
725 uint32_t osrl;
726 uint32_t tsrh;
727 uint32_t tsrl;
728 uint32_t odr;
729 uint32_t ir;
730 uint32_t rr1;
731 uint32_t isr1h;
732 uint32_t isr1l;
733 };
734
735 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
736 {
737 #ifdef DEBUG_GPIO
738 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
739 #endif
740
741 return 0;
742 }
743
744 static void ppc405_gpio_writeb (void *opaque,
745 target_phys_addr_t addr, uint32_t value)
746 {
747 #ifdef DEBUG_GPIO
748 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
749 value);
750 #endif
751 }
752
753 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
754 {
755 #ifdef DEBUG_GPIO
756 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
757 #endif
758
759 return 0;
760 }
761
762 static void ppc405_gpio_writew (void *opaque,
763 target_phys_addr_t addr, uint32_t value)
764 {
765 #ifdef DEBUG_GPIO
766 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
767 value);
768 #endif
769 }
770
771 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
772 {
773 #ifdef DEBUG_GPIO
774 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
775 #endif
776
777 return 0;
778 }
779
780 static void ppc405_gpio_writel (void *opaque,
781 target_phys_addr_t addr, uint32_t value)
782 {
783 #ifdef DEBUG_GPIO
784 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
785 value);
786 #endif
787 }
788
789 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
790 &ppc405_gpio_readb,
791 &ppc405_gpio_readw,
792 &ppc405_gpio_readl,
793 };
794
795 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
796 &ppc405_gpio_writeb,
797 &ppc405_gpio_writew,
798 &ppc405_gpio_writel,
799 };
800
801 static void ppc405_gpio_reset (void *opaque)
802 {
803 }
804
805 static void ppc405_gpio_init(target_phys_addr_t base)
806 {
807 ppc405_gpio_t *gpio;
808 int io;
809
810 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
811 #ifdef DEBUG_GPIO
812 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
813 #endif
814 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
815 DEVICE_NATIVE_ENDIAN);
816 cpu_register_physical_memory(base, 0x038, io);
817 qemu_register_reset(&ppc405_gpio_reset, gpio);
818 }
819
820 /*****************************************************************************/
821 /* On Chip Memory */
822 enum {
823 OCM0_ISARC = 0x018,
824 OCM0_ISACNTL = 0x019,
825 OCM0_DSARC = 0x01A,
826 OCM0_DSACNTL = 0x01B,
827 };
828
829 typedef struct ppc405_ocm_t ppc405_ocm_t;
830 struct ppc405_ocm_t {
831 target_ulong offset;
832 uint32_t isarc;
833 uint32_t isacntl;
834 uint32_t dsarc;
835 uint32_t dsacntl;
836 };
837
838 static void ocm_update_mappings (ppc405_ocm_t *ocm,
839 uint32_t isarc, uint32_t isacntl,
840 uint32_t dsarc, uint32_t dsacntl)
841 {
842 #ifdef DEBUG_OCM
843 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
844 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
845 " (%08" PRIx32 " %08" PRIx32 ")\n",
846 isarc, isacntl, dsarc, dsacntl,
847 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
848 #endif
849 if (ocm->isarc != isarc ||
850 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
851 if (ocm->isacntl & 0x80000000) {
852 /* Unmap previously assigned memory region */
853 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
854 cpu_register_physical_memory(ocm->isarc, 0x04000000,
855 IO_MEM_UNASSIGNED);
856 }
857 if (isacntl & 0x80000000) {
858 /* Map new instruction memory region */
859 #ifdef DEBUG_OCM
860 printf("OCM map ISA %08" PRIx32 "\n", isarc);
861 #endif
862 cpu_register_physical_memory(isarc, 0x04000000,
863 ocm->offset | IO_MEM_RAM);
864 }
865 }
866 if (ocm->dsarc != dsarc ||
867 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
868 if (ocm->dsacntl & 0x80000000) {
869 /* Beware not to unmap the region we just mapped */
870 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
871 /* Unmap previously assigned memory region */
872 #ifdef DEBUG_OCM
873 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
874 #endif
875 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
876 IO_MEM_UNASSIGNED);
877 }
878 }
879 if (dsacntl & 0x80000000) {
880 /* Beware not to remap the region we just mapped */
881 if (!(isacntl & 0x80000000) || dsarc != isarc) {
882 /* Map new data memory region */
883 #ifdef DEBUG_OCM
884 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
885 #endif
886 cpu_register_physical_memory(dsarc, 0x04000000,
887 ocm->offset | IO_MEM_RAM);
888 }
889 }
890 }
891 }
892
893 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
894 {
895 ppc405_ocm_t *ocm;
896 uint32_t ret;
897
898 ocm = opaque;
899 switch (dcrn) {
900 case OCM0_ISARC:
901 ret = ocm->isarc;
902 break;
903 case OCM0_ISACNTL:
904 ret = ocm->isacntl;
905 break;
906 case OCM0_DSARC:
907 ret = ocm->dsarc;
908 break;
909 case OCM0_DSACNTL:
910 ret = ocm->dsacntl;
911 break;
912 default:
913 ret = 0;
914 break;
915 }
916
917 return ret;
918 }
919
920 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
921 {
922 ppc405_ocm_t *ocm;
923 uint32_t isarc, dsarc, isacntl, dsacntl;
924
925 ocm = opaque;
926 isarc = ocm->isarc;
927 dsarc = ocm->dsarc;
928 isacntl = ocm->isacntl;
929 dsacntl = ocm->dsacntl;
930 switch (dcrn) {
931 case OCM0_ISARC:
932 isarc = val & 0xFC000000;
933 break;
934 case OCM0_ISACNTL:
935 isacntl = val & 0xC0000000;
936 break;
937 case OCM0_DSARC:
938 isarc = val & 0xFC000000;
939 break;
940 case OCM0_DSACNTL:
941 isacntl = val & 0xC0000000;
942 break;
943 }
944 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
945 ocm->isarc = isarc;
946 ocm->dsarc = dsarc;
947 ocm->isacntl = isacntl;
948 ocm->dsacntl = dsacntl;
949 }
950
951 static void ocm_reset (void *opaque)
952 {
953 ppc405_ocm_t *ocm;
954 uint32_t isarc, dsarc, isacntl, dsacntl;
955
956 ocm = opaque;
957 isarc = 0x00000000;
958 isacntl = 0x00000000;
959 dsarc = 0x00000000;
960 dsacntl = 0x00000000;
961 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
962 ocm->isarc = isarc;
963 ocm->dsarc = dsarc;
964 ocm->isacntl = isacntl;
965 ocm->dsacntl = dsacntl;
966 }
967
968 static void ppc405_ocm_init(CPUState *env)
969 {
970 ppc405_ocm_t *ocm;
971
972 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
973 ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
974 qemu_register_reset(&ocm_reset, ocm);
975 ppc_dcr_register(env, OCM0_ISARC,
976 ocm, &dcr_read_ocm, &dcr_write_ocm);
977 ppc_dcr_register(env, OCM0_ISACNTL,
978 ocm, &dcr_read_ocm, &dcr_write_ocm);
979 ppc_dcr_register(env, OCM0_DSARC,
980 ocm, &dcr_read_ocm, &dcr_write_ocm);
981 ppc_dcr_register(env, OCM0_DSACNTL,
982 ocm, &dcr_read_ocm, &dcr_write_ocm);
983 }
984
985 /*****************************************************************************/
986 /* I2C controller */
987 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
988 struct ppc4xx_i2c_t {
989 qemu_irq irq;
990 uint8_t mdata;
991 uint8_t lmadr;
992 uint8_t hmadr;
993 uint8_t cntl;
994 uint8_t mdcntl;
995 uint8_t sts;
996 uint8_t extsts;
997 uint8_t sdata;
998 uint8_t lsadr;
999 uint8_t hsadr;
1000 uint8_t clkdiv;
1001 uint8_t intrmsk;
1002 uint8_t xfrcnt;
1003 uint8_t xtcntlss;
1004 uint8_t directcntl;
1005 };
1006
1007 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1008 {
1009 ppc4xx_i2c_t *i2c;
1010 uint32_t ret;
1011
1012 #ifdef DEBUG_I2C
1013 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1014 #endif
1015 i2c = opaque;
1016 switch (addr) {
1017 case 0x00:
1018 // i2c_readbyte(&i2c->mdata);
1019 ret = i2c->mdata;
1020 break;
1021 case 0x02:
1022 ret = i2c->sdata;
1023 break;
1024 case 0x04:
1025 ret = i2c->lmadr;
1026 break;
1027 case 0x05:
1028 ret = i2c->hmadr;
1029 break;
1030 case 0x06:
1031 ret = i2c->cntl;
1032 break;
1033 case 0x07:
1034 ret = i2c->mdcntl;
1035 break;
1036 case 0x08:
1037 ret = i2c->sts;
1038 break;
1039 case 0x09:
1040 ret = i2c->extsts;
1041 break;
1042 case 0x0A:
1043 ret = i2c->lsadr;
1044 break;
1045 case 0x0B:
1046 ret = i2c->hsadr;
1047 break;
1048 case 0x0C:
1049 ret = i2c->clkdiv;
1050 break;
1051 case 0x0D:
1052 ret = i2c->intrmsk;
1053 break;
1054 case 0x0E:
1055 ret = i2c->xfrcnt;
1056 break;
1057 case 0x0F:
1058 ret = i2c->xtcntlss;
1059 break;
1060 case 0x10:
1061 ret = i2c->directcntl;
1062 break;
1063 default:
1064 ret = 0x00;
1065 break;
1066 }
1067 #ifdef DEBUG_I2C
1068 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1069 #endif
1070
1071 return ret;
1072 }
1073
1074 static void ppc4xx_i2c_writeb (void *opaque,
1075 target_phys_addr_t addr, uint32_t value)
1076 {
1077 ppc4xx_i2c_t *i2c;
1078
1079 #ifdef DEBUG_I2C
1080 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1081 value);
1082 #endif
1083 i2c = opaque;
1084 switch (addr) {
1085 case 0x00:
1086 i2c->mdata = value;
1087 // i2c_sendbyte(&i2c->mdata);
1088 break;
1089 case 0x02:
1090 i2c->sdata = value;
1091 break;
1092 case 0x04:
1093 i2c->lmadr = value;
1094 break;
1095 case 0x05:
1096 i2c->hmadr = value;
1097 break;
1098 case 0x06:
1099 i2c->cntl = value;
1100 break;
1101 case 0x07:
1102 i2c->mdcntl = value & 0xDF;
1103 break;
1104 case 0x08:
1105 i2c->sts &= ~(value & 0x0A);
1106 break;
1107 case 0x09:
1108 i2c->extsts &= ~(value & 0x8F);
1109 break;
1110 case 0x0A:
1111 i2c->lsadr = value;
1112 break;
1113 case 0x0B:
1114 i2c->hsadr = value;
1115 break;
1116 case 0x0C:
1117 i2c->clkdiv = value;
1118 break;
1119 case 0x0D:
1120 i2c->intrmsk = value;
1121 break;
1122 case 0x0E:
1123 i2c->xfrcnt = value & 0x77;
1124 break;
1125 case 0x0F:
1126 i2c->xtcntlss = value;
1127 break;
1128 case 0x10:
1129 i2c->directcntl = value & 0x7;
1130 break;
1131 }
1132 }
1133
1134 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1135 {
1136 uint32_t ret;
1137
1138 #ifdef DEBUG_I2C
1139 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1140 #endif
1141 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1142 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1143
1144 return ret;
1145 }
1146
1147 static void ppc4xx_i2c_writew (void *opaque,
1148 target_phys_addr_t addr, uint32_t value)
1149 {
1150 #ifdef DEBUG_I2C
1151 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1152 value);
1153 #endif
1154 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1155 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1156 }
1157
1158 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1159 {
1160 uint32_t ret;
1161
1162 #ifdef DEBUG_I2C
1163 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1164 #endif
1165 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1166 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1167 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1168 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1169
1170 return ret;
1171 }
1172
1173 static void ppc4xx_i2c_writel (void *opaque,
1174 target_phys_addr_t addr, uint32_t value)
1175 {
1176 #ifdef DEBUG_I2C
1177 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1178 value);
1179 #endif
1180 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1181 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1182 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1183 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1184 }
1185
1186 static CPUReadMemoryFunc * const i2c_read[] = {
1187 &ppc4xx_i2c_readb,
1188 &ppc4xx_i2c_readw,
1189 &ppc4xx_i2c_readl,
1190 };
1191
1192 static CPUWriteMemoryFunc * const i2c_write[] = {
1193 &ppc4xx_i2c_writeb,
1194 &ppc4xx_i2c_writew,
1195 &ppc4xx_i2c_writel,
1196 };
1197
1198 static void ppc4xx_i2c_reset (void *opaque)
1199 {
1200 ppc4xx_i2c_t *i2c;
1201
1202 i2c = opaque;
1203 i2c->mdata = 0x00;
1204 i2c->sdata = 0x00;
1205 i2c->cntl = 0x00;
1206 i2c->mdcntl = 0x00;
1207 i2c->sts = 0x00;
1208 i2c->extsts = 0x00;
1209 i2c->clkdiv = 0x00;
1210 i2c->xfrcnt = 0x00;
1211 i2c->directcntl = 0x0F;
1212 }
1213
1214 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1215 {
1216 ppc4xx_i2c_t *i2c;
1217 int io;
1218
1219 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1220 i2c->irq = irq;
1221 #ifdef DEBUG_I2C
1222 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1223 #endif
1224 io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
1225 DEVICE_NATIVE_ENDIAN);
1226 cpu_register_physical_memory(base, 0x011, io);
1227 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1228 }
1229
1230 /*****************************************************************************/
1231 /* General purpose timers */
1232 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1233 struct ppc4xx_gpt_t {
1234 int64_t tb_offset;
1235 uint32_t tb_freq;
1236 struct QEMUTimer *timer;
1237 qemu_irq irqs[5];
1238 uint32_t oe;
1239 uint32_t ol;
1240 uint32_t im;
1241 uint32_t is;
1242 uint32_t ie;
1243 uint32_t comp[5];
1244 uint32_t mask[5];
1245 };
1246
1247 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1248 {
1249 #ifdef DEBUG_GPT
1250 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1251 #endif
1252 /* XXX: generate a bus fault */
1253 return -1;
1254 }
1255
1256 static void ppc4xx_gpt_writeb (void *opaque,
1257 target_phys_addr_t addr, uint32_t value)
1258 {
1259 #ifdef DEBUG_I2C
1260 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1261 value);
1262 #endif
1263 /* XXX: generate a bus fault */
1264 }
1265
1266 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1267 {
1268 #ifdef DEBUG_GPT
1269 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1270 #endif
1271 /* XXX: generate a bus fault */
1272 return -1;
1273 }
1274
1275 static void ppc4xx_gpt_writew (void *opaque,
1276 target_phys_addr_t addr, uint32_t value)
1277 {
1278 #ifdef DEBUG_I2C
1279 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1280 value);
1281 #endif
1282 /* XXX: generate a bus fault */
1283 }
1284
1285 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1286 {
1287 /* XXX: TODO */
1288 return 0;
1289 }
1290
1291 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1292 {
1293 /* XXX: TODO */
1294 }
1295
1296 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1297 {
1298 uint32_t mask;
1299 int i;
1300
1301 mask = 0x80000000;
1302 for (i = 0; i < 5; i++) {
1303 if (gpt->oe & mask) {
1304 /* Output is enabled */
1305 if (ppc4xx_gpt_compare(gpt, i)) {
1306 /* Comparison is OK */
1307 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1308 } else {
1309 /* Comparison is KO */
1310 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1311 }
1312 }
1313 mask = mask >> 1;
1314 }
1315 }
1316
1317 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1318 {
1319 uint32_t mask;
1320 int i;
1321
1322 mask = 0x00008000;
1323 for (i = 0; i < 5; i++) {
1324 if (gpt->is & gpt->im & mask)
1325 qemu_irq_raise(gpt->irqs[i]);
1326 else
1327 qemu_irq_lower(gpt->irqs[i]);
1328 mask = mask >> 1;
1329 }
1330 }
1331
1332 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1333 {
1334 /* XXX: TODO */
1335 }
1336
1337 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1338 {
1339 ppc4xx_gpt_t *gpt;
1340 uint32_t ret;
1341 int idx;
1342
1343 #ifdef DEBUG_GPT
1344 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1345 #endif
1346 gpt = opaque;
1347 switch (addr) {
1348 case 0x00:
1349 /* Time base counter */
1350 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1351 gpt->tb_freq, get_ticks_per_sec());
1352 break;
1353 case 0x10:
1354 /* Output enable */
1355 ret = gpt->oe;
1356 break;
1357 case 0x14:
1358 /* Output level */
1359 ret = gpt->ol;
1360 break;
1361 case 0x18:
1362 /* Interrupt mask */
1363 ret = gpt->im;
1364 break;
1365 case 0x1C:
1366 case 0x20:
1367 /* Interrupt status */
1368 ret = gpt->is;
1369 break;
1370 case 0x24:
1371 /* Interrupt enable */
1372 ret = gpt->ie;
1373 break;
1374 case 0x80 ... 0x90:
1375 /* Compare timer */
1376 idx = (addr - 0x80) >> 2;
1377 ret = gpt->comp[idx];
1378 break;
1379 case 0xC0 ... 0xD0:
1380 /* Compare mask */
1381 idx = (addr - 0xC0) >> 2;
1382 ret = gpt->mask[idx];
1383 break;
1384 default:
1385 ret = -1;
1386 break;
1387 }
1388
1389 return ret;
1390 }
1391
1392 static void ppc4xx_gpt_writel (void *opaque,
1393 target_phys_addr_t addr, uint32_t value)
1394 {
1395 ppc4xx_gpt_t *gpt;
1396 int idx;
1397
1398 #ifdef DEBUG_I2C
1399 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1400 value);
1401 #endif
1402 gpt = opaque;
1403 switch (addr) {
1404 case 0x00:
1405 /* Time base counter */
1406 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1407 - qemu_get_clock_ns(vm_clock);
1408 ppc4xx_gpt_compute_timer(gpt);
1409 break;
1410 case 0x10:
1411 /* Output enable */
1412 gpt->oe = value & 0xF8000000;
1413 ppc4xx_gpt_set_outputs(gpt);
1414 break;
1415 case 0x14:
1416 /* Output level */
1417 gpt->ol = value & 0xF8000000;
1418 ppc4xx_gpt_set_outputs(gpt);
1419 break;
1420 case 0x18:
1421 /* Interrupt mask */
1422 gpt->im = value & 0x0000F800;
1423 break;
1424 case 0x1C:
1425 /* Interrupt status set */
1426 gpt->is |= value & 0x0000F800;
1427 ppc4xx_gpt_set_irqs(gpt);
1428 break;
1429 case 0x20:
1430 /* Interrupt status clear */
1431 gpt->is &= ~(value & 0x0000F800);
1432 ppc4xx_gpt_set_irqs(gpt);
1433 break;
1434 case 0x24:
1435 /* Interrupt enable */
1436 gpt->ie = value & 0x0000F800;
1437 ppc4xx_gpt_set_irqs(gpt);
1438 break;
1439 case 0x80 ... 0x90:
1440 /* Compare timer */
1441 idx = (addr - 0x80) >> 2;
1442 gpt->comp[idx] = value & 0xF8000000;
1443 ppc4xx_gpt_compute_timer(gpt);
1444 break;
1445 case 0xC0 ... 0xD0:
1446 /* Compare mask */
1447 idx = (addr - 0xC0) >> 2;
1448 gpt->mask[idx] = value & 0xF8000000;
1449 ppc4xx_gpt_compute_timer(gpt);
1450 break;
1451 }
1452 }
1453
1454 static CPUReadMemoryFunc * const gpt_read[] = {
1455 &ppc4xx_gpt_readb,
1456 &ppc4xx_gpt_readw,
1457 &ppc4xx_gpt_readl,
1458 };
1459
1460 static CPUWriteMemoryFunc * const gpt_write[] = {
1461 &ppc4xx_gpt_writeb,
1462 &ppc4xx_gpt_writew,
1463 &ppc4xx_gpt_writel,
1464 };
1465
1466 static void ppc4xx_gpt_cb (void *opaque)
1467 {
1468 ppc4xx_gpt_t *gpt;
1469
1470 gpt = opaque;
1471 ppc4xx_gpt_set_irqs(gpt);
1472 ppc4xx_gpt_set_outputs(gpt);
1473 ppc4xx_gpt_compute_timer(gpt);
1474 }
1475
1476 static void ppc4xx_gpt_reset (void *opaque)
1477 {
1478 ppc4xx_gpt_t *gpt;
1479 int i;
1480
1481 gpt = opaque;
1482 qemu_del_timer(gpt->timer);
1483 gpt->oe = 0x00000000;
1484 gpt->ol = 0x00000000;
1485 gpt->im = 0x00000000;
1486 gpt->is = 0x00000000;
1487 gpt->ie = 0x00000000;
1488 for (i = 0; i < 5; i++) {
1489 gpt->comp[i] = 0x00000000;
1490 gpt->mask[i] = 0x00000000;
1491 }
1492 }
1493
1494 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1495 {
1496 ppc4xx_gpt_t *gpt;
1497 int i;
1498 int io;
1499
1500 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1501 for (i = 0; i < 5; i++) {
1502 gpt->irqs[i] = irqs[i];
1503 }
1504 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1505 #ifdef DEBUG_GPT
1506 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1507 #endif
1508 io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
1509 cpu_register_physical_memory(base, 0x0d4, io);
1510 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1511 }
1512
1513 /*****************************************************************************/
1514 /* MAL */
1515 enum {
1516 MAL0_CFG = 0x180,
1517 MAL0_ESR = 0x181,
1518 MAL0_IER = 0x182,
1519 MAL0_TXCASR = 0x184,
1520 MAL0_TXCARR = 0x185,
1521 MAL0_TXEOBISR = 0x186,
1522 MAL0_TXDEIR = 0x187,
1523 MAL0_RXCASR = 0x190,
1524 MAL0_RXCARR = 0x191,
1525 MAL0_RXEOBISR = 0x192,
1526 MAL0_RXDEIR = 0x193,
1527 MAL0_TXCTP0R = 0x1A0,
1528 MAL0_TXCTP1R = 0x1A1,
1529 MAL0_TXCTP2R = 0x1A2,
1530 MAL0_TXCTP3R = 0x1A3,
1531 MAL0_RXCTP0R = 0x1C0,
1532 MAL0_RXCTP1R = 0x1C1,
1533 MAL0_RCBS0 = 0x1E0,
1534 MAL0_RCBS1 = 0x1E1,
1535 };
1536
1537 typedef struct ppc40x_mal_t ppc40x_mal_t;
1538 struct ppc40x_mal_t {
1539 qemu_irq irqs[4];
1540 uint32_t cfg;
1541 uint32_t esr;
1542 uint32_t ier;
1543 uint32_t txcasr;
1544 uint32_t txcarr;
1545 uint32_t txeobisr;
1546 uint32_t txdeir;
1547 uint32_t rxcasr;
1548 uint32_t rxcarr;
1549 uint32_t rxeobisr;
1550 uint32_t rxdeir;
1551 uint32_t txctpr[4];
1552 uint32_t rxctpr[2];
1553 uint32_t rcbs[2];
1554 };
1555
1556 static void ppc40x_mal_reset (void *opaque);
1557
1558 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1559 {
1560 ppc40x_mal_t *mal;
1561 uint32_t ret;
1562
1563 mal = opaque;
1564 switch (dcrn) {
1565 case MAL0_CFG:
1566 ret = mal->cfg;
1567 break;
1568 case MAL0_ESR:
1569 ret = mal->esr;
1570 break;
1571 case MAL0_IER:
1572 ret = mal->ier;
1573 break;
1574 case MAL0_TXCASR:
1575 ret = mal->txcasr;
1576 break;
1577 case MAL0_TXCARR:
1578 ret = mal->txcarr;
1579 break;
1580 case MAL0_TXEOBISR:
1581 ret = mal->txeobisr;
1582 break;
1583 case MAL0_TXDEIR:
1584 ret = mal->txdeir;
1585 break;
1586 case MAL0_RXCASR:
1587 ret = mal->rxcasr;
1588 break;
1589 case MAL0_RXCARR:
1590 ret = mal->rxcarr;
1591 break;
1592 case MAL0_RXEOBISR:
1593 ret = mal->rxeobisr;
1594 break;
1595 case MAL0_RXDEIR:
1596 ret = mal->rxdeir;
1597 break;
1598 case MAL0_TXCTP0R:
1599 ret = mal->txctpr[0];
1600 break;
1601 case MAL0_TXCTP1R:
1602 ret = mal->txctpr[1];
1603 break;
1604 case MAL0_TXCTP2R:
1605 ret = mal->txctpr[2];
1606 break;
1607 case MAL0_TXCTP3R:
1608 ret = mal->txctpr[3];
1609 break;
1610 case MAL0_RXCTP0R:
1611 ret = mal->rxctpr[0];
1612 break;
1613 case MAL0_RXCTP1R:
1614 ret = mal->rxctpr[1];
1615 break;
1616 case MAL0_RCBS0:
1617 ret = mal->rcbs[0];
1618 break;
1619 case MAL0_RCBS1:
1620 ret = mal->rcbs[1];
1621 break;
1622 default:
1623 ret = 0;
1624 break;
1625 }
1626
1627 return ret;
1628 }
1629
1630 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1631 {
1632 ppc40x_mal_t *mal;
1633 int idx;
1634
1635 mal = opaque;
1636 switch (dcrn) {
1637 case MAL0_CFG:
1638 if (val & 0x80000000)
1639 ppc40x_mal_reset(mal);
1640 mal->cfg = val & 0x00FFC087;
1641 break;
1642 case MAL0_ESR:
1643 /* Read/clear */
1644 mal->esr &= ~val;
1645 break;
1646 case MAL0_IER:
1647 mal->ier = val & 0x0000001F;
1648 break;
1649 case MAL0_TXCASR:
1650 mal->txcasr = val & 0xF0000000;
1651 break;
1652 case MAL0_TXCARR:
1653 mal->txcarr = val & 0xF0000000;
1654 break;
1655 case MAL0_TXEOBISR:
1656 /* Read/clear */
1657 mal->txeobisr &= ~val;
1658 break;
1659 case MAL0_TXDEIR:
1660 /* Read/clear */
1661 mal->txdeir &= ~val;
1662 break;
1663 case MAL0_RXCASR:
1664 mal->rxcasr = val & 0xC0000000;
1665 break;
1666 case MAL0_RXCARR:
1667 mal->rxcarr = val & 0xC0000000;
1668 break;
1669 case MAL0_RXEOBISR:
1670 /* Read/clear */
1671 mal->rxeobisr &= ~val;
1672 break;
1673 case MAL0_RXDEIR:
1674 /* Read/clear */
1675 mal->rxdeir &= ~val;
1676 break;
1677 case MAL0_TXCTP0R:
1678 idx = 0;
1679 goto update_tx_ptr;
1680 case MAL0_TXCTP1R:
1681 idx = 1;
1682 goto update_tx_ptr;
1683 case MAL0_TXCTP2R:
1684 idx = 2;
1685 goto update_tx_ptr;
1686 case MAL0_TXCTP3R:
1687 idx = 3;
1688 update_tx_ptr:
1689 mal->txctpr[idx] = val;
1690 break;
1691 case MAL0_RXCTP0R:
1692 idx = 0;
1693 goto update_rx_ptr;
1694 case MAL0_RXCTP1R:
1695 idx = 1;
1696 update_rx_ptr:
1697 mal->rxctpr[idx] = val;
1698 break;
1699 case MAL0_RCBS0:
1700 idx = 0;
1701 goto update_rx_size;
1702 case MAL0_RCBS1:
1703 idx = 1;
1704 update_rx_size:
1705 mal->rcbs[idx] = val & 0x000000FF;
1706 break;
1707 }
1708 }
1709
1710 static void ppc40x_mal_reset (void *opaque)
1711 {
1712 ppc40x_mal_t *mal;
1713
1714 mal = opaque;
1715 mal->cfg = 0x0007C000;
1716 mal->esr = 0x00000000;
1717 mal->ier = 0x00000000;
1718 mal->rxcasr = 0x00000000;
1719 mal->rxdeir = 0x00000000;
1720 mal->rxeobisr = 0x00000000;
1721 mal->txcasr = 0x00000000;
1722 mal->txdeir = 0x00000000;
1723 mal->txeobisr = 0x00000000;
1724 }
1725
1726 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1727 {
1728 ppc40x_mal_t *mal;
1729 int i;
1730
1731 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1732 for (i = 0; i < 4; i++)
1733 mal->irqs[i] = irqs[i];
1734 qemu_register_reset(&ppc40x_mal_reset, mal);
1735 ppc_dcr_register(env, MAL0_CFG,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_ESR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_IER,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXCASR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXCARR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_TXEOBISR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_TXDEIR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXCASR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXCARR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_RXEOBISR,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_RXDEIR,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP0R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP1R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_TXCTP2R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_TXCTP3R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RXCTP0R,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RXCTP1R,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 ppc_dcr_register(env, MAL0_RCBS0,
1770 mal, &dcr_read_mal, &dcr_write_mal);
1771 ppc_dcr_register(env, MAL0_RCBS1,
1772 mal, &dcr_read_mal, &dcr_write_mal);
1773 }
1774
1775 /*****************************************************************************/
1776 /* SPR */
1777 void ppc40x_core_reset (CPUState *env)
1778 {
1779 target_ulong dbsr;
1780
1781 printf("Reset PowerPC core\n");
1782 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1783 /* XXX: TOFIX */
1784 #if 0
1785 cpu_reset(env);
1786 #else
1787 qemu_system_reset_request();
1788 #endif
1789 dbsr = env->spr[SPR_40x_DBSR];
1790 dbsr &= ~0x00000300;
1791 dbsr |= 0x00000100;
1792 env->spr[SPR_40x_DBSR] = dbsr;
1793 }
1794
1795 void ppc40x_chip_reset (CPUState *env)
1796 {
1797 target_ulong dbsr;
1798
1799 printf("Reset PowerPC chip\n");
1800 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1801 /* XXX: TOFIX */
1802 #if 0
1803 cpu_reset(env);
1804 #else
1805 qemu_system_reset_request();
1806 #endif
1807 /* XXX: TODO reset all internal peripherals */
1808 dbsr = env->spr[SPR_40x_DBSR];
1809 dbsr &= ~0x00000300;
1810 dbsr |= 0x00000200;
1811 env->spr[SPR_40x_DBSR] = dbsr;
1812 }
1813
1814 void ppc40x_system_reset (CPUState *env)
1815 {
1816 printf("Reset PowerPC system\n");
1817 qemu_system_reset_request();
1818 }
1819
1820 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1821 {
1822 switch ((val >> 28) & 0x3) {
1823 case 0x0:
1824 /* No action */
1825 break;
1826 case 0x1:
1827 /* Core reset */
1828 ppc40x_core_reset(env);
1829 break;
1830 case 0x2:
1831 /* Chip reset */
1832 ppc40x_chip_reset(env);
1833 break;
1834 case 0x3:
1835 /* System reset */
1836 ppc40x_system_reset(env);
1837 break;
1838 }
1839 }
1840
1841 /*****************************************************************************/
1842 /* PowerPC 405CR */
1843 enum {
1844 PPC405CR_CPC0_PLLMR = 0x0B0,
1845 PPC405CR_CPC0_CR0 = 0x0B1,
1846 PPC405CR_CPC0_CR1 = 0x0B2,
1847 PPC405CR_CPC0_PSR = 0x0B4,
1848 PPC405CR_CPC0_JTAGID = 0x0B5,
1849 PPC405CR_CPC0_ER = 0x0B9,
1850 PPC405CR_CPC0_FR = 0x0BA,
1851 PPC405CR_CPC0_SR = 0x0BB,
1852 };
1853
1854 enum {
1855 PPC405CR_CPU_CLK = 0,
1856 PPC405CR_TMR_CLK = 1,
1857 PPC405CR_PLB_CLK = 2,
1858 PPC405CR_SDRAM_CLK = 3,
1859 PPC405CR_OPB_CLK = 4,
1860 PPC405CR_EXT_CLK = 5,
1861 PPC405CR_UART_CLK = 6,
1862 PPC405CR_CLK_NB = 7,
1863 };
1864
1865 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1866 struct ppc405cr_cpc_t {
1867 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1868 uint32_t sysclk;
1869 uint32_t psr;
1870 uint32_t cr0;
1871 uint32_t cr1;
1872 uint32_t jtagid;
1873 uint32_t pllmr;
1874 uint32_t er;
1875 uint32_t fr;
1876 };
1877
1878 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1879 {
1880 uint64_t VCO_out, PLL_out;
1881 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1882 int M, D0, D1, D2;
1883
1884 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1885 if (cpc->pllmr & 0x80000000) {
1886 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1887 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1888 M = D0 * D1 * D2;
1889 VCO_out = cpc->sysclk * M;
1890 if (VCO_out < 400000000 || VCO_out > 800000000) {
1891 /* PLL cannot lock */
1892 cpc->pllmr &= ~0x80000000;
1893 goto bypass_pll;
1894 }
1895 PLL_out = VCO_out / D2;
1896 } else {
1897 /* Bypass PLL */
1898 bypass_pll:
1899 M = D0;
1900 PLL_out = cpc->sysclk * M;
1901 }
1902 CPU_clk = PLL_out;
1903 if (cpc->cr1 & 0x00800000)
1904 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1905 else
1906 TMR_clk = CPU_clk;
1907 PLB_clk = CPU_clk / D0;
1908 SDRAM_clk = PLB_clk;
1909 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1910 OPB_clk = PLB_clk / D0;
1911 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1912 EXT_clk = PLB_clk / D0;
1913 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1914 UART_clk = CPU_clk / D0;
1915 /* Setup CPU clocks */
1916 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1917 /* Setup time-base clock */
1918 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1919 /* Setup PLB clock */
1920 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1921 /* Setup SDRAM clock */
1922 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1923 /* Setup OPB clock */
1924 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1925 /* Setup external clock */
1926 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1927 /* Setup UART clock */
1928 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1929 }
1930
1931 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1932 {
1933 ppc405cr_cpc_t *cpc;
1934 uint32_t ret;
1935
1936 cpc = opaque;
1937 switch (dcrn) {
1938 case PPC405CR_CPC0_PLLMR:
1939 ret = cpc->pllmr;
1940 break;
1941 case PPC405CR_CPC0_CR0:
1942 ret = cpc->cr0;
1943 break;
1944 case PPC405CR_CPC0_CR1:
1945 ret = cpc->cr1;
1946 break;
1947 case PPC405CR_CPC0_PSR:
1948 ret = cpc->psr;
1949 break;
1950 case PPC405CR_CPC0_JTAGID:
1951 ret = cpc->jtagid;
1952 break;
1953 case PPC405CR_CPC0_ER:
1954 ret = cpc->er;
1955 break;
1956 case PPC405CR_CPC0_FR:
1957 ret = cpc->fr;
1958 break;
1959 case PPC405CR_CPC0_SR:
1960 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1961 break;
1962 default:
1963 /* Avoid gcc warning */
1964 ret = 0;
1965 break;
1966 }
1967
1968 return ret;
1969 }
1970
1971 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1972 {
1973 ppc405cr_cpc_t *cpc;
1974
1975 cpc = opaque;
1976 switch (dcrn) {
1977 case PPC405CR_CPC0_PLLMR:
1978 cpc->pllmr = val & 0xFFF77C3F;
1979 break;
1980 case PPC405CR_CPC0_CR0:
1981 cpc->cr0 = val & 0x0FFFFFFE;
1982 break;
1983 case PPC405CR_CPC0_CR1:
1984 cpc->cr1 = val & 0x00800000;
1985 break;
1986 case PPC405CR_CPC0_PSR:
1987 /* Read-only */
1988 break;
1989 case PPC405CR_CPC0_JTAGID:
1990 /* Read-only */
1991 break;
1992 case PPC405CR_CPC0_ER:
1993 cpc->er = val & 0xBFFC0000;
1994 break;
1995 case PPC405CR_CPC0_FR:
1996 cpc->fr = val & 0xBFFC0000;
1997 break;
1998 case PPC405CR_CPC0_SR:
1999 /* Read-only */
2000 break;
2001 }
2002 }
2003
2004 static void ppc405cr_cpc_reset (void *opaque)
2005 {
2006 ppc405cr_cpc_t *cpc;
2007 int D;
2008
2009 cpc = opaque;
2010 /* Compute PLLMR value from PSR settings */
2011 cpc->pllmr = 0x80000000;
2012 /* PFWD */
2013 switch ((cpc->psr >> 30) & 3) {
2014 case 0:
2015 /* Bypass */
2016 cpc->pllmr &= ~0x80000000;
2017 break;
2018 case 1:
2019 /* Divide by 3 */
2020 cpc->pllmr |= 5 << 16;
2021 break;
2022 case 2:
2023 /* Divide by 4 */
2024 cpc->pllmr |= 4 << 16;
2025 break;
2026 case 3:
2027 /* Divide by 6 */
2028 cpc->pllmr |= 2 << 16;
2029 break;
2030 }
2031 /* PFBD */
2032 D = (cpc->psr >> 28) & 3;
2033 cpc->pllmr |= (D + 1) << 20;
2034 /* PT */
2035 D = (cpc->psr >> 25) & 7;
2036 switch (D) {
2037 case 0x2:
2038 cpc->pllmr |= 0x13;
2039 break;
2040 case 0x4:
2041 cpc->pllmr |= 0x15;
2042 break;
2043 case 0x5:
2044 cpc->pllmr |= 0x16;
2045 break;
2046 default:
2047 break;
2048 }
2049 /* PDC */
2050 D = (cpc->psr >> 23) & 3;
2051 cpc->pllmr |= D << 26;
2052 /* ODP */
2053 D = (cpc->psr >> 21) & 3;
2054 cpc->pllmr |= D << 10;
2055 /* EBPD */
2056 D = (cpc->psr >> 17) & 3;
2057 cpc->pllmr |= D << 24;
2058 cpc->cr0 = 0x0000003C;
2059 cpc->cr1 = 0x2B0D8800;
2060 cpc->er = 0x00000000;
2061 cpc->fr = 0x00000000;
2062 ppc405cr_clk_setup(cpc);
2063 }
2064
2065 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2066 {
2067 int D;
2068
2069 /* XXX: this should be read from IO pins */
2070 cpc->psr = 0x00000000; /* 8 bits ROM */
2071 /* PFWD */
2072 D = 0x2; /* Divide by 4 */
2073 cpc->psr |= D << 30;
2074 /* PFBD */
2075 D = 0x1; /* Divide by 2 */
2076 cpc->psr |= D << 28;
2077 /* PDC */
2078 D = 0x1; /* Divide by 2 */
2079 cpc->psr |= D << 23;
2080 /* PT */
2081 D = 0x5; /* M = 16 */
2082 cpc->psr |= D << 25;
2083 /* ODP */
2084 D = 0x1; /* Divide by 2 */
2085 cpc->psr |= D << 21;
2086 /* EBDP */
2087 D = 0x2; /* Divide by 4 */
2088 cpc->psr |= D << 17;
2089 }
2090
2091 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2092 uint32_t sysclk)
2093 {
2094 ppc405cr_cpc_t *cpc;
2095
2096 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2097 memcpy(cpc->clk_setup, clk_setup,
2098 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2099 cpc->sysclk = sysclk;
2100 cpc->jtagid = 0x42051049;
2101 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2106 &dcr_read_crcpc, &dcr_write_crcpc);
2107 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2108 &dcr_read_crcpc, &dcr_write_crcpc);
2109 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2110 &dcr_read_crcpc, &dcr_write_crcpc);
2111 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2112 &dcr_read_crcpc, &dcr_write_crcpc);
2113 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2114 &dcr_read_crcpc, &dcr_write_crcpc);
2115 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2116 &dcr_read_crcpc, &dcr_write_crcpc);
2117 ppc405cr_clk_init(cpc);
2118 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2119 }
2120
2121 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2122 target_phys_addr_t ram_sizes[4],
2123 uint32_t sysclk, qemu_irq **picp,
2124 int do_init)
2125 {
2126 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2127 qemu_irq dma_irqs[4];
2128 CPUState *env;
2129 qemu_irq *pic, *irqs;
2130
2131 memset(clk_setup, 0, sizeof(clk_setup));
2132 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2133 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2134 /* Memory mapped devices registers */
2135 /* PLB arbitrer */
2136 ppc4xx_plb_init(env);
2137 /* PLB to OPB bridge */
2138 ppc4xx_pob_init(env);
2139 /* OBP arbitrer */
2140 ppc4xx_opba_init(0xef600600);
2141 /* Universal interrupt controller */
2142 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2143 irqs[PPCUIC_OUTPUT_INT] =
2144 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2145 irqs[PPCUIC_OUTPUT_CINT] =
2146 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2147 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2148 *picp = pic;
2149 /* SDRAM controller */
2150 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2151 /* External bus controller */
2152 ppc405_ebc_init(env);
2153 /* DMA controller */
2154 dma_irqs[0] = pic[26];
2155 dma_irqs[1] = pic[25];
2156 dma_irqs[2] = pic[24];
2157 dma_irqs[3] = pic[23];
2158 ppc405_dma_init(env, dma_irqs);
2159 /* Serial ports */
2160 if (serial_hds[0] != NULL) {
2161 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2162 serial_hds[0], 1, 1);
2163 }
2164 if (serial_hds[1] != NULL) {
2165 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2166 serial_hds[1], 1, 1);
2167 }
2168 /* IIC controller */
2169 ppc405_i2c_init(0xef600500, pic[2]);
2170 /* GPIO */
2171 ppc405_gpio_init(0xef600700);
2172 /* CPU control */
2173 ppc405cr_cpc_init(env, clk_setup, sysclk);
2174
2175 return env;
2176 }
2177
2178 /*****************************************************************************/
2179 /* PowerPC 405EP */
2180 /* CPU control */
2181 enum {
2182 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2183 PPC405EP_CPC0_BOOT = 0x0F1,
2184 PPC405EP_CPC0_EPCTL = 0x0F3,
2185 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2186 PPC405EP_CPC0_UCR = 0x0F5,
2187 PPC405EP_CPC0_SRR = 0x0F6,
2188 PPC405EP_CPC0_JTAGID = 0x0F7,
2189 PPC405EP_CPC0_PCI = 0x0F9,
2190 #if 0
2191 PPC405EP_CPC0_ER = xxx,
2192 PPC405EP_CPC0_FR = xxx,
2193 PPC405EP_CPC0_SR = xxx,
2194 #endif
2195 };
2196
2197 enum {
2198 PPC405EP_CPU_CLK = 0,
2199 PPC405EP_PLB_CLK = 1,
2200 PPC405EP_OPB_CLK = 2,
2201 PPC405EP_EBC_CLK = 3,
2202 PPC405EP_MAL_CLK = 4,
2203 PPC405EP_PCI_CLK = 5,
2204 PPC405EP_UART0_CLK = 6,
2205 PPC405EP_UART1_CLK = 7,
2206 PPC405EP_CLK_NB = 8,
2207 };
2208
2209 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2210 struct ppc405ep_cpc_t {
2211 uint32_t sysclk;
2212 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2213 uint32_t boot;
2214 uint32_t epctl;
2215 uint32_t pllmr[2];
2216 uint32_t ucr;
2217 uint32_t srr;
2218 uint32_t jtagid;
2219 uint32_t pci;
2220 /* Clock and power management */
2221 uint32_t er;
2222 uint32_t fr;
2223 uint32_t sr;
2224 };
2225
2226 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2227 {
2228 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2229 uint32_t UART0_clk, UART1_clk;
2230 uint64_t VCO_out, PLL_out;
2231 int M, D;
2232
2233 VCO_out = 0;
2234 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2235 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2236 #ifdef DEBUG_CLOCKS_LL
2237 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2238 #endif
2239 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2240 #ifdef DEBUG_CLOCKS_LL
2241 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2242 #endif
2243 VCO_out = cpc->sysclk * M * D;
2244 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2245 /* Error - unlock the PLL */
2246 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2247 #if 0
2248 cpc->pllmr[1] &= ~0x80000000;
2249 goto pll_bypass;
2250 #endif
2251 }
2252 PLL_out = VCO_out / D;
2253 /* Pretend the PLL is locked */
2254 cpc->boot |= 0x00000001;
2255 } else {
2256 #if 0
2257 pll_bypass:
2258 #endif
2259 PLL_out = cpc->sysclk;
2260 if (cpc->pllmr[1] & 0x40000000) {
2261 /* Pretend the PLL is not locked */
2262 cpc->boot &= ~0x00000001;
2263 }
2264 }
2265 /* Now, compute all other clocks */
2266 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2267 #ifdef DEBUG_CLOCKS_LL
2268 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2269 #endif
2270 CPU_clk = PLL_out / D;
2271 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2272 #ifdef DEBUG_CLOCKS_LL
2273 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2274 #endif
2275 PLB_clk = CPU_clk / D;
2276 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2277 #ifdef DEBUG_CLOCKS_LL
2278 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2279 #endif
2280 OPB_clk = PLB_clk / D;
2281 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2282 #ifdef DEBUG_CLOCKS_LL
2283 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2284 #endif
2285 EBC_clk = PLB_clk / D;
2286 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2287 #ifdef DEBUG_CLOCKS_LL
2288 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2289 #endif
2290 MAL_clk = PLB_clk / D;
2291 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2292 #ifdef DEBUG_CLOCKS_LL
2293 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2294 #endif
2295 PCI_clk = PLB_clk / D;
2296 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2297 #ifdef DEBUG_CLOCKS_LL
2298 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2299 #endif
2300 UART0_clk = PLL_out / D;
2301 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2302 #ifdef DEBUG_CLOCKS_LL
2303 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2304 #endif
2305 UART1_clk = PLL_out / D;
2306 #ifdef DEBUG_CLOCKS
2307 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2308 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2309 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2310 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2311 " UART1 %" PRIu32 "\n",
2312 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2313 UART0_clk, UART1_clk);
2314 #endif
2315 /* Setup CPU clocks */
2316 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2317 /* Setup PLB clock */
2318 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2319 /* Setup OPB clock */
2320 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2321 /* Setup external clock */
2322 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2323 /* Setup MAL clock */
2324 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2325 /* Setup PCI clock */
2326 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2327 /* Setup UART0 clock */
2328 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2329 /* Setup UART1 clock */
2330 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2331 }
2332
2333 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2334 {
2335 ppc405ep_cpc_t *cpc;
2336 uint32_t ret;
2337
2338 cpc = opaque;
2339 switch (dcrn) {
2340 case PPC405EP_CPC0_BOOT:
2341 ret = cpc->boot;
2342 break;
2343 case PPC405EP_CPC0_EPCTL:
2344 ret = cpc->epctl;
2345 break;
2346 case PPC405EP_CPC0_PLLMR0:
2347 ret = cpc->pllmr[0];
2348 break;
2349 case PPC405EP_CPC0_PLLMR1:
2350 ret = cpc->pllmr[1];
2351 break;
2352 case PPC405EP_CPC0_UCR:
2353 ret = cpc->ucr;
2354 break;
2355 case PPC405EP_CPC0_SRR:
2356 ret = cpc->srr;
2357 break;
2358 case PPC405EP_CPC0_JTAGID:
2359 ret = cpc->jtagid;
2360 break;
2361 case PPC405EP_CPC0_PCI:
2362 ret = cpc->pci;
2363 break;
2364 default:
2365 /* Avoid gcc warning */
2366 ret = 0;
2367 break;
2368 }
2369
2370 return ret;
2371 }
2372
2373 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2374 {
2375 ppc405ep_cpc_t *cpc;
2376
2377 cpc = opaque;
2378 switch (dcrn) {
2379 case PPC405EP_CPC0_BOOT:
2380 /* Read-only register */
2381 break;
2382 case PPC405EP_CPC0_EPCTL:
2383 /* Don't care for now */
2384 cpc->epctl = val & 0xC00000F3;
2385 break;
2386 case PPC405EP_CPC0_PLLMR0:
2387 cpc->pllmr[0] = val & 0x00633333;
2388 ppc405ep_compute_clocks(cpc);
2389 break;
2390 case PPC405EP_CPC0_PLLMR1:
2391 cpc->pllmr[1] = val & 0xC0F73FFF;
2392 ppc405ep_compute_clocks(cpc);
2393 break;
2394 case PPC405EP_CPC0_UCR:
2395 /* UART control - don't care for now */
2396 cpc->ucr = val & 0x003F7F7F;
2397 break;
2398 case PPC405EP_CPC0_SRR:
2399 cpc->srr = val;
2400 break;
2401 case PPC405EP_CPC0_JTAGID:
2402 /* Read-only */
2403 break;
2404 case PPC405EP_CPC0_PCI:
2405 cpc->pci = val;
2406 break;
2407 }
2408 }
2409
2410 static void ppc405ep_cpc_reset (void *opaque)
2411 {
2412 ppc405ep_cpc_t *cpc = opaque;
2413
2414 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2415 cpc->epctl = 0x00000000;
2416 cpc->pllmr[0] = 0x00011010;
2417 cpc->pllmr[1] = 0x40000000;
2418 cpc->ucr = 0x00000000;
2419 cpc->srr = 0x00040000;
2420 cpc->pci = 0x00000000;
2421 cpc->er = 0x00000000;
2422 cpc->fr = 0x00000000;
2423 cpc->sr = 0x00000000;
2424 ppc405ep_compute_clocks(cpc);
2425 }
2426
2427 /* XXX: sysclk should be between 25 and 100 MHz */
2428 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2429 uint32_t sysclk)
2430 {
2431 ppc405ep_cpc_t *cpc;
2432
2433 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2434 memcpy(cpc->clk_setup, clk_setup,
2435 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2436 cpc->jtagid = 0x20267049;
2437 cpc->sysclk = sysclk;
2438 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2439 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2446 &dcr_read_epcpc, &dcr_write_epcpc);
2447 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2453 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2454 &dcr_read_epcpc, &dcr_write_epcpc);
2455 #if 0
2456 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2459 &dcr_read_epcpc, &dcr_write_epcpc);
2460 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2461 &dcr_read_epcpc, &dcr_write_epcpc);
2462 #endif
2463 }
2464
2465 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2466 target_phys_addr_t ram_sizes[2],
2467 uint32_t sysclk, qemu_irq **picp,
2468 int do_init)
2469 {
2470 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2471 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2472 CPUState *env;
2473 qemu_irq *pic, *irqs;
2474
2475 memset(clk_setup, 0, sizeof(clk_setup));
2476 /* init CPUs */
2477 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2478 &tlb_clk_setup, sysclk);
2479 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2480 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2481 /* Internal devices init */
2482 /* Memory mapped devices registers */
2483 /* PLB arbitrer */
2484 ppc4xx_plb_init(env);
2485 /* PLB to OPB bridge */
2486 ppc4xx_pob_init(env);
2487 /* OBP arbitrer */
2488 ppc4xx_opba_init(0xef600600);
2489 /* Universal interrupt controller */
2490 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2491 irqs[PPCUIC_OUTPUT_INT] =
2492 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2493 irqs[PPCUIC_OUTPUT_CINT] =
2494 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2495 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2496 *picp = pic;
2497 /* SDRAM controller */
2498 /* XXX 405EP has no ECC interrupt */
2499 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2500 /* External bus controller */
2501 ppc405_ebc_init(env);
2502 /* DMA controller */
2503 dma_irqs[0] = pic[5];
2504 dma_irqs[1] = pic[6];
2505 dma_irqs[2] = pic[7];
2506 dma_irqs[3] = pic[8];
2507 ppc405_dma_init(env, dma_irqs);
2508 /* IIC controller */
2509 ppc405_i2c_init(0xef600500, pic[2]);
2510 /* GPIO */
2511 ppc405_gpio_init(0xef600700);
2512 /* Serial ports */
2513 if (serial_hds[0] != NULL) {
2514 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2515 serial_hds[0], 1, 1);
2516 }
2517 if (serial_hds[1] != NULL) {
2518 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2519 serial_hds[1], 1, 1);
2520 }
2521 /* OCM */
2522 ppc405_ocm_init(env);
2523 /* GPT */
2524 gpt_irqs[0] = pic[19];
2525 gpt_irqs[1] = pic[20];
2526 gpt_irqs[2] = pic[21];
2527 gpt_irqs[3] = pic[22];
2528 gpt_irqs[4] = pic[23];
2529 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2530 /* PCI */
2531 /* Uses pic[3], pic[16], pic[18] */
2532 /* MAL */
2533 mal_irqs[0] = pic[11];
2534 mal_irqs[1] = pic[12];
2535 mal_irqs[2] = pic[13];
2536 mal_irqs[3] = pic[14];
2537 ppc405_mal_init(env, mal_irqs);
2538 /* Ethernet */
2539 /* Uses pic[9], pic[15], pic[17] */
2540 /* CPU control */
2541 ppc405ep_cpc_init(env, clk_setup, sysclk);
2542
2543 return env;
2544 }
QEmu