hw/ppc/ppc4xx_sdram.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors SDRAM controller emulation
   3  *
   4  * DDR SDRAM controller:
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * DDR2 SDRAM controller:
  26  * Copyright (c) 2012 François Revol
  27  * Copyright (c) 2016-2019 BALATON Zoltan
  28  *
  29  * This work is licensed under the GNU GPL license version 2 or later.
  30  */
  31
  32 #include "qemu/osdep.h"
  33 #include "qemu/units.h"
  34 #include "qapi/error.h"
  35 #include "qemu/log.h"
  36 #include "exec/address-spaces.h" /* get_system_memory() */
  37 #include "hw/irq.h"
  38 #include "hw/qdev-properties.h"
  39 #include "hw/ppc/ppc4xx.h"
  40 #include "trace.h"
  41
  42 /*****************************************************************************/
  43 /* Shared functions */
  44
  45 /*
  46  * Split RAM between SDRAM banks.
  47  *
  48  * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
  49  * and must be 0-terminated.
  50  *
  51  * The 4xx SDRAM controller supports a small number of banks, and each bank
  52  * must be one of a small set of sizes. The number of banks and the supported
  53  * sizes varies by SoC.
  54  */
  55 static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
  56                                Ppc4xxSdramBank ram_banks[],
  57                                const ram_addr_t sdram_bank_sizes[],
  58                                Error **errp)
  59 {
  60     ERRP_GUARD();
  61     ram_addr_t size_left = memory_region_size(ram);
  62     ram_addr_t base = 0;
  63     ram_addr_t bank_size;
  64     int i;
  65     int j;
  66
  67     for (i = 0; i < nr_banks; i++) {
  68         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
  69             bank_size = sdram_bank_sizes[j];
  70             if (bank_size <= size_left) {
  71                 char name[32];
  72
  73                 ram_banks[i].base = base;
  74                 ram_banks[i].size = bank_size;
  75                 base += bank_size;
  76                 size_left -= bank_size;
  77                 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
  78                 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
  79                                          ram_banks[i].base, ram_banks[i].size);
  80                 break;
  81             }
  82         }
  83         if (!size_left) {
  84             /* No need to use the remaining banks. */
  85             break;
  86         }
  87     }
  88
  89     if (size_left) {
  90         ram_addr_t used_size = memory_region_size(ram) - size_left;
  91         GString *s = g_string_new(NULL);
  92
  93         for (i = 0; sdram_bank_sizes[i]; i++) {
  94             g_string_append_printf(s, "%" PRIi64 "%s",
  95                                    sdram_bank_sizes[i] / MiB,
  96                                    sdram_bank_sizes[i + 1] ? ", " : "");
  97         }
  98         error_setg(errp, "Invalid SDRAM banks");
  99         error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n",
 100                           nr_banks, nr_banks == 1 ? "" : "s", s->str);
 101         error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n",
 102                   used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
 103
 104         g_string_free(s, true);
 105         return false;
 106     }
 107     return true;
 108 }
 109
 110 static void sdram_bank_map(Ppc4xxSdramBank *bank)
 111 {
 112     trace_ppc4xx_sdram_map(bank->base, bank->size);
 113     memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
 114     memory_region_add_subregion(&bank->container, 0, &bank->ram);
 115     memory_region_add_subregion(get_system_memory(), bank->base,
 116                                 &bank->container);
 117 }
 118
 119 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
 120 {
 121     trace_ppc4xx_sdram_unmap(bank->base, bank->size);
 122     memory_region_del_subregion(get_system_memory(), &bank->container);
 123     memory_region_del_subregion(&bank->container, &bank->ram);
 124     object_unparent(OBJECT(&bank->container));
 125 }
 126
 127 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
 128                                hwaddr base, hwaddr size, int enabled)
 129 {
 130     if (memory_region_is_mapped(&bank->container)) {
 131         sdram_bank_unmap(bank);
 132     }
 133     bank->bcr = bcr;
 134     bank->base = base;
 135     bank->size = size;
 136     if (enabled && (bcr & 1)) {
 137         sdram_bank_map(bank);
 138     }
 139 }
 140
 141 enum {
 142     SDRAM0_CFGADDR = 0x010,
 143     SDRAM0_CFGDATA = 0x011,
 144 };
 145
 146 /*****************************************************************************/
 147 /* DDR SDRAM controller */
 148 #define SDRAM_DDR_BCR_MASK 0xFFDEE001
 149
 150 static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
 151 {
 152     uint32_t bcr;
 153
 154     switch (ram_size) {
 155     case 4 * MiB:
 156         bcr = 0;
 157         break;
 158     case 8 * MiB:
 159         bcr = 0x20000;
 160         break;
 161     case 16 * MiB:
 162         bcr = 0x40000;
 163         break;
 164     case 32 * MiB:
 165         bcr = 0x60000;
 166         break;
 167     case 64 * MiB:
 168         bcr = 0x80000;
 169         break;
 170     case 128 * MiB:
 171         bcr = 0xA0000;
 172         break;
 173     case 256 * MiB:
 174         bcr = 0xC0000;
 175         break;
 176     default:
 177         qemu_log_mask(LOG_GUEST_ERROR,
 178                       "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
 179                       ram_size);
 180         return 0;
 181     }
 182     bcr |= ram_base & 0xFF800000;
 183     bcr |= 1;
 184
 185     return bcr;
 186 }
 187
 188 static inline hwaddr sdram_ddr_base(uint32_t bcr)
 189 {
 190     return bcr & 0xFF800000;
 191 }
 192
 193 static hwaddr sdram_ddr_size(uint32_t bcr)
 194 {
 195     int sh = (bcr >> 17) & 0x7;
 196
 197     if (sh == 7) {
 198         return -1;
 199     }
 200
 201     return (4 * MiB) << sh;
 202 }
 203
 204 static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
 205 {
 206     Ppc4xxSdramDdrState *s = opaque;
 207     uint32_t ret;
 208
 209     switch (dcrn) {
 210     case SDRAM0_CFGADDR:
 211         ret = s->addr;
 212         break;
 213     case SDRAM0_CFGDATA:
 214         switch (s->addr) {
 215         case 0x00: /* SDRAM_BESR0 */
 216             ret = s->besr0;
 217             break;
 218         case 0x08: /* SDRAM_BESR1 */
 219             ret = s->besr1;
 220             break;
 221         case 0x10: /* SDRAM_BEAR */
 222             ret = s->bear;
 223             break;
 224         case 0x20: /* SDRAM_CFG */
 225             ret = s->cfg;
 226             break;
 227         case 0x24: /* SDRAM_STATUS */
 228             ret = s->status;
 229             break;
 230         case 0x30: /* SDRAM_RTR */
 231             ret = s->rtr;
 232             break;
 233         case 0x34: /* SDRAM_PMIT */
 234             ret = s->pmit;
 235             break;
 236         case 0x40: /* SDRAM_B0CR */
 237             ret = s->bank[0].bcr;
 238             break;
 239         case 0x44: /* SDRAM_B1CR */
 240             ret = s->bank[1].bcr;
 241             break;
 242         case 0x48: /* SDRAM_B2CR */
 243             ret = s->bank[2].bcr;
 244             break;
 245         case 0x4C: /* SDRAM_B3CR */
 246             ret = s->bank[3].bcr;
 247             break;
 248         case 0x80: /* SDRAM_TR */
 249             ret = -1; /* ? */
 250             break;
 251         case 0x94: /* SDRAM_ECCCFG */
 252             ret = s->ecccfg;
 253             break;
 254         case 0x98: /* SDRAM_ECCESR */
 255             ret = s->eccesr;
 256             break;
 257         default: /* Error */
 258             ret = -1;
 259             break;
 260         }
 261         break;
 262     default:
 263         /* Avoid gcc warning */
 264         ret = 0;
 265         break;
 266     }
 267
 268     return ret;
 269 }
 270
 271 static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
 272 {
 273     Ppc4xxSdramDdrState *s = opaque;
 274     int i;
 275
 276     switch (dcrn) {
 277     case SDRAM0_CFGADDR:
 278         s->addr = val;
 279         break;
 280     case SDRAM0_CFGDATA:
 281         switch (s->addr) {
 282         case 0x00: /* SDRAM_BESR0 */
 283             s->besr0 &= ~val;
 284             break;
 285         case 0x08: /* SDRAM_BESR1 */
 286             s->besr1 &= ~val;
 287             break;
 288         case 0x10: /* SDRAM_BEAR */
 289             s->bear = val;
 290             break;
 291         case 0x20: /* SDRAM_CFG */
 292             val &= 0xFFE00000;
 293             if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
 294                 trace_ppc4xx_sdram_enable("enable");
 295                 /* validate all RAM mappings */
 296                 for (i = 0; i < s->nbanks; i++) {
 297                     if (s->bank[i].size) {
 298                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 299                                            s->bank[i].base, s->bank[i].size,
 300                                            1);
 301                     }
 302                 }
 303                 s->status &= ~0x80000000;
 304             } else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
 305                 trace_ppc4xx_sdram_enable("disable");
 306                 /* invalidate all RAM mappings */
 307                 for (i = 0; i < s->nbanks; i++) {
 308                     if (s->bank[i].size) {
 309                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 310                                            s->bank[i].base, s->bank[i].size,
 311                                            0);
 312                     }
 313                 }
 314                 s->status |= 0x80000000;
 315             }
 316             if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
 317                 s->status |= 0x40000000;
 318             } else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
 319                 s->status &= ~0x40000000;
 320             }
 321             s->cfg = val;
 322             break;
 323         case 0x24: /* SDRAM_STATUS */
 324             /* Read-only register */
 325             break;
 326         case 0x30: /* SDRAM_RTR */
 327             s->rtr = val & 0x3FF80000;
 328             break;
 329         case 0x34: /* SDRAM_PMIT */
 330             s->pmit = (val & 0xF8000000) | 0x07C00000;
 331             break;
 332         case 0x40: /* SDRAM_B0CR */
 333         case 0x44: /* SDRAM_B1CR */
 334         case 0x48: /* SDRAM_B2CR */
 335         case 0x4C: /* SDRAM_B3CR */
 336             i = (s->addr - 0x40) / 4;
 337             val &= SDRAM_DDR_BCR_MASK;
 338             if (s->bank[i].size) {
 339                 sdram_bank_set_bcr(&s->bank[i], val,
 340                                    sdram_ddr_base(val), sdram_ddr_size(val),
 341                                    s->cfg & 0x80000000);
 342             }
 343             break;
 344         case 0x80: /* SDRAM_TR */
 345             s->tr = val & 0x018FC01F;
 346             break;
 347         case 0x94: /* SDRAM_ECCCFG */
 348             s->ecccfg = val & 0x00F00000;
 349             break;
 350         case 0x98: /* SDRAM_ECCESR */
 351             val &= 0xFFF0F000;
 352             if (s->eccesr == 0 && val != 0) {
 353                 qemu_irq_raise(s->irq);
 354             } else if (s->eccesr != 0 && val == 0) {
 355                 qemu_irq_lower(s->irq);
 356             }
 357             s->eccesr = val;
 358             break;
 359         default: /* Error */
 360             break;
 361         }
 362         break;
 363     }
 364 }
 365
 366 static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
 367 {
 368     Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
 369
 370     s->addr = 0;
 371     s->bear = 0;
 372     s->besr0 = 0; /* No error */
 373     s->besr1 = 0; /* No error */
 374     s->cfg = 0;
 375     s->ecccfg = 0; /* No ECC */
 376     s->eccesr = 0; /* No error */
 377     s->pmit = 0x07C00000;
 378     s->rtr = 0x05F00000;
 379     s->tr = 0x00854009;
 380     /* We pre-initialize RAM banks */
 381     s->status = 0;
 382     s->cfg = 0x00800000;
 383 }
 384
 385 static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
 386 {
 387     Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
 388     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 389     const ram_addr_t valid_bank_sizes[] = {
 390         256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
 391     };
 392     int i;
 393
 394     if (s->nbanks < 1 || s->nbanks > 4) {
 395         error_setg(errp, "Invalid number of RAM banks");
 396         return;
 397     }
 398     if (!s->dram_mr) {
 399         error_setg(errp, "Missing dram memory region");
 400         return;
 401     }
 402     if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
 403                             valid_bank_sizes, errp)) {
 404         return;
 405     }
 406     for (i = 0; i < s->nbanks; i++) {
 407         if (s->bank[i].size) {
 408             s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
 409             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 410                                s->bank[i].base, s->bank[i].size, 0);
 411         } else {
 412             sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
 413         }
 414         trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),
 415                                 sdram_ddr_size(s->bank[i].bcr),
 416                                 s->bank[i].bcr);
 417     }
 418
 419     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 420
 421     ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
 422                         s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
 423     ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
 424                         s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
 425 }
 426
 427 static Property ppc4xx_sdram_ddr_props[] = {
 428     DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
 429                      MemoryRegion *),
 430     DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
 431     DEFINE_PROP_END_OF_LIST(),
 432 };
 433
 434 static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
 435 {
 436     DeviceClass *dc = DEVICE_CLASS(oc);
 437
 438     dc->realize = ppc4xx_sdram_ddr_realize;
 439     dc->reset = ppc4xx_sdram_ddr_reset;
 440     /* Reason: only works as function of a ppc4xx SoC */
 441     dc->user_creatable = false;
 442     device_class_set_props(dc, ppc4xx_sdram_ddr_props);
 443 }
 444
 445 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
 446 {
 447     sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
 448     sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
 449 }
 450
 451 /*****************************************************************************/
 452 /* DDR2 SDRAM controller */
 453 #define SDRAM_DDR2_BCR_MASK 0xffe0ffc1
 454
 455 enum {
 456     SDRAM_R0BAS = 0x40,
 457     SDRAM_R1BAS,
 458     SDRAM_R2BAS,
 459     SDRAM_R3BAS,
 460     SDRAM_CONF1HB = 0x45,
 461     SDRAM_PLBADDULL = 0x4a,
 462     SDRAM_CONF1LL = 0x4b,
 463     SDRAM_CONFPATHB = 0x4f,
 464     SDRAM_PLBADDUHB = 0x50,
 465 };
 466
 467 static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
 468 {
 469     uint32_t bcr;
 470
 471     switch (ram_size) {
 472     case 8 * MiB:
 473         bcr = 0xffc0;
 474         break;
 475     case 16 * MiB:
 476         bcr = 0xff80;
 477         break;
 478     case 32 * MiB:
 479         bcr = 0xff00;
 480         break;
 481     case 64 * MiB:
 482         bcr = 0xfe00;
 483         break;
 484     case 128 * MiB:
 485         bcr = 0xfc00;
 486         break;
 487     case 256 * MiB:
 488         bcr = 0xf800;
 489         break;
 490     case 512 * MiB:
 491         bcr = 0xf000;
 492         break;
 493     case 1 * GiB:
 494         bcr = 0xe000;
 495         break;
 496     case 2 * GiB:
 497         bcr = 0xc000;
 498         break;
 499     case 4 * GiB:
 500         bcr = 0x8000;
 501         break;
 502     default:
 503         error_report("invalid RAM size " HWADDR_FMT_plx, ram_size);
 504         return 0;
 505     }
 506     bcr |= ram_base >> 2 & 0xffe00000;
 507     bcr |= 1;
 508
 509     return bcr;
 510 }
 511
 512 static inline hwaddr sdram_ddr2_base(uint32_t bcr)
 513 {
 514     return (bcr & 0xffe00000) << 2;
 515 }
 516
 517 static hwaddr sdram_ddr2_size(uint32_t bcr)
 518 {
 519     int sh;
 520
 521     sh = 1024 - ((bcr >> 6) & 0x3ff);
 522     return 8 * MiB * sh;
 523 }
 524
 525 static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
 526 {
 527     Ppc4xxSdramDdr2State *s = opaque;
 528     uint32_t ret = 0;
 529
 530     switch (dcrn) {
 531     case SDRAM_R0BAS:
 532     case SDRAM_R1BAS:
 533     case SDRAM_R2BAS:
 534     case SDRAM_R3BAS:
 535         if (s->bank[dcrn - SDRAM_R0BAS].size) {
 536             ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
 537                                  s->bank[dcrn - SDRAM_R0BAS].size);
 538         }
 539         break;
 540     case SDRAM_CONF1HB:
 541     case SDRAM_CONF1LL:
 542     case SDRAM_CONFPATHB:
 543     case SDRAM_PLBADDULL:
 544     case SDRAM_PLBADDUHB:
 545         break;
 546     case SDRAM0_CFGADDR:
 547         ret = s->addr;
 548         break;
 549     case SDRAM0_CFGDATA:
 550         switch (s->addr) {
 551         case 0x14: /* SDRAM_MCSTAT (405EX) */
 552         case 0x1F:
 553             ret = 0x80000000;
 554             break;
 555         case 0x21: /* SDRAM_MCOPT2 */
 556             ret = s->mcopt2;
 557             break;
 558         case 0x40: /* SDRAM_MB0CF */
 559             ret = 0x00008001;
 560             break;
 561         case 0x7A: /* SDRAM_DLCR */
 562             ret = 0x02000000;
 563             break;
 564         case 0xE1: /* SDR0_DDR0 */
 565             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 566             break;
 567         default:
 568             break;
 569         }
 570         break;
 571     default:
 572         break;
 573     }
 574
 575     return ret;
 576 }
 577
 578 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
 579
 580 static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
 581 {
 582     Ppc4xxSdramDdr2State *s = opaque;
 583     int i;
 584
 585     switch (dcrn) {
 586     case SDRAM_R0BAS:
 587     case SDRAM_R1BAS:
 588     case SDRAM_R2BAS:
 589     case SDRAM_R3BAS:
 590     case SDRAM_CONF1HB:
 591     case SDRAM_CONF1LL:
 592     case SDRAM_CONFPATHB:
 593     case SDRAM_PLBADDULL:
 594     case SDRAM_PLBADDUHB:
 595         break;
 596     case SDRAM0_CFGADDR:
 597         s->addr = val;
 598         break;
 599     case SDRAM0_CFGDATA:
 600         switch (s->addr) {
 601         case 0x00: /* B0CR */
 602             break;
 603         case 0x21: /* SDRAM_MCOPT2 */
 604             if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 605                 (val & SDRAM_DDR2_MCOPT2_DCEN)) {
 606                 trace_ppc4xx_sdram_enable("enable");
 607                 /* validate all RAM mappings */
 608                 for (i = 0; i < s->nbanks; i++) {
 609                     if (s->bank[i].size) {
 610                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 611                                            s->bank[i].base, s->bank[i].size,
 612                                            1);
 613                     }
 614                 }
 615                 s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
 616             } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 617                        !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
 618                 trace_ppc4xx_sdram_enable("disable");
 619                 /* invalidate all RAM mappings */
 620                 for (i = 0; i < s->nbanks; i++) {
 621                     if (s->bank[i].size) {
 622                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 623                                            s->bank[i].base, s->bank[i].size,
 624                                            0);
 625                     }
 626                 }
 627                 s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
 628             }
 629             break;
 630         default:
 631             break;
 632         }
 633         break;
 634     default:
 635         break;
 636     }
 637 }
 638
 639 static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
 640 {
 641     Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
 642
 643     s->addr = 0;
 644     s->mcopt2 = 0;
 645 }
 646
 647 static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
 648 {
 649     Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
 650     Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
 651     /*
 652      * SoC also has 4 GiB but that causes problem with 32 bit
 653      * builds (4*GiB overflows the 32 bit ram_addr_t).
 654      */
 655     const ram_addr_t valid_bank_sizes[] = {
 656         2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
 657         64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
 658     };
 659     int i;
 660
 661     if (s->nbanks < 1 || s->nbanks > 4) {
 662         error_setg(errp, "Invalid number of RAM banks");
 663         return;
 664     }
 665     if (!s->dram_mr) {
 666         error_setg(errp, "Missing dram memory region");
 667         return;
 668     }
 669     if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
 670                             valid_bank_sizes, errp)) {
 671         return;
 672     }
 673     for (i = 0; i < s->nbanks; i++) {
 674         if (s->bank[i].size) {
 675             s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
 676             s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;
 677             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
 678                                s->bank[i].base, s->bank[i].size, 0);
 679         } else {
 680             sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
 681         }
 682         trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),
 683                                 sdram_ddr2_size(s->bank[i].bcr),
 684                                 s->bank[i].bcr);
 685     }
 686
 687     ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
 688                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 689     ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
 690                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 691
 692     ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
 693                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 694     ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
 695                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 696     ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
 697                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 698     ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
 699                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 700     ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
 701                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 702     ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
 703                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 704     ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
 705                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 706     ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
 707                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 708     ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
 709                         s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
 710 }
 711
 712 static Property ppc4xx_sdram_ddr2_props[] = {
 713     DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
 714                      MemoryRegion *),
 715     DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
 716     DEFINE_PROP_END_OF_LIST(),
 717 };
 718
 719 static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
 720 {
 721     DeviceClass *dc = DEVICE_CLASS(oc);
 722
 723     dc->realize = ppc4xx_sdram_ddr2_realize;
 724     dc->reset = ppc4xx_sdram_ddr2_reset;
 725     /* Reason: only works as function of a ppc4xx SoC */
 726     dc->user_creatable = false;
 727     device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
 728 }
 729
 730 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
 731 {
 732     sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
 733     sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
 734 }
 735
 736 static const TypeInfo ppc4xx_sdram_types[] = {
 737     {
 738         .name           = TYPE_PPC4xx_SDRAM_DDR,
 739         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 740         .instance_size  = sizeof(Ppc4xxSdramDdrState),
 741         .class_init     = ppc4xx_sdram_ddr_class_init,
 742     }, {
 743         .name           = TYPE_PPC4xx_SDRAM_DDR2,
 744         .parent         = TYPE_PPC4xx_DCR_DEVICE,
 745         .instance_size  = sizeof(Ppc4xxSdramDdr2State),
 746         .class_init     = ppc4xx_sdram_ddr2_class_init,
 747     }
 748 };
 749
 750 DEFINE_TYPES(ppc4xx_sdram_types)