hw/ppc/pnv_xscom.c

   1 /*
   2  * QEMU PowerPC PowerNV XSCOM bus
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "qemu/module.h"
  23 #include "sysemu/hw_accel.h"
  24 #include "target/ppc/cpu.h"
  25 #include "hw/sysbus.h"
  26
  27 #include "hw/ppc/fdt.h"
  28 #include "hw/ppc/pnv.h"
  29 #include "hw/ppc/pnv_chip.h"
  30 #include "hw/ppc/pnv_xscom.h"
  31
  32 #include <libfdt.h>
  33
  34 /* PRD registers */
  35 #define PRD_P8_IPOLL_REG_MASK           0x01020013
  36 #define PRD_P8_IPOLL_REG_STATUS         0x01020014
  37 #define PRD_P9_IPOLL_REG_MASK           0x000F0033
  38 #define PRD_P9_IPOLL_REG_STATUS         0x000F0034
  39
  40 static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
  41 {
  42     /*
  43      * TODO: When the read/write comes from the monitor, NULL is
  44      * passed for the cpu, and no CPU completion is generated.
  45      */
  46     if (cs) {
  47         PowerPCCPU *cpu = POWERPC_CPU(cs);
  48         CPUPPCState *env = &cpu->env;
  49
  50         /*
  51          * TODO: Need a CPU helper to set HMER, also handle generation
  52          * of HMIs
  53          */
  54         cpu_synchronize_state(cs);
  55         env->spr[SPR_HMER] |= hmer_bits;
  56     }
  57 }
  58
  59 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
  60 {
  61     return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr);
  62 }
  63
  64 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
  65 {
  66     switch (pcba) {
  67     case 0xf000f:
  68         return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id;
  69     case 0x18002:       /* ECID2 */
  70         return 0;
  71
  72     case 0x1010c00:     /* PIBAM FIR */
  73     case 0x1010c03:     /* PIBAM FIR MASK */
  74
  75         /* PRD registers */
  76     case PRD_P8_IPOLL_REG_MASK:
  77     case PRD_P8_IPOLL_REG_STATUS:
  78     case PRD_P9_IPOLL_REG_MASK:
  79     case PRD_P9_IPOLL_REG_STATUS:
  80
  81         /* P9 xscom reset */
  82     case 0x0090018:     /* Receive status reg */
  83     case 0x0090012:     /* log register */
  84     case 0x0090013:     /* error register */
  85
  86         /* P8 xscom reset */
  87     case 0x2020007:     /* ADU stuff, log register */
  88     case 0x2020009:     /* ADU stuff, error register */
  89     case 0x202000f:     /* ADU stuff, receive status register*/
  90         return 0;
  91     case 0x2013f01:     /* PBA stuff */
  92     case 0x2013f05:     /* PBA stuff */
  93         return 0;
  94     case 0x2013028:     /* CAPP stuff */
  95     case 0x201302a:     /* CAPP stuff */
  96     case 0x2013801:     /* CAPP stuff */
  97     case 0x2013802:     /* CAPP stuff */
  98
  99         /* P9 CAPP regs */
 100     case 0x2010841:
 101     case 0x2010842:
 102     case 0x201082a:
 103     case 0x2010828:
 104     case 0x4010841:
 105     case 0x4010842:
 106     case 0x401082a:
 107     case 0x4010828:
 108         return 0;
 109     default:
 110         return -1;
 111     }
 112 }
 113
 114 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val)
 115 {
 116     /* We ignore writes to these */
 117     switch (pcba) {
 118     case 0xf000f:       /* chip id is RO */
 119     case 0x1010c00:     /* PIBAM FIR */
 120     case 0x1010c01:     /* PIBAM FIR */
 121     case 0x1010c02:     /* PIBAM FIR */
 122     case 0x1010c03:     /* PIBAM FIR MASK */
 123     case 0x1010c04:     /* PIBAM FIR MASK */
 124     case 0x1010c05:     /* PIBAM FIR MASK */
 125         /* P9 xscom reset */
 126     case 0x0090018:     /* Receive status reg */
 127     case 0x0090012:     /* log register */
 128     case 0x0090013:     /* error register */
 129
 130         /* P8 xscom reset */
 131     case 0x2020007:     /* ADU stuff, log register */
 132     case 0x2020009:     /* ADU stuff, error register */
 133     case 0x202000f:     /* ADU stuff, receive status register*/
 134
 135     case 0x2013028:     /* CAPP stuff */
 136     case 0x201302a:     /* CAPP stuff */
 137     case 0x2013801:     /* CAPP stuff */
 138     case 0x2013802:     /* CAPP stuff */
 139
 140         /* P9 CAPP regs */
 141     case 0x2010841:
 142     case 0x2010842:
 143     case 0x201082a:
 144     case 0x2010828:
 145     case 0x4010841:
 146     case 0x4010842:
 147     case 0x401082a:
 148     case 0x4010828:
 149
 150         /* P8 PRD registers */
 151     case PRD_P8_IPOLL_REG_MASK:
 152     case PRD_P8_IPOLL_REG_STATUS:
 153     case PRD_P9_IPOLL_REG_MASK:
 154     case PRD_P9_IPOLL_REG_STATUS:
 155         return true;
 156     default:
 157         return false;
 158     }
 159 }
 160
 161 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width)
 162 {
 163     PnvChip *chip = opaque;
 164     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 165     uint64_t val = 0;
 166     MemTxResult result;
 167
 168     /* Handle some SCOMs here before dispatch */
 169     val = xscom_read_default(chip, pcba);
 170     if (val != -1) {
 171         goto complete;
 172     }
 173
 174     val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3,
 175                             MEMTXATTRS_UNSPECIFIED, &result);
 176     if (result != MEMTX_OK) {
 177         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%"
 178                       HWADDR_PRIx " pcba=0x%08x\n", addr, pcba);
 179         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 180         return 0;
 181     }
 182
 183 complete:
 184     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 185     return val;
 186 }
 187
 188 static void xscom_write(void *opaque, hwaddr addr, uint64_t val,
 189                         unsigned width)
 190 {
 191     PnvChip *chip = opaque;
 192     uint32_t pcba = pnv_xscom_pcba(chip, addr);
 193     MemTxResult result;
 194
 195     /* Handle some SCOMs here before dispatch */
 196     if (xscom_write_default(chip, pcba, val)) {
 197         goto complete;
 198     }
 199
 200     address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val,
 201                       MEMTXATTRS_UNSPECIFIED, &result);
 202     if (result != MEMTX_OK) {
 203         qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%"
 204                       HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n",
 205                       addr, pcba, val);
 206         xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE);
 207         return;
 208     }
 209
 210 complete:
 211     xscom_complete(current_cpu, HMER_XSCOM_DONE);
 212 }
 213
 214 const MemoryRegionOps pnv_xscom_ops = {
 215     .read = xscom_read,
 216     .write = xscom_write,
 217     .valid.min_access_size = 8,
 218     .valid.max_access_size = 8,
 219     .impl.min_access_size = 8,
 220     .impl.max_access_size = 8,
 221     .endianness = DEVICE_BIG_ENDIAN,
 222 };
 223
 224 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp)
 225 {
 226     SysBusDevice *sbd = SYS_BUS_DEVICE(chip);
 227     char *name;
 228
 229     name = g_strdup_printf("xscom-%x", chip->chip_id);
 230     memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops,
 231                           chip, name, size);
 232     sysbus_init_mmio(sbd, &chip->xscom_mmio);
 233
 234     memory_region_init(&chip->xscom, OBJECT(chip), name, size);
 235     address_space_init(&chip->xscom_as, &chip->xscom, name);
 236     g_free(name);
 237 }
 238
 239 static const TypeInfo pnv_xscom_interface_info = {
 240     .name = TYPE_PNV_XSCOM_INTERFACE,
 241     .parent = TYPE_INTERFACE,
 242     .class_size = sizeof(PnvXScomInterfaceClass),
 243 };
 244
 245 static void pnv_xscom_register_types(void)
 246 {
 247     type_register_static(&pnv_xscom_interface_info);
 248 }
 249
 250 type_init(pnv_xscom_register_types)
 251
 252 typedef struct ForeachPopulateArgs {
 253     void *fdt;
 254     int xscom_offset;
 255 } ForeachPopulateArgs;
 256
 257 static int xscom_dt_child(Object *child, void *opaque)
 258 {
 259     if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) {
 260         ForeachPopulateArgs *args = opaque;
 261         PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child);
 262         PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd);
 263
 264         /*
 265          * Only "realized" devices should be configured in the DT
 266          */
 267         if (xc->dt_xscom && DEVICE(child)->realized) {
 268             _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset)));
 269         }
 270     }
 271     return 0;
 272 }
 273
 274 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
 275                  uint64_t xscom_base, uint64_t xscom_size,
 276                  const char *compat, int compat_size)
 277 {
 278     uint64_t reg[] = { xscom_base, xscom_size };
 279     int xscom_offset;
 280     ForeachPopulateArgs args;
 281     char *name;
 282
 283     name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0]));
 284     xscom_offset = fdt_add_subnode(fdt, root_offset, name);
 285     _FDT(xscom_offset);
 286     g_free(name);
 287     _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id)));
 288     /*
 289      * On P10, the xscom bus id has been deprecated and the chip id is
 290      * calculated from the "Primary topology table index". See skiboot.
 291      */
 292     _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,primary-topology-index",
 293                            chip->chip_id)));
 294     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1)));
 295     _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1)));
 296     _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg))));
 297     _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size)));
 298     _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0)));
 299     if (chip->chip_id == 0) {
 300         _FDT((fdt_setprop(fdt, xscom_offset, "primary", NULL, 0)));
 301     }
 302
 303     args.fdt = fdt;
 304     args.xscom_offset = xscom_offset;
 305
 306     /*
 307      * Loop on the whole object hierarchy to catch all
 308      * PnvXScomInterface objects which can lie a bit deeper than the
 309      * first layer.
 310      */
 311     object_child_foreach_recursive(OBJECT(chip), xscom_dt_child, &args);
 312     return 0;
 313 }
 314
 315 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr)
 316 {
 317     memory_region_add_subregion(&chip->xscom, offset << 3, mr);
 318 }
 319
 320 void pnv_xscom_region_init(MemoryRegion *mr,
 321                            Object *owner,
 322                            const MemoryRegionOps *ops,
 323                            void *opaque,
 324                            const char *name,
 325                            uint64_t size)
 326 {
 327     memory_region_init_io(mr, owner, ops, opaque, name, size << 3);
 328 }