hw/core/cpu-common.c

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/core/cpu.h"
  24 #include "sysemu/hw_accel.h"
  25 #include "qemu/notify.h"
  26 #include "qemu/log.h"
  27 #include "qemu/main-loop.h"
  28 #include "exec/log.h"
  29 #include "exec/cpu-common.h"
  30 #include "qemu/error-report.h"
  31 #include "qemu/qemu-print.h"
  32 #include "sysemu/tcg.h"
  33 #include "hw/boards.h"
  34 #include "hw/qdev-properties.h"
  35 #include "trace/trace-root.h"
  36 #include "qemu/plugin.h"
  37
  38 CPUState *cpu_by_arch_id(int64_t id)
  39 {
  40     CPUState *cpu;
  41
  42     CPU_FOREACH(cpu) {
  43         CPUClass *cc = CPU_GET_CLASS(cpu);
  44
  45         if (cc->get_arch_id(cpu) == id) {
  46             return cpu;
  47         }
  48     }
  49     return NULL;
  50 }
  51
  52 bool cpu_exists(int64_t id)
  53 {
  54     return !!cpu_by_arch_id(id);
  55 }
  56
  57 CPUState *cpu_create(const char *typename)
  58 {
  59     Error *err = NULL;
  60     CPUState *cpu = CPU(object_new(typename));
  61     if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
  62         error_report_err(err);
  63         object_unref(OBJECT(cpu));
  64         exit(EXIT_FAILURE);
  65     }
  66     return cpu;
  67 }
  68
  69 /* Resetting the IRQ comes from across the code base so we take the
  70  * BQL here if we need to.  cpu_interrupt assumes it is held.*/
  71 void cpu_reset_interrupt(CPUState *cpu, int mask)
  72 {
  73     bool need_lock = !qemu_mutex_iothread_locked();
  74
  75     if (need_lock) {
  76         qemu_mutex_lock_iothread();
  77     }
  78     cpu->interrupt_request &= ~mask;
  79     if (need_lock) {
  80         qemu_mutex_unlock_iothread();
  81     }
  82 }
  83
  84 void cpu_exit(CPUState *cpu)
  85 {
  86     qatomic_set(&cpu->exit_request, 1);
  87     /* Ensure cpu_exec will see the exit request after TCG has exited.  */
  88     smp_wmb();
  89     qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
  90 }
  91
  92 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
  93 {
  94     return 0;
  95 }
  96
  97 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
  98 {
  99     return 0;
 100 }
 101
 102 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
 103 {
 104     CPUClass *cc = CPU_GET_CLASS(cpu);
 105
 106     if (cc->dump_state) {
 107         cpu_synchronize_state(cpu);
 108         cc->dump_state(cpu, f, flags);
 109     }
 110 }
 111
 112 void cpu_reset(CPUState *cpu)
 113 {
 114     device_cold_reset(DEVICE(cpu));
 115
 116     trace_guest_cpu_reset(cpu);
 117 }
 118
 119 static void cpu_common_reset_hold(Object *obj)
 120 {
 121     CPUState *cpu = CPU(obj);
 122     CPUClass *cc = CPU_GET_CLASS(cpu);
 123
 124     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
 125         qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
 126         log_cpu_state(cpu, cc->reset_dump_flags);
 127     }
 128
 129     cpu->interrupt_request = 0;
 130     cpu->halted = cpu->start_powered_off;
 131     cpu->mem_io_pc = 0;
 132     cpu->icount_extra = 0;
 133     qatomic_set(&cpu->icount_decr_ptr->u32, 0);
 134     cpu->can_do_io = 1;
 135     cpu->exception_index = -1;
 136     cpu->crash_occurred = false;
 137     cpu->cflags_next_tb = -1;
 138
 139     if (tcg_enabled()) {
 140         tcg_flush_jmp_cache(cpu);
 141         tcg_flush_softmmu_tlb(cpu);
 142     }
 143 }
 144
 145 static bool cpu_common_has_work(CPUState *cs)
 146 {
 147     return false;
 148 }
 149
 150 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
 151 {
 152     CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
 153
 154     assert(cpu_model && cc->class_by_name);
 155     return cc->class_by_name(cpu_model);
 156 }
 157
 158 static void cpu_common_parse_features(const char *typename, char *features,
 159                                       Error **errp)
 160 {
 161     char *val;
 162     static bool cpu_globals_initialized;
 163     /* Single "key=value" string being parsed */
 164     char *featurestr = features ? strtok(features, ",") : NULL;
 165
 166     /* should be called only once, catch invalid users */
 167     assert(!cpu_globals_initialized);
 168     cpu_globals_initialized = true;
 169
 170     while (featurestr) {
 171         val = strchr(featurestr, '=');
 172         if (val) {
 173             GlobalProperty *prop = g_new0(typeof(*prop), 1);
 174             *val = 0;
 175             val++;
 176             prop->driver = typename;
 177             prop->property = g_strdup(featurestr);
 178             prop->value = g_strdup(val);
 179             qdev_prop_register_global(prop);
 180         } else {
 181             error_setg(errp, "Expected key=value format, found %s.",
 182                        featurestr);
 183             return;
 184         }
 185         featurestr = strtok(NULL, ",");
 186     }
 187 }
 188
 189 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
 190 {
 191     CPUState *cpu = CPU(dev);
 192     Object *machine = qdev_get_machine();
 193
 194     /* qdev_get_machine() can return something that's not TYPE_MACHINE
 195      * if this is one of the user-only emulators; in that case there's
 196      * no need to check the ignore_memory_transaction_failures board flag.
 197      */
 198     if (object_dynamic_cast(machine, TYPE_MACHINE)) {
 199         ObjectClass *oc = object_get_class(machine);
 200         MachineClass *mc = MACHINE_CLASS(oc);
 201
 202         if (mc) {
 203             cpu->ignore_memory_transaction_failures =
 204                 mc->ignore_memory_transaction_failures;
 205         }
 206     }
 207
 208     if (dev->hotplugged) {
 209         cpu_synchronize_post_init(cpu);
 210         cpu_resume(cpu);
 211     }
 212
 213     /* NOTE: latest generic point where the cpu is fully realized */
 214     trace_init_vcpu(cpu);
 215 }
 216
 217 static void cpu_common_unrealizefn(DeviceState *dev)
 218 {
 219     CPUState *cpu = CPU(dev);
 220
 221     /* NOTE: latest generic point before the cpu is fully unrealized */
 222     trace_fini_vcpu(cpu);
 223     cpu_exec_unrealizefn(cpu);
 224 }
 225
 226 static void cpu_common_initfn(Object *obj)
 227 {
 228     CPUState *cpu = CPU(obj);
 229     CPUClass *cc = CPU_GET_CLASS(obj);
 230
 231     cpu->cpu_index = UNASSIGNED_CPU_INDEX;
 232     cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
 233     cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
 234     /* *-user doesn't have configurable SMP topology */
 235     /* the default value is changed by qemu_init_vcpu() for softmmu */
 236     cpu->nr_cores = 1;
 237     cpu->nr_threads = 1;
 238     cpu->cflags_next_tb = -1;
 239
 240     qemu_mutex_init(&cpu->work_mutex);
 241     qemu_lockcnt_init(&cpu->in_ioctl_lock);
 242     QSIMPLEQ_INIT(&cpu->work_list);
 243     QTAILQ_INIT(&cpu->breakpoints);
 244     QTAILQ_INIT(&cpu->watchpoints);
 245
 246     cpu_exec_initfn(cpu);
 247 }
 248
 249 static void cpu_common_finalize(Object *obj)
 250 {
 251     CPUState *cpu = CPU(obj);
 252
 253     qemu_lockcnt_destroy(&cpu->in_ioctl_lock);
 254     qemu_mutex_destroy(&cpu->work_mutex);
 255 }
 256
 257 static int64_t cpu_common_get_arch_id(CPUState *cpu)
 258 {
 259     return cpu->cpu_index;
 260 }
 261
 262 static void cpu_class_init(ObjectClass *klass, void *data)
 263 {
 264     DeviceClass *dc = DEVICE_CLASS(klass);
 265     ResettableClass *rc = RESETTABLE_CLASS(klass);
 266     CPUClass *k = CPU_CLASS(klass);
 267
 268     k->parse_features = cpu_common_parse_features;
 269     k->get_arch_id = cpu_common_get_arch_id;
 270     k->has_work = cpu_common_has_work;
 271     k->gdb_read_register = cpu_common_gdb_read_register;
 272     k->gdb_write_register = cpu_common_gdb_write_register;
 273     set_bit(DEVICE_CATEGORY_CPU, dc->categories);
 274     dc->realize = cpu_common_realizefn;
 275     dc->unrealize = cpu_common_unrealizefn;
 276     rc->phases.hold = cpu_common_reset_hold;
 277     cpu_class_init_props(dc);
 278     /*
 279      * Reason: CPUs still need special care by board code: wiring up
 280      * IRQs, adding reset handlers, halting non-first CPUs, ...
 281      */
 282     dc->user_creatable = false;
 283 }
 284
 285 static const TypeInfo cpu_type_info = {
 286     .name = TYPE_CPU,
 287     .parent = TYPE_DEVICE,
 288     .instance_size = sizeof(CPUState),
 289     .instance_init = cpu_common_initfn,
 290     .instance_finalize = cpu_common_finalize,
 291     .abstract = true,
 292     .class_size = sizeof(CPUClass),
 293     .class_init = cpu_class_init,
 294 };
 295
 296 static void cpu_register_types(void)
 297 {
 298     type_register_static(&cpu_type_info);
 299 }
 300
 301 type_init(cpu_register_types)