4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
8 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
15 #include "hw/timer/imx_gpt.h"
16 #include "hw/misc/imx_ccm.h"
17 #include "qemu/main-loop.h"
20 #define DEBUG_IMX_GPT 0
23 #define DPRINTF(fmt, args...) \
25 if (DEBUG_IMX_GPT) { \
26 fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
31 static char const *imx_gpt_reg_name(uint32_t reg
)
59 static const VMStateDescription vmstate_imx_timer_gpt
= {
62 .minimum_version_id
= 3,
63 .fields
= (VMStateField
[]) {
64 VMSTATE_UINT32(cr
, IMXGPTState
),
65 VMSTATE_UINT32(pr
, IMXGPTState
),
66 VMSTATE_UINT32(sr
, IMXGPTState
),
67 VMSTATE_UINT32(ir
, IMXGPTState
),
68 VMSTATE_UINT32(ocr1
, IMXGPTState
),
69 VMSTATE_UINT32(ocr2
, IMXGPTState
),
70 VMSTATE_UINT32(ocr3
, IMXGPTState
),
71 VMSTATE_UINT32(icr1
, IMXGPTState
),
72 VMSTATE_UINT32(icr2
, IMXGPTState
),
73 VMSTATE_UINT32(cnt
, IMXGPTState
),
74 VMSTATE_UINT32(next_timeout
, IMXGPTState
),
75 VMSTATE_UINT32(next_int
, IMXGPTState
),
76 VMSTATE_UINT32(freq
, IMXGPTState
),
77 VMSTATE_PTIMER(timer
, IMXGPTState
),
82 static const IMXClk imx_gpt_clocks
[] = {
83 NOCLK
, /* 000 No clock source */
84 CLK_IPG
, /* 001 ipg_clk, 532MHz*/
85 CLK_IPG
, /* 010 ipg_clk_highfreq */
86 NOCLK
, /* 011 not defined */
87 CLK_32k
, /* 100 ipg_clk_32k */
88 NOCLK
, /* 101 not defined */
89 NOCLK
, /* 110 not defined */
90 NOCLK
, /* 111 not defined */
93 static void imx_gpt_set_freq(IMXGPTState
*s
)
95 uint32_t clksrc
= extract32(s
->cr
, GPT_CR_CLKSRC_SHIFT
, 3);
97 s
->freq
= imx_ccm_get_clock_frequency(s
->ccm
,
98 imx_gpt_clocks
[clksrc
]) / (1 + s
->pr
);
100 DPRINTF("Setting clksrc %d to frequency %d\n", clksrc
, s
->freq
);
103 ptimer_set_freq(s
->timer
, s
->freq
);
107 static void imx_gpt_update_int(IMXGPTState
*s
)
109 if ((s
->sr
& s
->ir
) && (s
->cr
& GPT_CR_EN
)) {
110 qemu_irq_raise(s
->irq
);
112 qemu_irq_lower(s
->irq
);
116 static uint32_t imx_gpt_update_count(IMXGPTState
*s
)
118 s
->cnt
= s
->next_timeout
- (uint32_t)ptimer_get_count(s
->timer
);
123 static inline uint32_t imx_gpt_find_limit(uint32_t count
, uint32_t reg
,
126 if ((count
< reg
) && (timeout
> reg
)) {
133 static void imx_gpt_compute_next_timeout(IMXGPTState
*s
, bool event
)
135 uint32_t timeout
= GPT_TIMER_MAX
;
139 if (!(s
->cr
& GPT_CR_EN
)) {
140 /* if not enabled just return */
145 /* This is a timer event */
147 if ((s
->cr
& GPT_CR_FRR
) && (s
->next_timeout
!= GPT_TIMER_MAX
)) {
149 * if we are in free running mode and we have not reached
150 * the GPT_TIMER_MAX limit, then update the count
152 count
= imx_gpt_update_count(s
);
155 /* not a timer event, then just update the count */
157 count
= imx_gpt_update_count(s
);
160 /* now, find the next timeout related to count */
162 if (s
->ir
& GPT_IR_OF1IE
) {
163 timeout
= imx_gpt_find_limit(count
, s
->ocr1
, timeout
);
165 if (s
->ir
& GPT_IR_OF2IE
) {
166 timeout
= imx_gpt_find_limit(count
, s
->ocr2
, timeout
);
168 if (s
->ir
& GPT_IR_OF3IE
) {
169 timeout
= imx_gpt_find_limit(count
, s
->ocr3
, timeout
);
172 /* find the next set of interrupts to raise for next timer event */
175 if ((s
->ir
& GPT_IR_OF1IE
) && (timeout
== s
->ocr1
)) {
176 s
->next_int
|= GPT_SR_OF1
;
178 if ((s
->ir
& GPT_IR_OF2IE
) && (timeout
== s
->ocr2
)) {
179 s
->next_int
|= GPT_SR_OF2
;
181 if ((s
->ir
& GPT_IR_OF3IE
) && (timeout
== s
->ocr3
)) {
182 s
->next_int
|= GPT_SR_OF3
;
184 if ((s
->ir
& GPT_IR_ROVIE
) && (timeout
== GPT_TIMER_MAX
)) {
185 s
->next_int
|= GPT_SR_ROV
;
188 /* the new range to count down from */
189 limit
= timeout
- imx_gpt_update_count(s
);
193 * if we reach here, then QEMU is running too slow and we pass the
194 * timeout limit while computing it. Let's deliver the interrupt
195 * and compute a new limit.
197 s
->sr
|= s
->next_int
;
199 imx_gpt_compute_next_timeout(s
, event
);
201 imx_gpt_update_int(s
);
203 /* New timeout value */
204 s
->next_timeout
= timeout
;
206 /* reset the limit to the computed range */
207 ptimer_set_limit(s
->timer
, limit
, 1);
211 static uint64_t imx_gpt_read(void *opaque
, hwaddr offset
, unsigned size
)
213 IMXGPTState
*s
= IMX_GPT(opaque
);
214 uint32_t reg_value
= 0;
216 switch (offset
>> 2) {
217 case 0: /* Control Register */
221 case 1: /* prescaler */
225 case 2: /* Status Register */
229 case 3: /* Interrupt Register */
233 case 4: /* Output Compare Register 1 */
237 case 5: /* Output Compare Register 2 */
241 case 6: /* Output Compare Register 3 */
245 case 7: /* input Capture Register 1 */
246 qemu_log_mask(LOG_UNIMP
, "[%s]%s: icr1 feature is not implemented\n",
247 TYPE_IMX_GPT
, __func__
);
251 case 8: /* input Capture Register 2 */
252 qemu_log_mask(LOG_UNIMP
, "[%s]%s: icr2 feature is not implemented\n",
253 TYPE_IMX_GPT
, __func__
);
258 imx_gpt_update_count(s
);
263 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
264 HWADDR_PRIx
"\n", TYPE_IMX_GPT
, __func__
, offset
);
268 DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset
>> 2), reg_value
);
273 static void imx_gpt_reset(DeviceState
*dev
)
275 IMXGPTState
*s
= IMX_GPT(dev
);
278 ptimer_stop(s
->timer
);
281 * Soft reset doesn't touch some bits; hard reset clears them
283 s
->cr
&= ~(GPT_CR_EN
|GPT_CR_ENMOD
|GPT_CR_STOPEN
|GPT_CR_DOZEN
|
284 GPT_CR_WAITEN
|GPT_CR_DBGEN
);
289 s
->ocr1
= GPT_TIMER_MAX
;
290 s
->ocr2
= GPT_TIMER_MAX
;
291 s
->ocr3
= GPT_TIMER_MAX
;
295 s
->next_timeout
= GPT_TIMER_MAX
;
298 /* compute new freq */
301 /* reset the limit to GPT_TIMER_MAX */
302 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
304 /* if the timer is still enabled, restart it */
305 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
306 ptimer_run(s
->timer
, 1);
310 static void imx_gpt_write(void *opaque
, hwaddr offset
, uint64_t value
,
313 IMXGPTState
*s
= IMX_GPT(opaque
);
316 DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset
>> 2),
319 switch (offset
>> 2) {
322 s
->cr
= value
& ~0x7c14;
323 if (s
->cr
& GPT_CR_SWR
) { /* force reset */
324 /* handle the reset */
325 imx_gpt_reset(DEVICE(s
));
327 /* set our freq, as the source might have changed */
330 if ((oldreg
^ s
->cr
) & GPT_CR_EN
) {
331 if (s
->cr
& GPT_CR_EN
) {
332 if (s
->cr
& GPT_CR_ENMOD
) {
333 s
->next_timeout
= GPT_TIMER_MAX
;
334 ptimer_set_count(s
->timer
, GPT_TIMER_MAX
);
335 imx_gpt_compute_next_timeout(s
, false);
337 ptimer_run(s
->timer
, 1);
340 ptimer_stop(s
->timer
);
346 case 1: /* Prescaler */
347 s
->pr
= value
& 0xfff;
352 s
->sr
&= ~(value
& 0x3f);
353 imx_gpt_update_int(s
);
356 case 3: /* IR -- interrupt register */
357 s
->ir
= value
& 0x3f;
358 imx_gpt_update_int(s
);
360 imx_gpt_compute_next_timeout(s
, false);
364 case 4: /* OCR1 -- output compare register */
367 /* In non-freerun mode, reset count when this register is written */
368 if (!(s
->cr
& GPT_CR_FRR
)) {
369 s
->next_timeout
= GPT_TIMER_MAX
;
370 ptimer_set_limit(s
->timer
, GPT_TIMER_MAX
, 1);
373 /* compute the new timeout */
374 imx_gpt_compute_next_timeout(s
, false);
378 case 5: /* OCR2 -- output compare register */
381 /* compute the new timeout */
382 imx_gpt_compute_next_timeout(s
, false);
386 case 6: /* OCR3 -- output compare register */
389 /* compute the new timeout */
390 imx_gpt_compute_next_timeout(s
, false);
395 qemu_log_mask(LOG_GUEST_ERROR
, "[%s]%s: Bad register at offset 0x%"
396 HWADDR_PRIx
"\n", TYPE_IMX_GPT
, __func__
, offset
);
401 static void imx_gpt_timeout(void *opaque
)
403 IMXGPTState
*s
= IMX_GPT(opaque
);
407 s
->sr
|= s
->next_int
;
410 imx_gpt_compute_next_timeout(s
, true);
412 imx_gpt_update_int(s
);
414 if (s
->freq
&& (s
->cr
& GPT_CR_EN
)) {
415 ptimer_run(s
->timer
, 1);
419 static const MemoryRegionOps imx_gpt_ops
= {
420 .read
= imx_gpt_read
,
421 .write
= imx_gpt_write
,
422 .endianness
= DEVICE_NATIVE_ENDIAN
,
426 static void imx_gpt_realize(DeviceState
*dev
, Error
**errp
)
428 IMXGPTState
*s
= IMX_GPT(dev
);
429 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
432 sysbus_init_irq(sbd
, &s
->irq
);
433 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_gpt_ops
, s
, TYPE_IMX_GPT
,
435 sysbus_init_mmio(sbd
, &s
->iomem
);
437 bh
= qemu_bh_new(imx_gpt_timeout
, s
);
438 s
->timer
= ptimer_init(bh
);
441 static void imx_gpt_class_init(ObjectClass
*klass
, void *data
)
443 DeviceClass
*dc
= DEVICE_CLASS(klass
);
445 dc
->realize
= imx_gpt_realize
;
446 dc
->reset
= imx_gpt_reset
;
447 dc
->vmsd
= &vmstate_imx_timer_gpt
;
448 dc
->desc
= "i.MX general timer";
451 static const TypeInfo imx_gpt_info
= {
452 .name
= TYPE_IMX_GPT
,
453 .parent
= TYPE_SYS_BUS_DEVICE
,
454 .instance_size
= sizeof(IMXGPTState
),
455 .class_init
= imx_gpt_class_init
,
458 static void imx_gpt_register_types(void)
460 type_register_static(&imx_gpt_info
);
463 type_init(imx_gpt_register_types
)