2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
26 #include "hw/pci-host/apb.h"
27 #include "hw/i386/pc.h"
28 #include "hw/char/serial.h"
29 #include "hw/timer/m48t59.h"
30 #include "hw/block/fdc.h"
32 #include "qemu/timer.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/boards.h"
35 #include "hw/nvram/openbios_firmware_abi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/sysbus.h"
39 #include "hw/loader.h"
41 #include "sysemu/block-backend.h"
42 #include "exec/address-spaces.h"
49 #define CPUIRQ_DPRINTF(fmt, ...) \
50 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
52 #define CPUIRQ_DPRINTF(fmt, ...)
56 #define EBUS_DPRINTF(fmt, ...) \
57 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
59 #define EBUS_DPRINTF(fmt, ...)
63 #define TIMER_DPRINTF(fmt, ...) \
64 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
66 #define TIMER_DPRINTF(fmt, ...)
69 #define KERNEL_LOAD_ADDR 0x00404000
70 #define CMDLINE_ADDR 0x003ff000
71 #define PROM_SIZE_MAX (4 * 1024 * 1024)
72 #define PROM_VADDR 0x000ffd00000ULL
73 #define APB_SPECIAL_BASE 0x1fe00000000ULL
74 #define APB_MEM_BASE 0x1ff00000000ULL
75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
76 #define PROM_FILENAME "openbios-sparc64"
77 #define NVRAM_SIZE 0x2000
79 #define BIOS_CFG_IOPORT 0x510
80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
86 #define TICK_MAX 0x7fffffffffffffffULL
89 const char * const default_cpu_model
;
92 uint64_t console_serial_base
;
95 typedef struct EbusState
{
101 int DMA_get_channel_mode (int nchan
)
105 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
109 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
113 void DMA_hold_DREQ (int nchan
) {}
114 void DMA_release_DREQ (int nchan
) {}
115 void DMA_schedule(void) {}
117 void DMA_init(int high_page_enable
)
121 void DMA_register_channel (int nchan
,
122 DMA_transfer_handler transfer_handler
,
127 static void fw_cfg_boot_set(void *opaque
, const char *boot_device
,
130 fw_cfg_modify_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
133 static int sun4u_NVRAM_set_params(Nvram
*nvram
, uint16_t NVRAM_size
,
134 const char *arch
, ram_addr_t RAM_size
,
135 const char *boot_devices
,
136 uint32_t kernel_image
, uint32_t kernel_size
,
138 uint32_t initrd_image
, uint32_t initrd_size
,
139 uint32_t NVRAM_image
,
140 int width
, int height
, int depth
,
141 const uint8_t *macaddr
)
145 uint8_t image
[0x1ff0];
146 struct OpenBIOS_nvpart_v1
*part_header
;
147 NvramClass
*k
= NVRAM_GET_CLASS(nvram
);
149 memset(image
, '\0', sizeof(image
));
153 // OpenBIOS nvram variables
154 // Variable partition
155 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
156 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
157 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
159 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
160 for (i
= 0; i
< nb_prom_envs
; i
++)
161 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
166 end
= start
+ ((end
- start
+ 15) & ~15);
167 OpenBIOS_finish_partition(part_header
, end
- start
);
171 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
172 part_header
->signature
= OPENBIOS_PART_FREE
;
173 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
176 OpenBIOS_finish_partition(part_header
, end
- start
);
178 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
180 for (i
= 0; i
< sizeof(image
); i
++) {
181 (k
->write
)(nvram
, i
, image
[i
]);
187 static uint64_t sun4u_load_kernel(const char *kernel_filename
,
188 const char *initrd_filename
,
189 ram_addr_t RAM_size
, uint64_t *initrd_size
,
190 uint64_t *initrd_addr
, uint64_t *kernel_addr
,
191 uint64_t *kernel_entry
)
199 linux_boot
= (kernel_filename
!= NULL
);
210 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, kernel_entry
,
211 kernel_addr
, &kernel_top
, 1, EM_SPARCV9
, 0);
212 if (kernel_size
< 0) {
213 *kernel_addr
= KERNEL_LOAD_ADDR
;
214 *kernel_entry
= KERNEL_LOAD_ADDR
;
215 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
216 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
219 if (kernel_size
< 0) {
220 kernel_size
= load_image_targphys(kernel_filename
,
222 RAM_size
- KERNEL_LOAD_ADDR
);
224 if (kernel_size
< 0) {
225 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
229 /* load initrd above kernel */
231 if (initrd_filename
) {
232 *initrd_addr
= TARGET_PAGE_ALIGN(kernel_top
);
234 *initrd_size
= load_image_targphys(initrd_filename
,
236 RAM_size
- *initrd_addr
);
237 if ((int)*initrd_size
< 0) {
238 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
243 if (*initrd_size
> 0) {
244 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
245 ptr
= rom_ptr(*kernel_addr
+ i
);
246 if (ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
247 stl_p(ptr
+ 24, *initrd_addr
+ *kernel_addr
);
248 stl_p(ptr
+ 28, *initrd_size
);
257 void cpu_check_irqs(CPUSPARCState
*env
)
260 uint32_t pil
= env
->pil_in
|
261 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
263 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
264 if (env
->ivec_status
& 0x20) {
267 cs
= CPU(sparc_env_get_cpu(env
));
268 /* check if TM or SM in SOFTINT are set
269 setting these also causes interrupt 14 */
270 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
274 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
276 if (pil
< (2 << env
->psrpil
)){
277 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
278 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
279 env
->interrupt_index
);
280 env
->interrupt_index
= 0;
281 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
286 if (cpu_interrupts_enabled(env
)) {
290 for (i
= 15; i
> env
->psrpil
; i
--) {
291 if (pil
& (1 << i
)) {
292 int old_interrupt
= env
->interrupt_index
;
293 int new_interrupt
= TT_EXTINT
| i
;
295 if (unlikely(env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
296 && ((cpu_tsptr(env
)->tt
& 0x1f0) == TT_EXTINT
))) {
297 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
298 "current %x >= pending %x\n",
299 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
300 } else if (old_interrupt
!= new_interrupt
) {
301 env
->interrupt_index
= new_interrupt
;
302 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
303 old_interrupt
, new_interrupt
);
304 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
309 } else if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
310 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
311 "current interrupt %x\n",
312 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
313 env
->interrupt_index
= 0;
314 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
318 static void cpu_kick_irq(SPARCCPU
*cpu
)
320 CPUState
*cs
= CPU(cpu
);
321 CPUSPARCState
*env
= &cpu
->env
;
328 static void cpu_set_ivec_irq(void *opaque
, int irq
, int level
)
330 SPARCCPU
*cpu
= opaque
;
331 CPUSPARCState
*env
= &cpu
->env
;
335 if (!(env
->ivec_status
& 0x20)) {
336 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq
);
339 env
->interrupt_index
= TT_IVEC
;
340 env
->ivec_status
|= 0x20;
341 env
->ivec_data
[0] = (0x1f << 6) | irq
;
342 env
->ivec_data
[1] = 0;
343 env
->ivec_data
[2] = 0;
344 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
347 if (env
->ivec_status
& 0x20) {
348 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq
);
350 env
->ivec_status
&= ~0x20;
351 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
356 typedef struct ResetData
{
361 static CPUTimer
*cpu_timer_create(const char *name
, SPARCCPU
*cpu
,
362 QEMUBHFunc
*cb
, uint32_t frequency
,
363 uint64_t disabled_mask
, uint64_t npt_mask
)
365 CPUTimer
*timer
= g_malloc0(sizeof (CPUTimer
));
368 timer
->frequency
= frequency
;
369 timer
->disabled_mask
= disabled_mask
;
370 timer
->npt_mask
= npt_mask
;
374 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
376 timer
->qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cb
, cpu
);
381 static void cpu_timer_reset(CPUTimer
*timer
)
384 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
386 timer_del(timer
->qtimer
);
389 static void main_cpu_reset(void *opaque
)
391 ResetData
*s
= (ResetData
*)opaque
;
392 CPUSPARCState
*env
= &s
->cpu
->env
;
393 static unsigned int nr_resets
;
395 cpu_reset(CPU(s
->cpu
));
397 cpu_timer_reset(env
->tick
);
398 cpu_timer_reset(env
->stick
);
399 cpu_timer_reset(env
->hstick
);
401 env
->gregs
[1] = 0; // Memory start
402 env
->gregs
[2] = ram_size
; // Memory size
403 env
->gregs
[3] = 0; // Machine description XXX
404 if (nr_resets
++ == 0) {
406 env
->pc
= s
->prom_addr
+ 0x20ULL
;
408 env
->pc
= s
->prom_addr
+ 0x40ULL
;
410 env
->npc
= env
->pc
+ 4;
413 static void tick_irq(void *opaque
)
415 SPARCCPU
*cpu
= opaque
;
416 CPUSPARCState
*env
= &cpu
->env
;
418 CPUTimer
* timer
= env
->tick
;
420 if (timer
->disabled
) {
421 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
424 CPUIRQ_DPRINTF("tick: fire\n");
427 env
->softint
|= SOFTINT_TIMER
;
431 static void stick_irq(void *opaque
)
433 SPARCCPU
*cpu
= opaque
;
434 CPUSPARCState
*env
= &cpu
->env
;
436 CPUTimer
* timer
= env
->stick
;
438 if (timer
->disabled
) {
439 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
442 CPUIRQ_DPRINTF("stick: fire\n");
445 env
->softint
|= SOFTINT_STIMER
;
449 static void hstick_irq(void *opaque
)
451 SPARCCPU
*cpu
= opaque
;
452 CPUSPARCState
*env
= &cpu
->env
;
454 CPUTimer
* timer
= env
->hstick
;
456 if (timer
->disabled
) {
457 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
460 CPUIRQ_DPRINTF("hstick: fire\n");
463 env
->softint
|= SOFTINT_STIMER
;
467 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks
, uint32_t frequency
)
469 return muldiv64(cpu_ticks
, get_ticks_per_sec(), frequency
);
472 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks
, uint32_t frequency
)
474 return muldiv64(timer_ticks
, frequency
, get_ticks_per_sec());
477 void cpu_tick_set_count(CPUTimer
*timer
, uint64_t count
)
479 uint64_t real_count
= count
& ~timer
->npt_mask
;
480 uint64_t npt_bit
= count
& timer
->npt_mask
;
482 int64_t vm_clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
483 cpu_to_timer_ticks(real_count
, timer
->frequency
);
485 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
486 timer
->name
, real_count
,
487 timer
->npt
? "disabled" : "enabled", timer
);
489 timer
->npt
= npt_bit
? 1 : 0;
490 timer
->clock_offset
= vm_clock_offset
;
493 uint64_t cpu_tick_get_count(CPUTimer
*timer
)
495 uint64_t real_count
= timer_to_cpu_ticks(
496 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->clock_offset
,
499 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
500 timer
->name
, real_count
,
501 timer
->npt
? "disabled" : "enabled", timer
);
504 real_count
|= timer
->npt_mask
;
510 void cpu_tick_set_limit(CPUTimer
*timer
, uint64_t limit
)
512 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
514 uint64_t real_limit
= limit
& ~timer
->disabled_mask
;
515 timer
->disabled
= (limit
& timer
->disabled_mask
) ? 1 : 0;
517 int64_t expires
= cpu_to_timer_ticks(real_limit
, timer
->frequency
) +
524 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
525 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
526 timer
->name
, real_limit
,
527 timer
->disabled
?"disabled":"enabled",
529 timer_to_cpu_ticks(now
- timer
->clock_offset
,
531 timer_to_cpu_ticks(expires
- now
, timer
->frequency
));
534 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
536 timer_del(timer
->qtimer
);
537 } else if (timer
->disabled
) {
538 timer_del(timer
->qtimer
);
540 timer_mod(timer
->qtimer
, expires
);
544 static void isa_irq_handler(void *opaque
, int n
, int level
)
546 static const int isa_irq_to_ivec
[16] = {
547 [1] = 0x29, /* keyboard */
548 [4] = 0x2b, /* serial */
549 [6] = 0x27, /* floppy */
550 [7] = 0x22, /* parallel */
551 [12] = 0x2a, /* mouse */
553 qemu_irq
*irqs
= opaque
;
557 ivec
= isa_irq_to_ivec
[n
];
558 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n
, level
, ivec
);
560 qemu_set_irq(irqs
[ivec
], level
);
564 /* EBUS (Eight bit bus) bridge */
566 pci_ebus_init(PCIBus
*bus
, int devfn
, qemu_irq
*irqs
)
572 pci_dev
= pci_create_simple(bus
, devfn
, "ebus");
573 isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev
), "isa.0"));
574 isa_irq
= qemu_allocate_irqs(isa_irq_handler
, irqs
, 16);
575 isa_bus_irqs(isa_bus
, isa_irq
);
579 static void pci_ebus_realize(PCIDevice
*pci_dev
, Error
**errp
)
581 EbusState
*s
= DO_UPCAST(EbusState
, pci_dev
, pci_dev
);
583 if (!isa_bus_new(DEVICE(pci_dev
), get_system_memory(),
584 pci_address_space_io(pci_dev
), errp
)) {
588 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
589 pci_dev
->config
[0x05] = 0x00;
590 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
591 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
592 pci_dev
->config
[0x09] = 0x00; // programming i/f
593 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
595 memory_region_init_alias(&s
->bar0
, OBJECT(s
), "bar0", get_system_io(),
597 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
598 memory_region_init_alias(&s
->bar1
, OBJECT(s
), "bar1", get_system_io(),
600 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->bar1
);
603 static void ebus_class_init(ObjectClass
*klass
, void *data
)
605 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
607 k
->realize
= pci_ebus_realize
;
608 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
609 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
611 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
614 static const TypeInfo ebus_info
= {
616 .parent
= TYPE_PCI_DEVICE
,
617 .instance_size
= sizeof(EbusState
),
618 .class_init
= ebus_class_init
,
621 #define TYPE_OPENPROM "openprom"
622 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
624 typedef struct PROMState
{
625 SysBusDevice parent_obj
;
630 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
632 hwaddr
*base_addr
= (hwaddr
*)opaque
;
633 return addr
+ *base_addr
- PROM_VADDR
;
636 /* Boot PROM (OpenBIOS) */
637 static void prom_init(hwaddr addr
, const char *bios_name
)
644 dev
= qdev_create(NULL
, TYPE_OPENPROM
);
645 qdev_init_nofail(dev
);
646 s
= SYS_BUS_DEVICE(dev
);
648 sysbus_mmio_map(s
, 0, addr
);
651 if (bios_name
== NULL
) {
652 bios_name
= PROM_FILENAME
;
654 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
656 ret
= load_elf(filename
, translate_prom_address
, &addr
,
657 NULL
, NULL
, NULL
, 1, EM_SPARCV9
, 0);
658 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
659 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
665 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
666 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
671 static int prom_init1(SysBusDevice
*dev
)
673 PROMState
*s
= OPENPROM(dev
);
675 memory_region_init_ram(&s
->prom
, OBJECT(s
), "sun4u.prom", PROM_SIZE_MAX
,
677 vmstate_register_ram_global(&s
->prom
);
678 memory_region_set_readonly(&s
->prom
, true);
679 sysbus_init_mmio(dev
, &s
->prom
);
683 static Property prom_properties
[] = {
684 {/* end of property list */},
687 static void prom_class_init(ObjectClass
*klass
, void *data
)
689 DeviceClass
*dc
= DEVICE_CLASS(klass
);
690 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
692 k
->init
= prom_init1
;
693 dc
->props
= prom_properties
;
696 static const TypeInfo prom_info
= {
697 .name
= TYPE_OPENPROM
,
698 .parent
= TYPE_SYS_BUS_DEVICE
,
699 .instance_size
= sizeof(PROMState
),
700 .class_init
= prom_class_init
,
704 #define TYPE_SUN4U_MEMORY "memory"
705 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY)
707 typedef struct RamDevice
{
708 SysBusDevice parent_obj
;
715 static int ram_init1(SysBusDevice
*dev
)
717 RamDevice
*d
= SUN4U_RAM(dev
);
719 memory_region_init_ram(&d
->ram
, OBJECT(d
), "sun4u.ram", d
->size
,
721 vmstate_register_ram_global(&d
->ram
);
722 sysbus_init_mmio(dev
, &d
->ram
);
726 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
)
733 dev
= qdev_create(NULL
, TYPE_SUN4U_MEMORY
);
734 s
= SYS_BUS_DEVICE(dev
);
738 qdev_init_nofail(dev
);
740 sysbus_mmio_map(s
, 0, addr
);
743 static Property ram_properties
[] = {
744 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
745 DEFINE_PROP_END_OF_LIST(),
748 static void ram_class_init(ObjectClass
*klass
, void *data
)
750 DeviceClass
*dc
= DEVICE_CLASS(klass
);
751 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
754 dc
->props
= ram_properties
;
757 static const TypeInfo ram_info
= {
758 .name
= TYPE_SUN4U_MEMORY
,
759 .parent
= TYPE_SYS_BUS_DEVICE
,
760 .instance_size
= sizeof(RamDevice
),
761 .class_init
= ram_class_init
,
764 static SPARCCPU
*cpu_devinit(const char *cpu_model
, const struct hwdef
*hwdef
)
768 ResetData
*reset_info
;
770 uint32_t tick_frequency
= 100*1000000;
771 uint32_t stick_frequency
= 100*1000000;
772 uint32_t hstick_frequency
= 100*1000000;
774 if (cpu_model
== NULL
) {
775 cpu_model
= hwdef
->default_cpu_model
;
777 cpu
= cpu_sparc_init(cpu_model
);
779 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
784 env
->tick
= cpu_timer_create("tick", cpu
, tick_irq
,
785 tick_frequency
, TICK_INT_DIS
,
788 env
->stick
= cpu_timer_create("stick", cpu
, stick_irq
,
789 stick_frequency
, TICK_INT_DIS
,
792 env
->hstick
= cpu_timer_create("hstick", cpu
, hstick_irq
,
793 hstick_frequency
, TICK_INT_DIS
,
796 reset_info
= g_malloc0(sizeof(ResetData
));
797 reset_info
->cpu
= cpu
;
798 reset_info
->prom_addr
= hwdef
->prom_addr
;
799 qemu_register_reset(main_cpu_reset
, reset_info
);
804 static void sun4uv_init(MemoryRegion
*address_space_mem
,
805 MachineState
*machine
,
806 const struct hwdef
*hwdef
)
811 uint64_t initrd_addr
, initrd_size
, kernel_addr
, kernel_size
, kernel_entry
;
812 PCIBus
*pci_bus
, *pci_bus2
, *pci_bus3
;
815 qemu_irq
*ivec_irqs
, *pbm_irqs
;
816 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
817 DriveInfo
*fd
[MAX_FD
];
821 cpu
= cpu_devinit(machine
->cpu_model
, hwdef
);
824 ram_init(0, machine
->ram_size
);
826 prom_init(hwdef
->prom_addr
, bios_name
);
828 ivec_irqs
= qemu_allocate_irqs(cpu_set_ivec_irq
, cpu
, IVEC_MAX
);
829 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, ivec_irqs
, &pci_bus2
,
830 &pci_bus3
, &pbm_irqs
);
831 pci_vga_init(pci_bus
);
833 // XXX Should be pci_bus3
834 isa_bus
= pci_ebus_init(pci_bus
, -1, pbm_irqs
);
837 if (hwdef
->console_serial_base
) {
838 serial_mm_init(address_space_mem
, hwdef
->console_serial_base
, 0,
839 NULL
, 115200, serial_hds
[i
], DEVICE_BIG_ENDIAN
);
843 serial_hds_isa_init(isa_bus
, MAX_SERIAL_PORTS
);
844 parallel_hds_isa_init(isa_bus
, MAX_PARALLEL_PORTS
);
846 for(i
= 0; i
< nb_nics
; i
++)
847 pci_nic_init_nofail(&nd_table
[i
], pci_bus
, "ne2k_pci", NULL
);
849 ide_drive_get(hd
, ARRAY_SIZE(hd
));
851 pci_cmd646_ide_init(pci_bus
, hd
, 1);
853 isa_create_simple(isa_bus
, "i8042");
854 for(i
= 0; i
< MAX_FD
; i
++) {
855 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
857 fdctrl_init_isa(isa_bus
, fd
);
859 /* Map NVRAM into I/O (ebus) space */
860 nvram
= m48t59_init(NULL
, 0, 0, NVRAM_SIZE
, 1968, 59);
861 s
= SYS_BUS_DEVICE(nvram
);
862 memory_region_add_subregion(get_system_io(), 0x2000,
863 sysbus_mmio_get_region(s
, 0));
867 kernel_size
= sun4u_load_kernel(machine
->kernel_filename
,
868 machine
->initrd_filename
,
869 ram_size
, &initrd_size
, &initrd_addr
,
870 &kernel_addr
, &kernel_entry
);
872 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", machine
->ram_size
,
874 kernel_addr
, kernel_size
,
875 machine
->kernel_cmdline
,
876 initrd_addr
, initrd_size
,
877 /* XXX: need an option to load a NVRAM image */
879 graphic_width
, graphic_height
, graphic_depth
,
880 (uint8_t *)&nd_table
[0].macaddr
);
882 fw_cfg
= fw_cfg_init_io(BIOS_CFG_IOPORT
);
883 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
884 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
885 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
886 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_ADDR
, kernel_entry
);
887 fw_cfg_add_i64(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
888 if (machine
->kernel_cmdline
) {
889 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
890 strlen(machine
->kernel_cmdline
) + 1);
891 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, machine
->kernel_cmdline
);
893 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
895 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
896 fw_cfg_add_i64(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
897 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, machine
->boot_order
[0]);
899 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
900 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
901 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
903 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
912 static const struct hwdef hwdefs
[] = {
913 /* Sun4u generic PC-like machine */
915 .default_cpu_model
= "TI UltraSparc IIi",
916 .machine_id
= sun4u_id
,
917 .prom_addr
= 0x1fff0000000ULL
,
918 .console_serial_base
= 0,
920 /* Sun4v generic PC-like machine */
922 .default_cpu_model
= "Sun UltraSparc T1",
923 .machine_id
= sun4v_id
,
924 .prom_addr
= 0x1fff0000000ULL
,
925 .console_serial_base
= 0,
927 /* Sun4v generic Niagara machine */
929 .default_cpu_model
= "Sun UltraSparc T1",
930 .machine_id
= niagara_id
,
931 .prom_addr
= 0xfff0000000ULL
,
932 .console_serial_base
= 0xfff0c2c000ULL
,
936 /* Sun4u hardware initialisation */
937 static void sun4u_init(MachineState
*machine
)
939 sun4uv_init(get_system_memory(), machine
, &hwdefs
[0]);
942 /* Sun4v hardware initialisation */
943 static void sun4v_init(MachineState
*machine
)
945 sun4uv_init(get_system_memory(), machine
, &hwdefs
[1]);
948 /* Niagara hardware initialisation */
949 static void niagara_init(MachineState
*machine
)
951 sun4uv_init(get_system_memory(), machine
, &hwdefs
[2]);
954 static void sun4u_class_init(ObjectClass
*oc
, void *data
)
956 MachineClass
*mc
= MACHINE_CLASS(oc
);
958 mc
->desc
= "Sun4u platform";
959 mc
->init
= sun4u_init
;
960 mc
->max_cpus
= 1; /* XXX for now */
962 mc
->default_boot_order
= "c";
965 static const TypeInfo sun4u_type
= {
966 .name
= MACHINE_TYPE_NAME("sun4u"),
967 .parent
= TYPE_MACHINE
,
968 .class_init
= sun4u_class_init
,
971 static void sun4v_class_init(ObjectClass
*oc
, void *data
)
973 MachineClass
*mc
= MACHINE_CLASS(oc
);
975 mc
->desc
= "Sun4v platform";
976 mc
->init
= sun4v_init
;
977 mc
->max_cpus
= 1; /* XXX for now */
978 mc
->default_boot_order
= "c";
981 static const TypeInfo sun4v_type
= {
982 .name
= MACHINE_TYPE_NAME("sun4v"),
983 .parent
= TYPE_MACHINE
,
984 .class_init
= sun4v_class_init
,
987 static void niagara_class_init(ObjectClass
*oc
, void *data
)
989 MachineClass
*mc
= MACHINE_CLASS(oc
);
991 mc
->desc
= "Sun4v platform, Niagara";
992 mc
->init
= niagara_init
;
993 mc
->max_cpus
= 1; /* XXX for now */
994 mc
->default_boot_order
= "c";
997 static const TypeInfo niagara_type
= {
998 .name
= MACHINE_TYPE_NAME("Niagara"),
999 .parent
= TYPE_MACHINE
,
1000 .class_init
= niagara_class_init
,
1003 static void sun4u_register_types(void)
1005 type_register_static(&ebus_info
);
1006 type_register_static(&prom_info
);
1007 type_register_static(&ram_info
);
1010 static void sun4u_machine_init(void)
1012 type_register_static(&sun4u_type
);
1013 type_register_static(&sun4v_type
);
1014 type_register_static(&niagara_type
);
1017 type_init(sun4u_register_types
)
1018 machine_init(sun4u_machine_init
)