2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qemu/main-loop.h"
31 #include "exec/helper-proto.h"
32 #include "qemu/host-utils.h"
33 #include "exec/exec-all.h"
34 #include "exec/cpu_ldst.h"
35 #include "exec/address-spaces.h"
36 #include "qemu/timer.h"
37 #include "fpu/softfloat.h"
39 #ifdef CONFIG_USER_ONLY
40 /* tb_invalidate_phys_range */
41 #include "accel/tcg/translate-all.h"
44 #ifndef CONFIG_USER_ONLY
46 void xtensa_cpu_do_unaligned_access(CPUState
*cs
,
47 vaddr addr
, MMUAccessType access_type
,
48 int mmu_idx
, uintptr_t retaddr
)
50 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
51 CPUXtensaState
*env
= &cpu
->env
;
53 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_UNALIGNED_EXCEPTION
) &&
54 !xtensa_option_enabled(env
->config
, XTENSA_OPTION_HW_ALIGNMENT
)) {
55 cpu_restore_state(CPU(cpu
), retaddr
, true);
56 HELPER(exception_cause_vaddr
)(env
,
57 env
->pc
, LOAD_STORE_ALIGNMENT_CAUSE
, addr
);
61 void tlb_fill(CPUState
*cs
, target_ulong vaddr
, int size
,
62 MMUAccessType access_type
, int mmu_idx
, uintptr_t retaddr
)
64 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
65 CPUXtensaState
*env
= &cpu
->env
;
69 int ret
= xtensa_get_physical_addr(env
, true, vaddr
, access_type
, mmu_idx
,
70 &paddr
, &page_size
, &access
);
72 qemu_log_mask(CPU_LOG_MMU
, "%s(%08x, %d, %d) -> %08x, ret = %d\n",
73 __func__
, vaddr
, access_type
, mmu_idx
, paddr
, ret
);
77 vaddr
& TARGET_PAGE_MASK
,
78 paddr
& TARGET_PAGE_MASK
,
79 access
, mmu_idx
, page_size
);
81 cpu_restore_state(cs
, retaddr
, true);
82 HELPER(exception_cause_vaddr
)(env
, env
->pc
, ret
, vaddr
);
86 void xtensa_cpu_do_unassigned_access(CPUState
*cs
, hwaddr addr
,
87 bool is_write
, bool is_exec
, int opaque
,
90 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
91 CPUXtensaState
*env
= &cpu
->env
;
93 HELPER(exception_cause_vaddr
)(env
, env
->pc
,
95 INSTR_PIF_ADDR_ERROR_CAUSE
:
96 LOAD_STORE_PIF_ADDR_ERROR_CAUSE
,
97 is_exec
? addr
: cs
->mem_io_vaddr
);
100 static void tb_invalidate_virtual_addr(CPUXtensaState
*env
, uint32_t vaddr
)
105 int ret
= xtensa_get_physical_addr(env
, false, vaddr
, 2, 0,
106 &paddr
, &page_size
, &access
);
108 tb_invalidate_phys_addr(&address_space_memory
, paddr
,
109 MEMTXATTRS_UNSPECIFIED
);
115 static void tb_invalidate_virtual_addr(CPUXtensaState
*env
, uint32_t vaddr
)
118 tb_invalidate_phys_range(vaddr
, vaddr
+ 1);
124 void HELPER(exception
)(CPUXtensaState
*env
, uint32_t excp
)
126 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
128 cs
->exception_index
= excp
;
129 if (excp
== EXCP_YIELD
) {
130 env
->yield_needed
= 0;
132 if (excp
== EXCP_DEBUG
) {
133 env
->exception_taken
= 0;
138 void HELPER(exception_cause
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
143 if (env
->sregs
[PS
] & PS_EXCM
) {
144 if (env
->config
->ndepc
) {
145 env
->sregs
[DEPC
] = pc
;
147 env
->sregs
[EPC1
] = pc
;
151 env
->sregs
[EPC1
] = pc
;
152 vector
= (env
->sregs
[PS
] & PS_UM
) ? EXC_USER
: EXC_KERNEL
;
155 env
->sregs
[EXCCAUSE
] = cause
;
156 env
->sregs
[PS
] |= PS_EXCM
;
158 HELPER(exception
)(env
, vector
);
161 void HELPER(exception_cause_vaddr
)(CPUXtensaState
*env
,
162 uint32_t pc
, uint32_t cause
, uint32_t vaddr
)
164 env
->sregs
[EXCVADDR
] = vaddr
;
165 HELPER(exception_cause
)(env
, pc
, cause
);
168 void debug_exception_env(CPUXtensaState
*env
, uint32_t cause
)
170 if (xtensa_get_cintlevel(env
) < env
->config
->debug_level
) {
171 HELPER(debug_exception
)(env
, env
->pc
, cause
);
175 void HELPER(debug_exception
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t cause
)
177 unsigned level
= env
->config
->debug_level
;
180 env
->sregs
[DEBUGCAUSE
] = cause
;
181 env
->sregs
[EPC1
+ level
- 1] = pc
;
182 env
->sregs
[EPS2
+ level
- 2] = env
->sregs
[PS
];
183 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) | PS_EXCM
|
184 (level
<< PS_INTLEVEL_SHIFT
);
185 HELPER(exception
)(env
, EXC_DEBUG
);
188 static void copy_window_from_phys(CPUXtensaState
*env
,
189 uint32_t window
, uint32_t phys
, uint32_t n
)
191 assert(phys
< env
->config
->nareg
);
192 if (phys
+ n
<= env
->config
->nareg
) {
193 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
194 n
* sizeof(uint32_t));
196 uint32_t n1
= env
->config
->nareg
- phys
;
197 memcpy(env
->regs
+ window
, env
->phys_regs
+ phys
,
198 n1
* sizeof(uint32_t));
199 memcpy(env
->regs
+ window
+ n1
, env
->phys_regs
,
200 (n
- n1
) * sizeof(uint32_t));
204 static void copy_phys_from_window(CPUXtensaState
*env
,
205 uint32_t phys
, uint32_t window
, uint32_t n
)
207 assert(phys
< env
->config
->nareg
);
208 if (phys
+ n
<= env
->config
->nareg
) {
209 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
210 n
* sizeof(uint32_t));
212 uint32_t n1
= env
->config
->nareg
- phys
;
213 memcpy(env
->phys_regs
+ phys
, env
->regs
+ window
,
214 n1
* sizeof(uint32_t));
215 memcpy(env
->phys_regs
, env
->regs
+ window
+ n1
,
216 (n
- n1
) * sizeof(uint32_t));
221 static inline unsigned windowbase_bound(unsigned a
, const CPUXtensaState
*env
)
223 return a
& (env
->config
->nareg
/ 4 - 1);
226 static inline unsigned windowstart_bit(unsigned a
, const CPUXtensaState
*env
)
228 return 1 << windowbase_bound(a
, env
);
231 void xtensa_sync_window_from_phys(CPUXtensaState
*env
)
233 copy_window_from_phys(env
, 0, env
->sregs
[WINDOW_BASE
] * 4, 16);
236 void xtensa_sync_phys_from_window(CPUXtensaState
*env
)
238 copy_phys_from_window(env
, env
->sregs
[WINDOW_BASE
] * 4, 0, 16);
241 static void xtensa_rotate_window_abs(CPUXtensaState
*env
, uint32_t position
)
243 xtensa_sync_phys_from_window(env
);
244 env
->sregs
[WINDOW_BASE
] = windowbase_bound(position
, env
);
245 xtensa_sync_window_from_phys(env
);
248 void xtensa_rotate_window(CPUXtensaState
*env
, uint32_t delta
)
250 xtensa_rotate_window_abs(env
, env
->sregs
[WINDOW_BASE
] + delta
);
253 void HELPER(wsr_windowbase
)(CPUXtensaState
*env
, uint32_t v
)
255 xtensa_rotate_window_abs(env
, v
);
258 void HELPER(entry
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t s
, uint32_t imm
)
260 int callinc
= (env
->sregs
[PS
] & PS_CALLINC
) >> PS_CALLINC_SHIFT
;
261 if (s
> 3 || ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
262 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal entry instruction(pc = %08x), PS = %08x\n",
264 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
266 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
267 (env
->sregs
[WINDOW_BASE
] + 1);
269 if (windowstart
& ((1 << callinc
) - 1)) {
270 HELPER(window_check
)(env
, pc
, callinc
);
272 env
->regs
[(callinc
<< 2) | (s
& 3)] = env
->regs
[s
] - imm
;
273 xtensa_rotate_window(env
, callinc
);
274 env
->sregs
[WINDOW_START
] |=
275 windowstart_bit(env
->sregs
[WINDOW_BASE
], env
);
279 void HELPER(window_check
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t w
)
281 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
282 uint32_t windowstart
= xtensa_replicate_windowstart(env
) >>
283 (env
->sregs
[WINDOW_BASE
] + 1);
284 uint32_t n
= ctz32(windowstart
) + 1;
288 xtensa_rotate_window(env
, n
);
289 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
290 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
291 env
->sregs
[EPC1
] = env
->pc
= pc
;
293 switch (ctz32(windowstart
>> n
)) {
295 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW4
);
298 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW8
);
301 HELPER(exception
)(env
, EXC_WINDOW_OVERFLOW12
);
306 uint32_t HELPER(retw
)(CPUXtensaState
*env
, uint32_t pc
)
308 int n
= (env
->regs
[0] >> 30) & 0x3;
310 uint32_t windowbase
= windowbase_bound(env
->sregs
[WINDOW_BASE
], env
);
311 uint32_t windowstart
= env
->sregs
[WINDOW_START
];
314 if (windowstart
& windowstart_bit(windowbase
- 1, env
)) {
316 } else if (windowstart
& windowstart_bit(windowbase
- 2, env
)) {
318 } else if (windowstart
& windowstart_bit(windowbase
- 3, env
)) {
322 if (n
== 0 || (m
!= 0 && m
!= n
) ||
323 ((env
->sregs
[PS
] & (PS_WOE
| PS_EXCM
)) ^ PS_WOE
) != 0) {
324 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal retw instruction(pc = %08x), "
325 "PS = %08x, m = %d, n = %d\n",
326 pc
, env
->sregs
[PS
], m
, n
);
327 HELPER(exception_cause
)(env
, pc
, ILLEGAL_INSTRUCTION_CAUSE
);
329 int owb
= windowbase
;
331 ret_pc
= (pc
& 0xc0000000) | (env
->regs
[0] & 0x3fffffff);
333 xtensa_rotate_window(env
, -n
);
334 if (windowstart
& windowstart_bit(env
->sregs
[WINDOW_BASE
], env
)) {
335 env
->sregs
[WINDOW_START
] &= ~windowstart_bit(owb
, env
);
337 /* window underflow */
338 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_OWB
) |
339 (windowbase
<< PS_OWB_SHIFT
) | PS_EXCM
;
340 env
->sregs
[EPC1
] = env
->pc
= pc
;
343 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW4
);
345 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW8
);
347 HELPER(exception
)(env
, EXC_WINDOW_UNDERFLOW12
);
354 void HELPER(rotw
)(CPUXtensaState
*env
, uint32_t imm4
)
356 xtensa_rotate_window(env
, imm4
);
359 void xtensa_restore_owb(CPUXtensaState
*env
)
361 xtensa_rotate_window_abs(env
, (env
->sregs
[PS
] & PS_OWB
) >> PS_OWB_SHIFT
);
364 void HELPER(restore_owb
)(CPUXtensaState
*env
)
366 xtensa_restore_owb(env
);
369 void HELPER(movsp
)(CPUXtensaState
*env
, uint32_t pc
)
371 if ((env
->sregs
[WINDOW_START
] &
372 (windowstart_bit(env
->sregs
[WINDOW_BASE
] - 3, env
) |
373 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 2, env
) |
374 windowstart_bit(env
->sregs
[WINDOW_BASE
] - 1, env
))) == 0) {
375 HELPER(exception_cause
)(env
, pc
, ALLOCA_CAUSE
);
379 void HELPER(wsr_lbeg
)(CPUXtensaState
*env
, uint32_t v
)
381 if (env
->sregs
[LBEG
] != v
) {
382 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
383 env
->sregs
[LBEG
] = v
;
387 void HELPER(wsr_lend
)(CPUXtensaState
*env
, uint32_t v
)
389 if (env
->sregs
[LEND
] != v
) {
390 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
391 env
->sregs
[LEND
] = v
;
392 tb_invalidate_virtual_addr(env
, env
->sregs
[LEND
] - 1);
396 void HELPER(dump_state
)(CPUXtensaState
*env
)
398 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
400 cpu_dump_state(CPU(cpu
), stderr
, fprintf
, 0);
403 #ifndef CONFIG_USER_ONLY
405 void HELPER(waiti
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t intlevel
)
410 env
->sregs
[PS
] = (env
->sregs
[PS
] & ~PS_INTLEVEL
) |
411 (intlevel
<< PS_INTLEVEL_SHIFT
);
413 qemu_mutex_lock_iothread();
414 check_interrupts(env
);
415 qemu_mutex_unlock_iothread();
417 if (env
->pending_irq_level
) {
418 cpu_loop_exit(CPU(xtensa_env_get_cpu(env
)));
422 cpu
= CPU(xtensa_env_get_cpu(env
));
424 HELPER(exception
)(env
, EXCP_HLT
);
427 void HELPER(update_ccount
)(CPUXtensaState
*env
)
429 uint64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
431 env
->ccount_time
= now
;
432 env
->sregs
[CCOUNT
] = env
->ccount_base
+
433 (uint32_t)((now
- env
->time_base
) *
434 env
->config
->clock_freq_khz
/ 1000000);
437 void HELPER(wsr_ccount
)(CPUXtensaState
*env
, uint32_t v
)
441 HELPER(update_ccount
)(env
);
442 env
->ccount_base
+= v
- env
->sregs
[CCOUNT
];
443 for (i
= 0; i
< env
->config
->nccompare
; ++i
) {
444 HELPER(update_ccompare
)(env
, i
);
448 void HELPER(update_ccompare
)(CPUXtensaState
*env
, uint32_t i
)
452 HELPER(update_ccount
)(env
);
453 dcc
= (uint64_t)(env
->sregs
[CCOMPARE
+ i
] - env
->sregs
[CCOUNT
] - 1) + 1;
454 timer_mod(env
->ccompare
[i
].timer
,
455 env
->ccount_time
+ (dcc
* 1000000) / env
->config
->clock_freq_khz
);
456 env
->yield_needed
= 1;
459 void HELPER(check_interrupts
)(CPUXtensaState
*env
)
461 qemu_mutex_lock_iothread();
462 check_interrupts(env
);
463 qemu_mutex_unlock_iothread();
466 void HELPER(itlb_hit_test
)(CPUXtensaState
*env
, uint32_t vaddr
)
468 get_page_addr_code(env
, vaddr
);
472 * Check vaddr accessibility/cache attributes and raise an exception if
473 * specified by the ATOMCTL SR.
475 * Note: local memory exclusion is not implemented
477 void HELPER(check_atomctl
)(CPUXtensaState
*env
, uint32_t pc
, uint32_t vaddr
)
479 uint32_t paddr
, page_size
, access
;
480 uint32_t atomctl
= env
->sregs
[ATOMCTL
];
481 int rc
= xtensa_get_physical_addr(env
, true, vaddr
, 1,
482 xtensa_get_cring(env
), &paddr
, &page_size
, &access
);
485 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
486 * see opcode description in the ISA
489 (access
& (PAGE_READ
| PAGE_WRITE
)) != (PAGE_READ
| PAGE_WRITE
)) {
490 rc
= STORE_PROHIBITED_CAUSE
;
494 HELPER(exception_cause_vaddr
)(env
, pc
, rc
, vaddr
);
498 * When data cache is not configured use ATOMCTL bypass field.
499 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
500 * under the Conditional Store Option.
502 if (!xtensa_option_enabled(env
->config
, XTENSA_OPTION_DCACHE
)) {
503 access
= PAGE_CACHE_BYPASS
;
506 switch (access
& PAGE_CACHE_MASK
) {
513 case PAGE_CACHE_BYPASS
:
514 if ((atomctl
& 0x3) == 0) {
515 HELPER(exception_cause_vaddr
)(env
, pc
,
516 LOAD_STORE_ERROR_CAUSE
, vaddr
);
520 case PAGE_CACHE_ISOLATE
:
521 HELPER(exception_cause_vaddr
)(env
, pc
,
522 LOAD_STORE_ERROR_CAUSE
, vaddr
);
530 void HELPER(wsr_memctl
)(CPUXtensaState
*env
, uint32_t v
)
532 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_ICACHE
)) {
533 if (extract32(v
, MEMCTL_IUSEWAYS_SHIFT
, MEMCTL_IUSEWAYS_LEN
) >
534 env
->config
->icache_ways
) {
535 deposit32(v
, MEMCTL_IUSEWAYS_SHIFT
, MEMCTL_IUSEWAYS_LEN
,
536 env
->config
->icache_ways
);
539 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_DCACHE
)) {
540 if (extract32(v
, MEMCTL_DUSEWAYS_SHIFT
, MEMCTL_DUSEWAYS_LEN
) >
541 env
->config
->dcache_ways
) {
542 deposit32(v
, MEMCTL_DUSEWAYS_SHIFT
, MEMCTL_DUSEWAYS_LEN
,
543 env
->config
->dcache_ways
);
545 if (extract32(v
, MEMCTL_DALLOCWAYS_SHIFT
, MEMCTL_DALLOCWAYS_LEN
) >
546 env
->config
->dcache_ways
) {
547 deposit32(v
, MEMCTL_DALLOCWAYS_SHIFT
, MEMCTL_DALLOCWAYS_LEN
,
548 env
->config
->dcache_ways
);
551 env
->sregs
[MEMCTL
] = v
& env
->config
->memctl_mask
;
554 void HELPER(wsr_rasid
)(CPUXtensaState
*env
, uint32_t v
)
556 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
558 v
= (v
& 0xffffff00) | 0x1;
559 if (v
!= env
->sregs
[RASID
]) {
560 env
->sregs
[RASID
] = v
;
565 static uint32_t get_page_size(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
567 uint32_t tlbcfg
= env
->sregs
[dtlb
? DTLBCFG
: ITLBCFG
];
571 return (tlbcfg
>> 16) & 0x3;
574 return (tlbcfg
>> 20) & 0x1;
577 return (tlbcfg
>> 24) & 0x1;
585 * Get bit mask for the virtual address bits translated by the TLB way
587 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
589 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
590 bool varway56
= dtlb
?
591 env
->config
->dtlb
.varway56
:
592 env
->config
->itlb
.varway56
;
596 return 0xfff00000 << get_page_size(env
, dtlb
, way
) * 2;
600 return 0xf8000000 << get_page_size(env
, dtlb
, way
);
607 return 0xf0000000 << (1 - get_page_size(env
, dtlb
, way
));
616 return REGION_PAGE_MASK
;
621 * Get bit mask for the 'VPN without index' field.
622 * See ISA, 4.6.5.6, data format for RxTLB0
624 static uint32_t get_vpn_mask(const CPUXtensaState
*env
, bool dtlb
, uint32_t way
)
628 env
->config
->dtlb
.nrefillentries
:
629 env
->config
->itlb
.nrefillentries
) == 32;
630 return is32
? 0xffff8000 : 0xffffc000;
631 } else if (way
== 4) {
632 return xtensa_tlb_get_addr_mask(env
, dtlb
, way
) << 2;
633 } else if (way
<= 6) {
634 uint32_t mask
= xtensa_tlb_get_addr_mask(env
, dtlb
, way
);
635 bool varway56
= dtlb
?
636 env
->config
->dtlb
.varway56
:
637 env
->config
->itlb
.varway56
;
640 return mask
<< (way
== 5 ? 2 : 3);
650 * Split virtual address into VPN (with index) and entry index
651 * for the given TLB way
653 void split_tlb_entry_spec_way(const CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
654 uint32_t *vpn
, uint32_t wi
, uint32_t *ei
)
656 bool varway56
= dtlb
?
657 env
->config
->dtlb
.varway56
:
658 env
->config
->itlb
.varway56
;
666 env
->config
->dtlb
.nrefillentries
:
667 env
->config
->itlb
.nrefillentries
) == 32;
668 *ei
= (v
>> 12) & (is32
? 0x7 : 0x3);
673 uint32_t eibase
= 20 + get_page_size(env
, dtlb
, wi
) * 2;
674 *ei
= (v
>> eibase
) & 0x3;
680 uint32_t eibase
= 27 + get_page_size(env
, dtlb
, wi
);
681 *ei
= (v
>> eibase
) & 0x3;
683 *ei
= (v
>> 27) & 0x1;
689 uint32_t eibase
= 29 - get_page_size(env
, dtlb
, wi
);
690 *ei
= (v
>> eibase
) & 0x7;
692 *ei
= (v
>> 28) & 0x1;
701 *vpn
= v
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
705 * Split TLB address into TLB way, entry index and VPN (with index).
706 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
708 static void split_tlb_entry_spec(CPUXtensaState
*env
, uint32_t v
, bool dtlb
,
709 uint32_t *vpn
, uint32_t *wi
, uint32_t *ei
)
711 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
712 *wi
= v
& (dtlb
? 0xf : 0x7);
713 split_tlb_entry_spec_way(env
, v
, dtlb
, vpn
, *wi
, ei
);
715 *vpn
= v
& REGION_PAGE_MASK
;
717 *ei
= (v
>> 29) & 0x7;
721 static xtensa_tlb_entry
*get_tlb_entry(CPUXtensaState
*env
,
722 uint32_t v
, bool dtlb
, uint32_t *pwi
)
728 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
732 return xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
735 uint32_t HELPER(rtlb0
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
737 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
739 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
740 return (entry
->vaddr
& get_vpn_mask(env
, dtlb
, wi
)) | entry
->asid
;
742 return v
& REGION_PAGE_MASK
;
746 uint32_t HELPER(rtlb1
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
748 const xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, NULL
);
749 return entry
->paddr
| entry
->attr
;
752 void HELPER(itlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
754 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
756 xtensa_tlb_entry
*entry
= get_tlb_entry(env
, v
, dtlb
, &wi
);
757 if (entry
->variable
&& entry
->asid
) {
758 tlb_flush_page(CPU(xtensa_env_get_cpu(env
)), entry
->vaddr
);
764 uint32_t HELPER(ptlb
)(CPUXtensaState
*env
, uint32_t v
, uint32_t dtlb
)
766 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
770 int res
= xtensa_tlb_lookup(env
, v
, dtlb
, &wi
, &ei
, &ring
);
774 if (ring
>= xtensa_get_ring(env
)) {
775 return (v
& 0xfffff000) | wi
| (dtlb
? 0x10 : 0x8);
779 case INST_TLB_MULTI_HIT_CAUSE
:
780 case LOAD_STORE_TLB_MULTI_HIT_CAUSE
:
781 HELPER(exception_cause_vaddr
)(env
, env
->pc
, res
, v
);
786 return (v
& REGION_PAGE_MASK
) | 0x1;
790 void xtensa_tlb_set_entry_mmu(const CPUXtensaState
*env
,
791 xtensa_tlb_entry
*entry
, bool dtlb
,
792 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
795 entry
->paddr
= pte
& xtensa_tlb_get_addr_mask(env
, dtlb
, wi
);
796 entry
->asid
= (env
->sregs
[RASID
] >> ((pte
>> 1) & 0x18)) & 0xff;
797 entry
->attr
= pte
& 0xf;
800 void xtensa_tlb_set_entry(CPUXtensaState
*env
, bool dtlb
,
801 unsigned wi
, unsigned ei
, uint32_t vpn
, uint32_t pte
)
803 XtensaCPU
*cpu
= xtensa_env_get_cpu(env
);
804 CPUState
*cs
= CPU(cpu
);
805 xtensa_tlb_entry
*entry
= xtensa_tlb_get_entry(env
, dtlb
, wi
, ei
);
807 if (xtensa_option_enabled(env
->config
, XTENSA_OPTION_MMU
)) {
808 if (entry
->variable
) {
810 tlb_flush_page(cs
, entry
->vaddr
);
812 xtensa_tlb_set_entry_mmu(env
, entry
, dtlb
, wi
, ei
, vpn
, pte
);
813 tlb_flush_page(cs
, entry
->vaddr
);
815 qemu_log_mask(LOG_GUEST_ERROR
, "%s %d, %d, %d trying to set immutable entry\n",
816 __func__
, dtlb
, wi
, ei
);
819 tlb_flush_page(cs
, entry
->vaddr
);
820 if (xtensa_option_enabled(env
->config
,
821 XTENSA_OPTION_REGION_TRANSLATION
)) {
822 entry
->paddr
= pte
& REGION_PAGE_MASK
;
824 entry
->attr
= pte
& 0xf;
828 void HELPER(wtlb
)(CPUXtensaState
*env
, uint32_t p
, uint32_t v
, uint32_t dtlb
)
833 split_tlb_entry_spec(env
, v
, dtlb
, &vpn
, &wi
, &ei
);
834 xtensa_tlb_set_entry(env
, dtlb
, wi
, ei
, vpn
, p
);
838 void HELPER(wsr_ibreakenable
)(CPUXtensaState
*env
, uint32_t v
)
840 uint32_t change
= v
^ env
->sregs
[IBREAKENABLE
];
843 for (i
= 0; i
< env
->config
->nibreak
; ++i
) {
844 if (change
& (1 << i
)) {
845 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
848 env
->sregs
[IBREAKENABLE
] = v
& ((1 << env
->config
->nibreak
) - 1);
851 void HELPER(wsr_ibreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
853 if (env
->sregs
[IBREAKENABLE
] & (1 << i
) && env
->sregs
[IBREAKA
+ i
] != v
) {
854 tb_invalidate_virtual_addr(env
, env
->sregs
[IBREAKA
+ i
]);
855 tb_invalidate_virtual_addr(env
, v
);
857 env
->sregs
[IBREAKA
+ i
] = v
;
860 static void set_dbreak(CPUXtensaState
*env
, unsigned i
, uint32_t dbreaka
,
863 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
864 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
865 uint32_t mask
= dbreakc
| ~DBREAKC_MASK
;
867 if (env
->cpu_watchpoint
[i
]) {
868 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
870 if (dbreakc
& DBREAKC_SB
) {
871 flags
|= BP_MEM_WRITE
;
873 if (dbreakc
& DBREAKC_LB
) {
874 flags
|= BP_MEM_READ
;
876 /* contiguous mask after inversion is one less than some power of 2 */
877 if ((~mask
+ 1) & ~mask
) {
878 qemu_log_mask(LOG_GUEST_ERROR
, "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc
);
879 /* cut mask after the first zero bit */
880 mask
= 0xffffffff << (32 - clo32(mask
));
882 if (cpu_watchpoint_insert(cs
, dbreaka
& mask
, ~mask
+ 1,
883 flags
, &env
->cpu_watchpoint
[i
])) {
884 env
->cpu_watchpoint
[i
] = NULL
;
885 qemu_log_mask(LOG_GUEST_ERROR
, "Failed to set data breakpoint at 0x%08x/%d\n",
886 dbreaka
& mask
, ~mask
+ 1);
890 void HELPER(wsr_dbreaka
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
892 uint32_t dbreakc
= env
->sregs
[DBREAKC
+ i
];
894 if ((dbreakc
& DBREAKC_SB_LB
) &&
895 env
->sregs
[DBREAKA
+ i
] != v
) {
896 set_dbreak(env
, i
, v
, dbreakc
);
898 env
->sregs
[DBREAKA
+ i
] = v
;
901 void HELPER(wsr_dbreakc
)(CPUXtensaState
*env
, uint32_t i
, uint32_t v
)
903 if ((env
->sregs
[DBREAKC
+ i
] ^ v
) & (DBREAKC_SB_LB
| DBREAKC_MASK
)) {
904 if (v
& DBREAKC_SB_LB
) {
905 set_dbreak(env
, i
, env
->sregs
[DBREAKA
+ i
], v
);
907 if (env
->cpu_watchpoint
[i
]) {
908 CPUState
*cs
= CPU(xtensa_env_get_cpu(env
));
910 cpu_watchpoint_remove_by_ref(cs
, env
->cpu_watchpoint
[i
]);
911 env
->cpu_watchpoint
[i
] = NULL
;
915 env
->sregs
[DBREAKC
+ i
] = v
;
919 void HELPER(wur_fcr
)(CPUXtensaState
*env
, uint32_t v
)
921 static const int rounding_mode
[] = {
922 float_round_nearest_even
,
928 env
->uregs
[FCR
] = v
& 0xfffff07f;
929 set_float_rounding_mode(rounding_mode
[v
& 3], &env
->fp_status
);
932 float32
HELPER(abs_s
)(float32 v
)
934 return float32_abs(v
);
937 float32
HELPER(neg_s
)(float32 v
)
939 return float32_chs(v
);
942 float32
HELPER(add_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
944 return float32_add(a
, b
, &env
->fp_status
);
947 float32
HELPER(sub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
949 return float32_sub(a
, b
, &env
->fp_status
);
952 float32
HELPER(mul_s
)(CPUXtensaState
*env
, float32 a
, float32 b
)
954 return float32_mul(a
, b
, &env
->fp_status
);
957 float32
HELPER(madd_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
959 return float32_muladd(b
, c
, a
, 0,
963 float32
HELPER(msub_s
)(CPUXtensaState
*env
, float32 a
, float32 b
, float32 c
)
965 return float32_muladd(b
, c
, a
, float_muladd_negate_product
,
969 uint32_t HELPER(ftoi
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
971 float_status fp_status
= {0};
973 set_float_rounding_mode(rounding_mode
, &fp_status
);
974 return float32_to_int32(
975 float32_scalbn(v
, scale
, &fp_status
), &fp_status
);
978 uint32_t HELPER(ftoui
)(float32 v
, uint32_t rounding_mode
, uint32_t scale
)
980 float_status fp_status
= {0};
983 set_float_rounding_mode(rounding_mode
, &fp_status
);
985 res
= float32_scalbn(v
, scale
, &fp_status
);
987 if (float32_is_neg(v
) && !float32_is_any_nan(v
)) {
988 return float32_to_int32(res
, &fp_status
);
990 return float32_to_uint32(res
, &fp_status
);
994 float32
HELPER(itof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
996 return float32_scalbn(int32_to_float32(v
, &env
->fp_status
),
997 (int32_t)scale
, &env
->fp_status
);
1000 float32
HELPER(uitof
)(CPUXtensaState
*env
, uint32_t v
, uint32_t scale
)
1002 return float32_scalbn(uint32_to_float32(v
, &env
->fp_status
),
1003 (int32_t)scale
, &env
->fp_status
);
1006 static inline void set_br(CPUXtensaState
*env
, bool v
, uint32_t br
)
1009 env
->sregs
[BR
] |= br
;
1011 env
->sregs
[BR
] &= ~br
;
1015 void HELPER(un_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1017 set_br(env
, float32_unordered_quiet(a
, b
, &env
->fp_status
), br
);
1020 void HELPER(oeq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1022 set_br(env
, float32_eq_quiet(a
, b
, &env
->fp_status
), br
);
1025 void HELPER(ueq_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1027 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1028 set_br(env
, v
== float_relation_equal
|| v
== float_relation_unordered
, br
);
1031 void HELPER(olt_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1033 set_br(env
, float32_lt_quiet(a
, b
, &env
->fp_status
), br
);
1036 void HELPER(ult_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1038 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1039 set_br(env
, v
== float_relation_less
|| v
== float_relation_unordered
, br
);
1042 void HELPER(ole_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1044 set_br(env
, float32_le_quiet(a
, b
, &env
->fp_status
), br
);
1047 void HELPER(ule_s
)(CPUXtensaState
*env
, uint32_t br
, float32 a
, float32 b
)
1049 int v
= float32_compare_quiet(a
, b
, &env
->fp_status
);
1050 set_br(env
, v
!= float_relation_greater
, br
);
1053 uint32_t HELPER(rer
)(CPUXtensaState
*env
, uint32_t addr
)
1055 #ifndef CONFIG_USER_ONLY
1056 return address_space_ldl(env
->address_space_er
, addr
,
1057 MEMTXATTRS_UNSPECIFIED
, NULL
);
1063 void HELPER(wer
)(CPUXtensaState
*env
, uint32_t data
, uint32_t addr
)
1065 #ifndef CONFIG_USER_ONLY
1066 address_space_stl(env
->address_space_er
, addr
, data
,
1067 MEMTXATTRS_UNSPECIFIED
, NULL
);