target-s390x/misc_helper.c

   1 /*
   2  *  S/390 misc helper routines
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2009 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/memory.h"
  23 #include "qemu/host-utils.h"
  24 #include "exec/helper-proto.h"
  25 #include <string.h>
  26 #include "sysemu/kvm.h"
  27 #include "qemu/timer.h"
  28 #include "exec/address-spaces.h"
  29 #ifdef CONFIG_KVM
  30 #include <linux/kvm.h>
  31 #endif
  32 #include "exec/cpu_ldst.h"
  33
  34 #if !defined(CONFIG_USER_ONLY)
  35 #include "sysemu/cpus.h"
  36 #include "sysemu/sysemu.h"
  37 #include "hw/s390x/ebcdic.h"
  38 #include "hw/s390x/ipl.h"
  39 #endif
  40
  41 /* #define DEBUG_HELPER */
  42 #ifdef DEBUG_HELPER
  43 #define HELPER_LOG(x...) qemu_log(x)
  44 #else
  45 #define HELPER_LOG(x...)
  46 #endif
  47
  48 /* Raise an exception dynamically from a helper function.  */
  49 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
  50                                      uintptr_t retaddr)
  51 {
  52     CPUState *cs = CPU(s390_env_get_cpu(env));
  53     int t;
  54
  55     cs->exception_index = EXCP_PGM;
  56     env->int_pgm_code = excp;
  57
  58     /* Use the (ultimate) callers address to find the insn that trapped.  */
  59     cpu_restore_state(cs, retaddr);
  60
  61     /* Advance past the insn.  */
  62     t = cpu_ldub_code(env, env->psw.addr);
  63     env->int_pgm_ilen = t = get_ilen(t);
  64     env->psw.addr += 2 * t;
  65
  66     cpu_loop_exit(cs);
  67 }
  68
  69 /* Raise an exception statically from a TB.  */
  70 void HELPER(exception)(CPUS390XState *env, uint32_t excp)
  71 {
  72     CPUState *cs = CPU(s390_env_get_cpu(env));
  73
  74     HELPER_LOG("%s: exception %d\n", __func__, excp);
  75     cs->exception_index = excp;
  76     cpu_loop_exit(cs);
  77 }
  78
  79 #ifndef CONFIG_USER_ONLY
  80
  81 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
  82 {
  83     S390CPU *cpu = s390_env_get_cpu(env);
  84
  85     qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
  86                   env->psw.addr);
  87
  88     if (kvm_enabled()) {
  89 #ifdef CONFIG_KVM
  90         struct kvm_s390_irq irq = {
  91             .type = KVM_S390_PROGRAM_INT,
  92             .u.pgm.code = code,
  93         };
  94
  95         kvm_s390_vcpu_interrupt(cpu, &irq);
  96 #endif
  97     } else {
  98         CPUState *cs = CPU(cpu);
  99
 100         env->int_pgm_code = code;
 101         env->int_pgm_ilen = ilen;
 102         cs->exception_index = EXCP_PGM;
 103         cpu_loop_exit(cs);
 104     }
 105 }
 106
 107 /* SCLP service call */
 108 uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
 109 {
 110     int r = sclp_service_call(env, r1, r2);
 111     if (r < 0) {
 112         program_interrupt(env, -r, 4);
 113         return 0;
 114     }
 115     return r;
 116 }
 117
 118 #ifndef CONFIG_USER_ONLY
 119 static int modified_clear_reset(S390CPU *cpu)
 120 {
 121     S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
 122     CPUState *t;
 123
 124     pause_all_vcpus();
 125     cpu_synchronize_all_states();
 126     CPU_FOREACH(t) {
 127         run_on_cpu(t, s390_do_cpu_full_reset, t);
 128     }
 129     cmma_reset(cpu);
 130     io_subsystem_reset();
 131     scc->load_normal(CPU(cpu));
 132     cpu_synchronize_all_post_reset();
 133     resume_all_vcpus();
 134     return 0;
 135 }
 136
 137 static int load_normal_reset(S390CPU *cpu)
 138 {
 139     S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
 140     CPUState *t;
 141
 142     pause_all_vcpus();
 143     cpu_synchronize_all_states();
 144     CPU_FOREACH(t) {
 145         run_on_cpu(t, s390_do_cpu_reset, t);
 146     }
 147     cmma_reset(cpu);
 148     io_subsystem_reset();
 149     scc->initial_cpu_reset(CPU(cpu));
 150     scc->load_normal(CPU(cpu));
 151     cpu_synchronize_all_post_reset();
 152     resume_all_vcpus();
 153     return 0;
 154 }
 155
 156 #define DIAG_308_RC_OK              0x0001
 157 #define DIAG_308_RC_NO_CONF         0x0102
 158 #define DIAG_308_RC_INVALID         0x0402
 159
 160 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3)
 161 {
 162     uint64_t addr =  env->regs[r1];
 163     uint64_t subcode = env->regs[r3];
 164     IplParameterBlock *iplb;
 165
 166     if (env->psw.mask & PSW_MASK_PSTATE) {
 167         program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC);
 168         return;
 169     }
 170
 171     if ((subcode & ~0x0ffffULL) || (subcode > 6)) {
 172         program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
 173         return;
 174     }
 175
 176     switch (subcode) {
 177     case 0:
 178         modified_clear_reset(s390_env_get_cpu(env));
 179         break;
 180     case 1:
 181         load_normal_reset(s390_env_get_cpu(env));
 182         break;
 183     case 5:
 184         if ((r1 & 1) || (addr & 0x0fffULL)) {
 185             program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
 186             return;
 187         }
 188         if (!address_space_access_valid(&address_space_memory, addr,
 189                                         sizeof(IplParameterBlock), false)) {
 190             program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC);
 191             return;
 192         }
 193         iplb = g_malloc0(sizeof(struct IplParameterBlock));
 194         cpu_physical_memory_read(addr, iplb, sizeof(struct IplParameterBlock));
 195         if (!s390_ipl_update_diag308(iplb)) {
 196             env->regs[r1 + 1] = DIAG_308_RC_OK;
 197         } else {
 198             env->regs[r1 + 1] = DIAG_308_RC_INVALID;
 199         }
 200         g_free(iplb);
 201         return;
 202     case 6:
 203         if ((r1 & 1) || (addr & 0x0fffULL)) {
 204             program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
 205             return;
 206         }
 207         if (!address_space_access_valid(&address_space_memory, addr,
 208                                         sizeof(IplParameterBlock), true)) {
 209             program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC);
 210             return;
 211         }
 212         iplb = s390_ipl_get_iplb();
 213         if (iplb) {
 214             cpu_physical_memory_write(addr, iplb,
 215                                       sizeof(struct IplParameterBlock));
 216             env->regs[r1 + 1] = DIAG_308_RC_OK;
 217         } else {
 218             env->regs[r1 + 1] = DIAG_308_RC_NO_CONF;
 219         }
 220         return;
 221     default:
 222         hw_error("Unhandled diag308 subcode %" PRIx64, subcode);
 223         break;
 224     }
 225 }
 226 #endif
 227
 228 /* DIAG */
 229 uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
 230                       uint64_t code)
 231 {
 232     uint64_t r;
 233
 234     switch (num) {
 235     case 0x500:
 236         /* KVM hypercall */
 237         r = s390_virtio_hypercall(env);
 238         break;
 239     case 0x44:
 240         /* yield */
 241         r = 0;
 242         break;
 243     case 0x308:
 244         /* ipl */
 245         r = 0;
 246         break;
 247     default:
 248         r = -1;
 249         break;
 250     }
 251
 252     if (r) {
 253         program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
 254     }
 255
 256     return r;
 257 }
 258
 259 /* Set Prefix */
 260 void HELPER(spx)(CPUS390XState *env, uint64_t a1)
 261 {
 262     CPUState *cs = CPU(s390_env_get_cpu(env));
 263     uint32_t prefix = a1 & 0x7fffe000;
 264
 265     env->psa = prefix;
 266     qemu_log("prefix: %#x\n", prefix);
 267     tlb_flush_page(cs, 0);
 268     tlb_flush_page(cs, TARGET_PAGE_SIZE);
 269 }
 270
 271 static inline uint64_t clock_value(CPUS390XState *env)
 272 {
 273     uint64_t time;
 274
 275     time = env->tod_offset +
 276         time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - env->tod_basetime);
 277
 278     return time;
 279 }
 280
 281 /* Store Clock */
 282 uint64_t HELPER(stck)(CPUS390XState *env)
 283 {
 284     return clock_value(env);
 285 }
 286
 287 /* Set Clock Comparator */
 288 void HELPER(sckc)(CPUS390XState *env, uint64_t time)
 289 {
 290     if (time == -1ULL) {
 291         return;
 292     }
 293
 294     /* difference between now and then */
 295     time -= clock_value(env);
 296     /* nanoseconds */
 297     time = (time * 125) >> 9;
 298
 299     timer_mod(env->tod_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
 300 }
 301
 302 /* Store Clock Comparator */
 303 uint64_t HELPER(stckc)(CPUS390XState *env)
 304 {
 305     /* XXX implement */
 306     return 0;
 307 }
 308
 309 /* Set CPU Timer */
 310 void HELPER(spt)(CPUS390XState *env, uint64_t time)
 311 {
 312     if (time == -1ULL) {
 313         return;
 314     }
 315
 316     /* nanoseconds */
 317     time = (time * 125) >> 9;
 318
 319     timer_mod(env->cpu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time);
 320 }
 321
 322 /* Store CPU Timer */
 323 uint64_t HELPER(stpt)(CPUS390XState *env)
 324 {
 325     /* XXX implement */
 326     return 0;
 327 }
 328
 329 /* Store System Information */
 330 uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0,
 331                       uint64_t r0, uint64_t r1)
 332 {
 333     int cc = 0;
 334     int sel1, sel2;
 335
 336     if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
 337         ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
 338         /* valid function code, invalid reserved bits */
 339         program_interrupt(env, PGM_SPECIFICATION, 2);
 340     }
 341
 342     sel1 = r0 & STSI_R0_SEL1_MASK;
 343     sel2 = r1 & STSI_R1_SEL2_MASK;
 344
 345     /* XXX: spec exception if sysib is not 4k-aligned */
 346
 347     switch (r0 & STSI_LEVEL_MASK) {
 348     case STSI_LEVEL_1:
 349         if ((sel1 == 1) && (sel2 == 1)) {
 350             /* Basic Machine Configuration */
 351             struct sysib_111 sysib;
 352
 353             memset(&sysib, 0, sizeof(sysib));
 354             ebcdic_put(sysib.manuf, "QEMU            ", 16);
 355             /* same as machine type number in STORE CPU ID */
 356             ebcdic_put(sysib.type, "QEMU", 4);
 357             /* same as model number in STORE CPU ID */
 358             ebcdic_put(sysib.model, "QEMU            ", 16);
 359             ebcdic_put(sysib.sequence, "QEMU            ", 16);
 360             ebcdic_put(sysib.plant, "QEMU", 4);
 361             cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 362         } else if ((sel1 == 2) && (sel2 == 1)) {
 363             /* Basic Machine CPU */
 364             struct sysib_121 sysib;
 365
 366             memset(&sysib, 0, sizeof(sysib));
 367             /* XXX make different for different CPUs? */
 368             ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
 369             ebcdic_put(sysib.plant, "QEMU", 4);
 370             stw_p(&sysib.cpu_addr, env->cpu_num);
 371             cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 372         } else if ((sel1 == 2) && (sel2 == 2)) {
 373             /* Basic Machine CPUs */
 374             struct sysib_122 sysib;
 375
 376             memset(&sysib, 0, sizeof(sysib));
 377             stl_p(&sysib.capability, 0x443afc29);
 378             /* XXX change when SMP comes */
 379             stw_p(&sysib.total_cpus, 1);
 380             stw_p(&sysib.active_cpus, 1);
 381             stw_p(&sysib.standby_cpus, 0);
 382             stw_p(&sysib.reserved_cpus, 0);
 383             cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 384         } else {
 385             cc = 3;
 386         }
 387         break;
 388     case STSI_LEVEL_2:
 389         {
 390             if ((sel1 == 2) && (sel2 == 1)) {
 391                 /* LPAR CPU */
 392                 struct sysib_221 sysib;
 393
 394                 memset(&sysib, 0, sizeof(sysib));
 395                 /* XXX make different for different CPUs? */
 396                 ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
 397                 ebcdic_put(sysib.plant, "QEMU", 4);
 398                 stw_p(&sysib.cpu_addr, env->cpu_num);
 399                 stw_p(&sysib.cpu_id, 0);
 400                 cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 401             } else if ((sel1 == 2) && (sel2 == 2)) {
 402                 /* LPAR CPUs */
 403                 struct sysib_222 sysib;
 404
 405                 memset(&sysib, 0, sizeof(sysib));
 406                 stw_p(&sysib.lpar_num, 0);
 407                 sysib.lcpuc = 0;
 408                 /* XXX change when SMP comes */
 409                 stw_p(&sysib.total_cpus, 1);
 410                 stw_p(&sysib.conf_cpus, 1);
 411                 stw_p(&sysib.standby_cpus, 0);
 412                 stw_p(&sysib.reserved_cpus, 0);
 413                 ebcdic_put(sysib.name, "QEMU    ", 8);
 414                 stl_p(&sysib.caf, 1000);
 415                 stw_p(&sysib.dedicated_cpus, 0);
 416                 stw_p(&sysib.shared_cpus, 0);
 417                 cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 418             } else {
 419                 cc = 3;
 420             }
 421             break;
 422         }
 423     case STSI_LEVEL_3:
 424         {
 425             if ((sel1 == 2) && (sel2 == 2)) {
 426                 /* VM CPUs */
 427                 struct sysib_322 sysib;
 428
 429                 memset(&sysib, 0, sizeof(sysib));
 430                 sysib.count = 1;
 431                 /* XXX change when SMP comes */
 432                 stw_p(&sysib.vm[0].total_cpus, 1);
 433                 stw_p(&sysib.vm[0].conf_cpus, 1);
 434                 stw_p(&sysib.vm[0].standby_cpus, 0);
 435                 stw_p(&sysib.vm[0].reserved_cpus, 0);
 436                 ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
 437                 stl_p(&sysib.vm[0].caf, 1000);
 438                 ebcdic_put(sysib.vm[0].cpi, "KVM/Linux       ", 16);
 439                 cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
 440             } else {
 441                 cc = 3;
 442             }
 443             break;
 444         }
 445     case STSI_LEVEL_CURRENT:
 446         env->regs[0] = STSI_LEVEL_3;
 447         break;
 448     default:
 449         cc = 3;
 450         break;
 451     }
 452
 453     return cc;
 454 }
 455
 456 uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
 457                       uint64_t cpu_addr)
 458 {
 459     int cc = SIGP_CC_ORDER_CODE_ACCEPTED;
 460
 461     HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
 462                __func__, order_code, r1, cpu_addr);
 463
 464     /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
 465        as parameter (input). Status (output) is always R1. */
 466
 467     switch (order_code) {
 468     case SIGP_SET_ARCH:
 469         /* switch arch */
 470         break;
 471     case SIGP_SENSE:
 472         /* enumerate CPU status */
 473         if (cpu_addr) {
 474             /* XXX implement when SMP comes */
 475             return 3;
 476         }
 477         env->regs[r1] &= 0xffffffff00000000ULL;
 478         cc = 1;
 479         break;
 480 #if !defined(CONFIG_USER_ONLY)
 481     case SIGP_RESTART:
 482         qemu_system_reset_request();
 483         cpu_loop_exit(CPU(s390_env_get_cpu(env)));
 484         break;
 485     case SIGP_STOP:
 486         qemu_system_shutdown_request();
 487         cpu_loop_exit(CPU(s390_env_get_cpu(env)));
 488         break;
 489 #endif
 490     default:
 491         /* unknown sigp */
 492         fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
 493         cc = SIGP_CC_NOT_OPERATIONAL;
 494     }
 495
 496     return cc;
 497 }
 498 #endif