target-tricore: add CMPSWP instructions of the v1.6.1 ISA
[qemu.git] / target-arm / cpu.c
blob3ca3fa8d218db578a3bd4e81c0c6b772c6c71cf6
1 /*
2 * QEMU ARM CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "cpu.h"
22 #include "internals.h"
23 #include "qemu-common.h"
24 #include "hw/qdev-properties.h"
25 #include "qapi/qmp/qerror.h"
26 #if !defined(CONFIG_USER_ONLY)
27 #include "hw/loader.h"
28 #endif
29 #include "hw/arm/arm.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_arm.h"
34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
36 ARMCPU *cpu = ARM_CPU(cs);
38 cpu->env.regs[15] = value;
41 static bool arm_cpu_has_work(CPUState *cs)
43 ARMCPU *cpu = ARM_CPU(cs);
45 return !cpu->powered_off
46 && cs->interrupt_request &
47 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
48 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
49 | CPU_INTERRUPT_EXITTB);
52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
54 /* Reset a single ARMCPRegInfo register */
55 ARMCPRegInfo *ri = value;
56 ARMCPU *cpu = opaque;
58 if (ri->type & ARM_CP_SPECIAL) {
59 return;
62 if (ri->resetfn) {
63 ri->resetfn(&cpu->env, ri);
64 return;
67 /* A zero offset is never possible as it would be regs[0]
68 * so we use it to indicate that reset is being handled elsewhere.
69 * This is basically only used for fields in non-core coprocessors
70 * (like the pxa2xx ones).
72 if (!ri->fieldoffset) {
73 return;
76 if (cpreg_field_is_64bit(ri)) {
77 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
78 } else {
79 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
83 /* CPUClass::reset() */
84 static void arm_cpu_reset(CPUState *s)
86 ARMCPU *cpu = ARM_CPU(s);
87 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
88 CPUARMState *env = &cpu->env;
90 acc->parent_reset(s);
92 memset(env, 0, offsetof(CPUARMState, features));
93 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
94 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
95 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
96 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
97 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
99 cpu->powered_off = cpu->start_powered_off;
100 s->halted = cpu->start_powered_off;
102 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
103 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
106 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
107 /* 64 bit CPUs always start in 64 bit mode */
108 env->aarch64 = 1;
109 #if defined(CONFIG_USER_ONLY)
110 env->pstate = PSTATE_MODE_EL0t;
111 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
112 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
113 /* and to the FP/Neon instructions */
114 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
115 #else
116 /* Reset into the highest available EL */
117 if (arm_feature(env, ARM_FEATURE_EL3)) {
118 env->pstate = PSTATE_MODE_EL3h;
119 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
120 env->pstate = PSTATE_MODE_EL2h;
121 } else {
122 env->pstate = PSTATE_MODE_EL1h;
124 env->pc = cpu->rvbar;
125 #endif
126 } else {
127 #if defined(CONFIG_USER_ONLY)
128 /* Userspace expects access to cp10 and cp11 for FP/Neon */
129 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
130 #endif
133 #if defined(CONFIG_USER_ONLY)
134 env->uncached_cpsr = ARM_CPU_MODE_USR;
135 /* For user mode we must enable access to coprocessors */
136 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
137 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
138 env->cp15.c15_cpar = 3;
139 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
140 env->cp15.c15_cpar = 1;
142 #else
143 /* SVC mode with interrupts disabled. */
144 env->uncached_cpsr = ARM_CPU_MODE_SVC;
145 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
146 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
147 * clear at reset. Initial SP and PC are loaded from ROM.
149 if (IS_M(env)) {
150 uint32_t initial_msp; /* Loaded from 0x0 */
151 uint32_t initial_pc; /* Loaded from 0x4 */
152 uint8_t *rom;
154 env->daif &= ~PSTATE_I;
155 rom = rom_ptr(0);
156 if (rom) {
157 /* Address zero is covered by ROM which hasn't yet been
158 * copied into physical memory.
160 initial_msp = ldl_p(rom);
161 initial_pc = ldl_p(rom + 4);
162 } else {
163 /* Address zero not covered by a ROM blob, or the ROM blob
164 * is in non-modifiable memory and this is a second reset after
165 * it got copied into memory. In the latter case, rom_ptr
166 * will return a NULL pointer and we should use ldl_phys instead.
168 initial_msp = ldl_phys(s->as, 0);
169 initial_pc = ldl_phys(s->as, 4);
172 env->regs[13] = initial_msp & 0xFFFFFFFC;
173 env->regs[15] = initial_pc & ~1;
174 env->thumb = initial_pc & 1;
177 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
178 * executing as AArch32 then check if highvecs are enabled and
179 * adjust the PC accordingly.
181 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
182 env->regs[15] = 0xFFFF0000;
185 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
186 #endif
187 set_flush_to_zero(1, &env->vfp.standard_fp_status);
188 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
189 set_default_nan_mode(1, &env->vfp.standard_fp_status);
190 set_float_detect_tininess(float_tininess_before_rounding,
191 &env->vfp.fp_status);
192 set_float_detect_tininess(float_tininess_before_rounding,
193 &env->vfp.standard_fp_status);
194 tlb_flush(s, 1);
196 #ifndef CONFIG_USER_ONLY
197 if (kvm_enabled()) {
198 kvm_arm_reset_vcpu(cpu);
200 #endif
202 hw_breakpoint_update_all(cpu);
203 hw_watchpoint_update_all(cpu);
206 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
208 CPUClass *cc = CPU_GET_CLASS(cs);
209 bool ret = false;
211 if (interrupt_request & CPU_INTERRUPT_FIQ
212 && arm_excp_unmasked(cs, EXCP_FIQ)) {
213 cs->exception_index = EXCP_FIQ;
214 cc->do_interrupt(cs);
215 ret = true;
217 if (interrupt_request & CPU_INTERRUPT_HARD
218 && arm_excp_unmasked(cs, EXCP_IRQ)) {
219 cs->exception_index = EXCP_IRQ;
220 cc->do_interrupt(cs);
221 ret = true;
223 if (interrupt_request & CPU_INTERRUPT_VIRQ
224 && arm_excp_unmasked(cs, EXCP_VIRQ)) {
225 cs->exception_index = EXCP_VIRQ;
226 cc->do_interrupt(cs);
227 ret = true;
229 if (interrupt_request & CPU_INTERRUPT_VFIQ
230 && arm_excp_unmasked(cs, EXCP_VFIQ)) {
231 cs->exception_index = EXCP_VFIQ;
232 cc->do_interrupt(cs);
233 ret = true;
236 return ret;
239 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
240 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
242 CPUClass *cc = CPU_GET_CLASS(cs);
243 ARMCPU *cpu = ARM_CPU(cs);
244 CPUARMState *env = &cpu->env;
245 bool ret = false;
248 if (interrupt_request & CPU_INTERRUPT_FIQ
249 && !(env->daif & PSTATE_F)) {
250 cs->exception_index = EXCP_FIQ;
251 cc->do_interrupt(cs);
252 ret = true;
254 /* ARMv7-M interrupt return works by loading a magic value
255 * into the PC. On real hardware the load causes the
256 * return to occur. The qemu implementation performs the
257 * jump normally, then does the exception return when the
258 * CPU tries to execute code at the magic address.
259 * This will cause the magic PC value to be pushed to
260 * the stack if an interrupt occurred at the wrong time.
261 * We avoid this by disabling interrupts when
262 * pc contains a magic address.
264 if (interrupt_request & CPU_INTERRUPT_HARD
265 && !(env->daif & PSTATE_I)
266 && (env->regs[15] < 0xfffffff0)) {
267 cs->exception_index = EXCP_IRQ;
268 cc->do_interrupt(cs);
269 ret = true;
271 return ret;
273 #endif
275 #ifndef CONFIG_USER_ONLY
276 static void arm_cpu_set_irq(void *opaque, int irq, int level)
278 ARMCPU *cpu = opaque;
279 CPUARMState *env = &cpu->env;
280 CPUState *cs = CPU(cpu);
281 static const int mask[] = {
282 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
283 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
284 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
285 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
288 switch (irq) {
289 case ARM_CPU_VIRQ:
290 case ARM_CPU_VFIQ:
291 if (!arm_feature(env, ARM_FEATURE_EL2)) {
292 hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
293 __func__, irq);
295 /* fall through */
296 case ARM_CPU_IRQ:
297 case ARM_CPU_FIQ:
298 if (level) {
299 cpu_interrupt(cs, mask[irq]);
300 } else {
301 cpu_reset_interrupt(cs, mask[irq]);
303 break;
304 default:
305 hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
309 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
311 #ifdef CONFIG_KVM
312 ARMCPU *cpu = opaque;
313 CPUState *cs = CPU(cpu);
314 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
316 switch (irq) {
317 case ARM_CPU_IRQ:
318 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
319 break;
320 case ARM_CPU_FIQ:
321 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
322 break;
323 default:
324 hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
326 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
327 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
328 #endif
331 static bool arm_cpu_is_big_endian(CPUState *cs)
333 ARMCPU *cpu = ARM_CPU(cs);
334 CPUARMState *env = &cpu->env;
335 int cur_el;
337 cpu_synchronize_state(cs);
339 /* In 32bit guest endianness is determined by looking at CPSR's E bit */
340 if (!is_a64(env)) {
341 return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
344 cur_el = arm_current_el(env);
346 if (cur_el == 0) {
347 return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
350 return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
353 #endif
355 static inline void set_feature(CPUARMState *env, int feature)
357 env->features |= 1ULL << feature;
360 static inline void unset_feature(CPUARMState *env, int feature)
362 env->features &= ~(1ULL << feature);
365 static void arm_cpu_initfn(Object *obj)
367 CPUState *cs = CPU(obj);
368 ARMCPU *cpu = ARM_CPU(obj);
369 static bool inited;
371 cs->env_ptr = &cpu->env;
372 cpu_exec_init(&cpu->env);
373 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
374 g_free, g_free);
376 #ifndef CONFIG_USER_ONLY
377 /* Our inbound IRQ and FIQ lines */
378 if (kvm_enabled()) {
379 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
380 * the same interface as non-KVM CPUs.
382 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
383 } else {
384 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
387 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
388 arm_gt_ptimer_cb, cpu);
389 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
390 arm_gt_vtimer_cb, cpu);
391 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
392 ARRAY_SIZE(cpu->gt_timer_outputs));
393 #endif
395 /* DTB consumers generally don't in fact care what the 'compatible'
396 * string is, so always provide some string and trust that a hypothetical
397 * picky DTB consumer will also provide a helpful error message.
399 cpu->dtb_compatible = "qemu,unknown";
400 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
401 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
403 if (tcg_enabled()) {
404 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
405 if (!inited) {
406 inited = true;
407 arm_translate_init();
412 static Property arm_cpu_reset_cbar_property =
413 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
415 static Property arm_cpu_reset_hivecs_property =
416 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
418 static Property arm_cpu_rvbar_property =
419 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
421 static Property arm_cpu_has_el3_property =
422 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
424 static void arm_cpu_post_init(Object *obj)
426 ARMCPU *cpu = ARM_CPU(obj);
428 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
429 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
430 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
431 &error_abort);
434 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
435 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
436 &error_abort);
439 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
440 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
441 &error_abort);
444 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
445 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
446 * prevent "has_el3" from existing on CPUs which cannot support EL3.
448 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
449 &error_abort);
453 static void arm_cpu_finalizefn(Object *obj)
455 ARMCPU *cpu = ARM_CPU(obj);
456 g_hash_table_destroy(cpu->cp_regs);
459 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
461 CPUState *cs = CPU(dev);
462 ARMCPU *cpu = ARM_CPU(dev);
463 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
464 CPUARMState *env = &cpu->env;
466 /* Some features automatically imply others: */
467 if (arm_feature(env, ARM_FEATURE_V8)) {
468 set_feature(env, ARM_FEATURE_V7);
469 set_feature(env, ARM_FEATURE_ARM_DIV);
470 set_feature(env, ARM_FEATURE_LPAE);
472 if (arm_feature(env, ARM_FEATURE_V7)) {
473 set_feature(env, ARM_FEATURE_VAPA);
474 set_feature(env, ARM_FEATURE_THUMB2);
475 set_feature(env, ARM_FEATURE_MPIDR);
476 if (!arm_feature(env, ARM_FEATURE_M)) {
477 set_feature(env, ARM_FEATURE_V6K);
478 } else {
479 set_feature(env, ARM_FEATURE_V6);
482 if (arm_feature(env, ARM_FEATURE_V6K)) {
483 set_feature(env, ARM_FEATURE_V6);
484 set_feature(env, ARM_FEATURE_MVFR);
486 if (arm_feature(env, ARM_FEATURE_V6)) {
487 set_feature(env, ARM_FEATURE_V5);
488 if (!arm_feature(env, ARM_FEATURE_M)) {
489 set_feature(env, ARM_FEATURE_AUXCR);
492 if (arm_feature(env, ARM_FEATURE_V5)) {
493 set_feature(env, ARM_FEATURE_V4T);
495 if (arm_feature(env, ARM_FEATURE_M)) {
496 set_feature(env, ARM_FEATURE_THUMB_DIV);
498 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
499 set_feature(env, ARM_FEATURE_THUMB_DIV);
501 if (arm_feature(env, ARM_FEATURE_VFP4)) {
502 set_feature(env, ARM_FEATURE_VFP3);
503 set_feature(env, ARM_FEATURE_VFP_FP16);
505 if (arm_feature(env, ARM_FEATURE_VFP3)) {
506 set_feature(env, ARM_FEATURE_VFP);
508 if (arm_feature(env, ARM_FEATURE_LPAE)) {
509 set_feature(env, ARM_FEATURE_V7MP);
510 set_feature(env, ARM_FEATURE_PXN);
512 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
513 set_feature(env, ARM_FEATURE_CBAR);
516 if (cpu->reset_hivecs) {
517 cpu->reset_sctlr |= (1 << 13);
520 if (!cpu->has_el3) {
521 /* If the has_el3 CPU property is disabled then we need to disable the
522 * feature.
524 unset_feature(env, ARM_FEATURE_EL3);
526 /* Disable the security extension feature bits in the processor feature
527 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
529 cpu->id_pfr1 &= ~0xf0;
530 cpu->id_aa64pfr0 &= ~0xf000;
533 register_cp_regs_for_features(cpu);
534 arm_cpu_register_gdb_regs_for_features(cpu);
536 init_cpreg_list(cpu);
538 qemu_init_vcpu(cs);
539 cpu_reset(cs);
541 acc->parent_realize(dev, errp);
544 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
546 ObjectClass *oc;
547 char *typename;
548 char **cpuname;
550 if (!cpu_model) {
551 return NULL;
554 cpuname = g_strsplit(cpu_model, ",", 1);
555 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
556 oc = object_class_by_name(typename);
557 g_strfreev(cpuname);
558 g_free(typename);
559 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
560 object_class_is_abstract(oc)) {
561 return NULL;
563 return oc;
566 /* CPU models. These are not needed for the AArch64 linux-user build. */
567 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
569 static void arm926_initfn(Object *obj)
571 ARMCPU *cpu = ARM_CPU(obj);
573 cpu->dtb_compatible = "arm,arm926";
574 set_feature(&cpu->env, ARM_FEATURE_V5);
575 set_feature(&cpu->env, ARM_FEATURE_VFP);
576 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
577 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
578 cpu->midr = 0x41069265;
579 cpu->reset_fpsid = 0x41011090;
580 cpu->ctr = 0x1dd20d2;
581 cpu->reset_sctlr = 0x00090078;
584 static void arm946_initfn(Object *obj)
586 ARMCPU *cpu = ARM_CPU(obj);
588 cpu->dtb_compatible = "arm,arm946";
589 set_feature(&cpu->env, ARM_FEATURE_V5);
590 set_feature(&cpu->env, ARM_FEATURE_MPU);
591 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
592 cpu->midr = 0x41059461;
593 cpu->ctr = 0x0f004006;
594 cpu->reset_sctlr = 0x00000078;
597 static void arm1026_initfn(Object *obj)
599 ARMCPU *cpu = ARM_CPU(obj);
601 cpu->dtb_compatible = "arm,arm1026";
602 set_feature(&cpu->env, ARM_FEATURE_V5);
603 set_feature(&cpu->env, ARM_FEATURE_VFP);
604 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
605 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
606 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
607 cpu->midr = 0x4106a262;
608 cpu->reset_fpsid = 0x410110a0;
609 cpu->ctr = 0x1dd20d2;
610 cpu->reset_sctlr = 0x00090078;
611 cpu->reset_auxcr = 1;
613 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
614 ARMCPRegInfo ifar = {
615 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
616 .access = PL1_RW,
617 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
618 .resetvalue = 0
620 define_one_arm_cp_reg(cpu, &ifar);
624 static void arm1136_r2_initfn(Object *obj)
626 ARMCPU *cpu = ARM_CPU(obj);
627 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
628 * older core than plain "arm1136". In particular this does not
629 * have the v6K features.
630 * These ID register values are correct for 1136 but may be wrong
631 * for 1136_r2 (in particular r0p2 does not actually implement most
632 * of the ID registers).
635 cpu->dtb_compatible = "arm,arm1136";
636 set_feature(&cpu->env, ARM_FEATURE_V6);
637 set_feature(&cpu->env, ARM_FEATURE_VFP);
638 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
639 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
640 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
641 cpu->midr = 0x4107b362;
642 cpu->reset_fpsid = 0x410120b4;
643 cpu->mvfr0 = 0x11111111;
644 cpu->mvfr1 = 0x00000000;
645 cpu->ctr = 0x1dd20d2;
646 cpu->reset_sctlr = 0x00050078;
647 cpu->id_pfr0 = 0x111;
648 cpu->id_pfr1 = 0x1;
649 cpu->id_dfr0 = 0x2;
650 cpu->id_afr0 = 0x3;
651 cpu->id_mmfr0 = 0x01130003;
652 cpu->id_mmfr1 = 0x10030302;
653 cpu->id_mmfr2 = 0x01222110;
654 cpu->id_isar0 = 0x00140011;
655 cpu->id_isar1 = 0x12002111;
656 cpu->id_isar2 = 0x11231111;
657 cpu->id_isar3 = 0x01102131;
658 cpu->id_isar4 = 0x141;
659 cpu->reset_auxcr = 7;
662 static void arm1136_initfn(Object *obj)
664 ARMCPU *cpu = ARM_CPU(obj);
666 cpu->dtb_compatible = "arm,arm1136";
667 set_feature(&cpu->env, ARM_FEATURE_V6K);
668 set_feature(&cpu->env, ARM_FEATURE_V6);
669 set_feature(&cpu->env, ARM_FEATURE_VFP);
670 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
671 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
672 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
673 cpu->midr = 0x4117b363;
674 cpu->reset_fpsid = 0x410120b4;
675 cpu->mvfr0 = 0x11111111;
676 cpu->mvfr1 = 0x00000000;
677 cpu->ctr = 0x1dd20d2;
678 cpu->reset_sctlr = 0x00050078;
679 cpu->id_pfr0 = 0x111;
680 cpu->id_pfr1 = 0x1;
681 cpu->id_dfr0 = 0x2;
682 cpu->id_afr0 = 0x3;
683 cpu->id_mmfr0 = 0x01130003;
684 cpu->id_mmfr1 = 0x10030302;
685 cpu->id_mmfr2 = 0x01222110;
686 cpu->id_isar0 = 0x00140011;
687 cpu->id_isar1 = 0x12002111;
688 cpu->id_isar2 = 0x11231111;
689 cpu->id_isar3 = 0x01102131;
690 cpu->id_isar4 = 0x141;
691 cpu->reset_auxcr = 7;
694 static void arm1176_initfn(Object *obj)
696 ARMCPU *cpu = ARM_CPU(obj);
698 cpu->dtb_compatible = "arm,arm1176";
699 set_feature(&cpu->env, ARM_FEATURE_V6K);
700 set_feature(&cpu->env, ARM_FEATURE_VFP);
701 set_feature(&cpu->env, ARM_FEATURE_VAPA);
702 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
703 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
704 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
705 set_feature(&cpu->env, ARM_FEATURE_EL3);
706 cpu->midr = 0x410fb767;
707 cpu->reset_fpsid = 0x410120b5;
708 cpu->mvfr0 = 0x11111111;
709 cpu->mvfr1 = 0x00000000;
710 cpu->ctr = 0x1dd20d2;
711 cpu->reset_sctlr = 0x00050078;
712 cpu->id_pfr0 = 0x111;
713 cpu->id_pfr1 = 0x11;
714 cpu->id_dfr0 = 0x33;
715 cpu->id_afr0 = 0;
716 cpu->id_mmfr0 = 0x01130003;
717 cpu->id_mmfr1 = 0x10030302;
718 cpu->id_mmfr2 = 0x01222100;
719 cpu->id_isar0 = 0x0140011;
720 cpu->id_isar1 = 0x12002111;
721 cpu->id_isar2 = 0x11231121;
722 cpu->id_isar3 = 0x01102131;
723 cpu->id_isar4 = 0x01141;
724 cpu->reset_auxcr = 7;
727 static void arm11mpcore_initfn(Object *obj)
729 ARMCPU *cpu = ARM_CPU(obj);
731 cpu->dtb_compatible = "arm,arm11mpcore";
732 set_feature(&cpu->env, ARM_FEATURE_V6K);
733 set_feature(&cpu->env, ARM_FEATURE_VFP);
734 set_feature(&cpu->env, ARM_FEATURE_VAPA);
735 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
736 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
737 cpu->midr = 0x410fb022;
738 cpu->reset_fpsid = 0x410120b4;
739 cpu->mvfr0 = 0x11111111;
740 cpu->mvfr1 = 0x00000000;
741 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
742 cpu->id_pfr0 = 0x111;
743 cpu->id_pfr1 = 0x1;
744 cpu->id_dfr0 = 0;
745 cpu->id_afr0 = 0x2;
746 cpu->id_mmfr0 = 0x01100103;
747 cpu->id_mmfr1 = 0x10020302;
748 cpu->id_mmfr2 = 0x01222000;
749 cpu->id_isar0 = 0x00100011;
750 cpu->id_isar1 = 0x12002111;
751 cpu->id_isar2 = 0x11221011;
752 cpu->id_isar3 = 0x01102131;
753 cpu->id_isar4 = 0x141;
754 cpu->reset_auxcr = 1;
757 static void cortex_m3_initfn(Object *obj)
759 ARMCPU *cpu = ARM_CPU(obj);
760 set_feature(&cpu->env, ARM_FEATURE_V7);
761 set_feature(&cpu->env, ARM_FEATURE_M);
762 cpu->midr = 0x410fc231;
765 static void arm_v7m_class_init(ObjectClass *oc, void *data)
767 CPUClass *cc = CPU_CLASS(oc);
769 #ifndef CONFIG_USER_ONLY
770 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
771 #endif
773 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
776 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
777 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
778 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
779 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
780 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
781 REGINFO_SENTINEL
784 static void cortex_a8_initfn(Object *obj)
786 ARMCPU *cpu = ARM_CPU(obj);
788 cpu->dtb_compatible = "arm,cortex-a8";
789 set_feature(&cpu->env, ARM_FEATURE_V7);
790 set_feature(&cpu->env, ARM_FEATURE_VFP3);
791 set_feature(&cpu->env, ARM_FEATURE_NEON);
792 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
793 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
794 set_feature(&cpu->env, ARM_FEATURE_EL3);
795 cpu->midr = 0x410fc080;
796 cpu->reset_fpsid = 0x410330c0;
797 cpu->mvfr0 = 0x11110222;
798 cpu->mvfr1 = 0x00011100;
799 cpu->ctr = 0x82048004;
800 cpu->reset_sctlr = 0x00c50078;
801 cpu->id_pfr0 = 0x1031;
802 cpu->id_pfr1 = 0x11;
803 cpu->id_dfr0 = 0x400;
804 cpu->id_afr0 = 0;
805 cpu->id_mmfr0 = 0x31100003;
806 cpu->id_mmfr1 = 0x20000000;
807 cpu->id_mmfr2 = 0x01202000;
808 cpu->id_mmfr3 = 0x11;
809 cpu->id_isar0 = 0x00101111;
810 cpu->id_isar1 = 0x12112111;
811 cpu->id_isar2 = 0x21232031;
812 cpu->id_isar3 = 0x11112131;
813 cpu->id_isar4 = 0x00111142;
814 cpu->dbgdidr = 0x15141000;
815 cpu->clidr = (1 << 27) | (2 << 24) | 3;
816 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
817 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
818 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
819 cpu->reset_auxcr = 2;
820 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
823 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
824 /* power_control should be set to maximum latency. Again,
825 * default to 0 and set by private hook
827 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
828 .access = PL1_RW, .resetvalue = 0,
829 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
830 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
831 .access = PL1_RW, .resetvalue = 0,
832 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
833 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
834 .access = PL1_RW, .resetvalue = 0,
835 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
836 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
837 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
838 /* TLB lockdown control */
839 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
840 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
841 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
842 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
843 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
844 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
845 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
846 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
847 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
848 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
849 REGINFO_SENTINEL
852 static void cortex_a9_initfn(Object *obj)
854 ARMCPU *cpu = ARM_CPU(obj);
856 cpu->dtb_compatible = "arm,cortex-a9";
857 set_feature(&cpu->env, ARM_FEATURE_V7);
858 set_feature(&cpu->env, ARM_FEATURE_VFP3);
859 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
860 set_feature(&cpu->env, ARM_FEATURE_NEON);
861 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
862 set_feature(&cpu->env, ARM_FEATURE_EL3);
863 /* Note that A9 supports the MP extensions even for
864 * A9UP and single-core A9MP (which are both different
865 * and valid configurations; we don't model A9UP).
867 set_feature(&cpu->env, ARM_FEATURE_V7MP);
868 set_feature(&cpu->env, ARM_FEATURE_CBAR);
869 cpu->midr = 0x410fc090;
870 cpu->reset_fpsid = 0x41033090;
871 cpu->mvfr0 = 0x11110222;
872 cpu->mvfr1 = 0x01111111;
873 cpu->ctr = 0x80038003;
874 cpu->reset_sctlr = 0x00c50078;
875 cpu->id_pfr0 = 0x1031;
876 cpu->id_pfr1 = 0x11;
877 cpu->id_dfr0 = 0x000;
878 cpu->id_afr0 = 0;
879 cpu->id_mmfr0 = 0x00100103;
880 cpu->id_mmfr1 = 0x20000000;
881 cpu->id_mmfr2 = 0x01230000;
882 cpu->id_mmfr3 = 0x00002111;
883 cpu->id_isar0 = 0x00101111;
884 cpu->id_isar1 = 0x13112111;
885 cpu->id_isar2 = 0x21232041;
886 cpu->id_isar3 = 0x11112131;
887 cpu->id_isar4 = 0x00111142;
888 cpu->dbgdidr = 0x35141000;
889 cpu->clidr = (1 << 27) | (1 << 24) | 3;
890 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
891 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
892 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
895 #ifndef CONFIG_USER_ONLY
896 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
898 /* Linux wants the number of processors from here.
899 * Might as well set the interrupt-controller bit too.
901 return ((smp_cpus - 1) << 24) | (1 << 23);
903 #endif
905 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
906 #ifndef CONFIG_USER_ONLY
907 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
908 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
909 .writefn = arm_cp_write_ignore, },
910 #endif
911 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
912 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
913 REGINFO_SENTINEL
916 static void cortex_a15_initfn(Object *obj)
918 ARMCPU *cpu = ARM_CPU(obj);
920 cpu->dtb_compatible = "arm,cortex-a15";
921 set_feature(&cpu->env, ARM_FEATURE_V7);
922 set_feature(&cpu->env, ARM_FEATURE_VFP4);
923 set_feature(&cpu->env, ARM_FEATURE_NEON);
924 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
925 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
926 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
927 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
928 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
929 set_feature(&cpu->env, ARM_FEATURE_LPAE);
930 set_feature(&cpu->env, ARM_FEATURE_EL3);
931 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
932 cpu->midr = 0x412fc0f1;
933 cpu->reset_fpsid = 0x410430f0;
934 cpu->mvfr0 = 0x10110222;
935 cpu->mvfr1 = 0x11111111;
936 cpu->ctr = 0x8444c004;
937 cpu->reset_sctlr = 0x00c50078;
938 cpu->id_pfr0 = 0x00001131;
939 cpu->id_pfr1 = 0x00011011;
940 cpu->id_dfr0 = 0x02010555;
941 cpu->id_afr0 = 0x00000000;
942 cpu->id_mmfr0 = 0x10201105;
943 cpu->id_mmfr1 = 0x20000000;
944 cpu->id_mmfr2 = 0x01240000;
945 cpu->id_mmfr3 = 0x02102211;
946 cpu->id_isar0 = 0x02101110;
947 cpu->id_isar1 = 0x13112111;
948 cpu->id_isar2 = 0x21232041;
949 cpu->id_isar3 = 0x11112131;
950 cpu->id_isar4 = 0x10011142;
951 cpu->dbgdidr = 0x3515f021;
952 cpu->clidr = 0x0a200023;
953 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
954 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
955 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
956 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
959 static void ti925t_initfn(Object *obj)
961 ARMCPU *cpu = ARM_CPU(obj);
962 set_feature(&cpu->env, ARM_FEATURE_V4T);
963 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
964 cpu->midr = ARM_CPUID_TI925T;
965 cpu->ctr = 0x5109149;
966 cpu->reset_sctlr = 0x00000070;
969 static void sa1100_initfn(Object *obj)
971 ARMCPU *cpu = ARM_CPU(obj);
973 cpu->dtb_compatible = "intel,sa1100";
974 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
975 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
976 cpu->midr = 0x4401A11B;
977 cpu->reset_sctlr = 0x00000070;
980 static void sa1110_initfn(Object *obj)
982 ARMCPU *cpu = ARM_CPU(obj);
983 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
984 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
985 cpu->midr = 0x6901B119;
986 cpu->reset_sctlr = 0x00000070;
989 static void pxa250_initfn(Object *obj)
991 ARMCPU *cpu = ARM_CPU(obj);
993 cpu->dtb_compatible = "marvell,xscale";
994 set_feature(&cpu->env, ARM_FEATURE_V5);
995 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
996 cpu->midr = 0x69052100;
997 cpu->ctr = 0xd172172;
998 cpu->reset_sctlr = 0x00000078;
1001 static void pxa255_initfn(Object *obj)
1003 ARMCPU *cpu = ARM_CPU(obj);
1005 cpu->dtb_compatible = "marvell,xscale";
1006 set_feature(&cpu->env, ARM_FEATURE_V5);
1007 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1008 cpu->midr = 0x69052d00;
1009 cpu->ctr = 0xd172172;
1010 cpu->reset_sctlr = 0x00000078;
1013 static void pxa260_initfn(Object *obj)
1015 ARMCPU *cpu = ARM_CPU(obj);
1017 cpu->dtb_compatible = "marvell,xscale";
1018 set_feature(&cpu->env, ARM_FEATURE_V5);
1019 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1020 cpu->midr = 0x69052903;
1021 cpu->ctr = 0xd172172;
1022 cpu->reset_sctlr = 0x00000078;
1025 static void pxa261_initfn(Object *obj)
1027 ARMCPU *cpu = ARM_CPU(obj);
1029 cpu->dtb_compatible = "marvell,xscale";
1030 set_feature(&cpu->env, ARM_FEATURE_V5);
1031 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1032 cpu->midr = 0x69052d05;
1033 cpu->ctr = 0xd172172;
1034 cpu->reset_sctlr = 0x00000078;
1037 static void pxa262_initfn(Object *obj)
1039 ARMCPU *cpu = ARM_CPU(obj);
1041 cpu->dtb_compatible = "marvell,xscale";
1042 set_feature(&cpu->env, ARM_FEATURE_V5);
1043 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1044 cpu->midr = 0x69052d06;
1045 cpu->ctr = 0xd172172;
1046 cpu->reset_sctlr = 0x00000078;
1049 static void pxa270a0_initfn(Object *obj)
1051 ARMCPU *cpu = ARM_CPU(obj);
1053 cpu->dtb_compatible = "marvell,xscale";
1054 set_feature(&cpu->env, ARM_FEATURE_V5);
1055 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1056 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1057 cpu->midr = 0x69054110;
1058 cpu->ctr = 0xd172172;
1059 cpu->reset_sctlr = 0x00000078;
1062 static void pxa270a1_initfn(Object *obj)
1064 ARMCPU *cpu = ARM_CPU(obj);
1066 cpu->dtb_compatible = "marvell,xscale";
1067 set_feature(&cpu->env, ARM_FEATURE_V5);
1068 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1069 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1070 cpu->midr = 0x69054111;
1071 cpu->ctr = 0xd172172;
1072 cpu->reset_sctlr = 0x00000078;
1075 static void pxa270b0_initfn(Object *obj)
1077 ARMCPU *cpu = ARM_CPU(obj);
1079 cpu->dtb_compatible = "marvell,xscale";
1080 set_feature(&cpu->env, ARM_FEATURE_V5);
1081 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1082 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1083 cpu->midr = 0x69054112;
1084 cpu->ctr = 0xd172172;
1085 cpu->reset_sctlr = 0x00000078;
1088 static void pxa270b1_initfn(Object *obj)
1090 ARMCPU *cpu = ARM_CPU(obj);
1092 cpu->dtb_compatible = "marvell,xscale";
1093 set_feature(&cpu->env, ARM_FEATURE_V5);
1094 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1095 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1096 cpu->midr = 0x69054113;
1097 cpu->ctr = 0xd172172;
1098 cpu->reset_sctlr = 0x00000078;
1101 static void pxa270c0_initfn(Object *obj)
1103 ARMCPU *cpu = ARM_CPU(obj);
1105 cpu->dtb_compatible = "marvell,xscale";
1106 set_feature(&cpu->env, ARM_FEATURE_V5);
1107 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1108 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1109 cpu->midr = 0x69054114;
1110 cpu->ctr = 0xd172172;
1111 cpu->reset_sctlr = 0x00000078;
1114 static void pxa270c5_initfn(Object *obj)
1116 ARMCPU *cpu = ARM_CPU(obj);
1118 cpu->dtb_compatible = "marvell,xscale";
1119 set_feature(&cpu->env, ARM_FEATURE_V5);
1120 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1121 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1122 cpu->midr = 0x69054117;
1123 cpu->ctr = 0xd172172;
1124 cpu->reset_sctlr = 0x00000078;
1127 #ifdef CONFIG_USER_ONLY
1128 static void arm_any_initfn(Object *obj)
1130 ARMCPU *cpu = ARM_CPU(obj);
1131 set_feature(&cpu->env, ARM_FEATURE_V8);
1132 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1133 set_feature(&cpu->env, ARM_FEATURE_NEON);
1134 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1135 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1136 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1137 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1138 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1139 set_feature(&cpu->env, ARM_FEATURE_CRC);
1140 cpu->midr = 0xffffffff;
1142 #endif
1144 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1146 typedef struct ARMCPUInfo {
1147 const char *name;
1148 void (*initfn)(Object *obj);
1149 void (*class_init)(ObjectClass *oc, void *data);
1150 } ARMCPUInfo;
1152 static const ARMCPUInfo arm_cpus[] = {
1153 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1154 { .name = "arm926", .initfn = arm926_initfn },
1155 { .name = "arm946", .initfn = arm946_initfn },
1156 { .name = "arm1026", .initfn = arm1026_initfn },
1157 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1158 * older core than plain "arm1136". In particular this does not
1159 * have the v6K features.
1161 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1162 { .name = "arm1136", .initfn = arm1136_initfn },
1163 { .name = "arm1176", .initfn = arm1176_initfn },
1164 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1165 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1166 .class_init = arm_v7m_class_init },
1167 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1168 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1169 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1170 { .name = "ti925t", .initfn = ti925t_initfn },
1171 { .name = "sa1100", .initfn = sa1100_initfn },
1172 { .name = "sa1110", .initfn = sa1110_initfn },
1173 { .name = "pxa250", .initfn = pxa250_initfn },
1174 { .name = "pxa255", .initfn = pxa255_initfn },
1175 { .name = "pxa260", .initfn = pxa260_initfn },
1176 { .name = "pxa261", .initfn = pxa261_initfn },
1177 { .name = "pxa262", .initfn = pxa262_initfn },
1178 /* "pxa270" is an alias for "pxa270-a0" */
1179 { .name = "pxa270", .initfn = pxa270a0_initfn },
1180 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1181 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1182 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1183 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1184 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1185 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1186 #ifdef CONFIG_USER_ONLY
1187 { .name = "any", .initfn = arm_any_initfn },
1188 #endif
1189 #endif
1190 { .name = NULL }
1193 static Property arm_cpu_properties[] = {
1194 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1195 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1196 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1197 DEFINE_PROP_END_OF_LIST()
1200 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1202 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1203 CPUClass *cc = CPU_CLASS(acc);
1204 DeviceClass *dc = DEVICE_CLASS(oc);
1206 acc->parent_realize = dc->realize;
1207 dc->realize = arm_cpu_realizefn;
1208 dc->props = arm_cpu_properties;
1210 acc->parent_reset = cc->reset;
1211 cc->reset = arm_cpu_reset;
1213 cc->class_by_name = arm_cpu_class_by_name;
1214 cc->has_work = arm_cpu_has_work;
1215 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1216 cc->dump_state = arm_cpu_dump_state;
1217 cc->set_pc = arm_cpu_set_pc;
1218 cc->gdb_read_register = arm_cpu_gdb_read_register;
1219 cc->gdb_write_register = arm_cpu_gdb_write_register;
1220 #ifdef CONFIG_USER_ONLY
1221 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1222 #else
1223 cc->do_interrupt = arm_cpu_do_interrupt;
1224 cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1225 cc->vmsd = &vmstate_arm_cpu;
1226 cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1227 #endif
1228 cc->gdb_num_core_regs = 26;
1229 cc->gdb_core_xml_file = "arm-core.xml";
1230 cc->gdb_stop_before_watchpoint = true;
1231 cc->debug_excp_handler = arm_debug_excp_handler;
1234 static void cpu_register(const ARMCPUInfo *info)
1236 TypeInfo type_info = {
1237 .parent = TYPE_ARM_CPU,
1238 .instance_size = sizeof(ARMCPU),
1239 .instance_init = info->initfn,
1240 .class_size = sizeof(ARMCPUClass),
1241 .class_init = info->class_init,
1244 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1245 type_register(&type_info);
1246 g_free((void *)type_info.name);
1249 static const TypeInfo arm_cpu_type_info = {
1250 .name = TYPE_ARM_CPU,
1251 .parent = TYPE_CPU,
1252 .instance_size = sizeof(ARMCPU),
1253 .instance_init = arm_cpu_initfn,
1254 .instance_post_init = arm_cpu_post_init,
1255 .instance_finalize = arm_cpu_finalizefn,
1256 .abstract = true,
1257 .class_size = sizeof(ARMCPUClass),
1258 .class_init = arm_cpu_class_init,
1261 static void arm_cpu_register_types(void)
1263 const ARMCPUInfo *info = arm_cpus;
1265 type_register_static(&arm_cpu_type_info);
1267 while (info->name) {
1268 cpu_register(info);
1269 info++;
1273 type_init(arm_cpu_register_types)