Fix some typos in comments and documentation
[qemu.git] / ioport.c
blob2e971fa3e5cd89ff3c8c175214e15d7632c71b42
1 /*
2 * QEMU System Emulator
4 * Copyright (c) 2003-2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 * splitted out ioport related stuffs from vl.c.
28 #include "ioport.h"
29 #include "trace.h"
31 /***********************************************************/
32 /* IO Port */
34 //#define DEBUG_UNUSED_IOPORT
35 //#define DEBUG_IOPORT
37 #ifdef DEBUG_UNUSED_IOPORT
38 # define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
39 #else
40 # define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
41 #endif
43 #ifdef DEBUG_IOPORT
44 # define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
45 #else
46 # define LOG_IOPORT(...) do { } while (0)
47 #endif
49 /* XXX: use a two level table to limit memory usage */
51 static void *ioport_opaque[MAX_IOPORTS];
52 static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
53 static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
55 static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
56 static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;
58 static uint32_t ioport_read(int index, uint32_t address)
60 static IOPortReadFunc * const default_func[3] = {
61 default_ioport_readb,
62 default_ioport_readw,
63 default_ioport_readl
65 IOPortReadFunc *func = ioport_read_table[index][address];
66 if (!func)
67 func = default_func[index];
68 return func(ioport_opaque[address], address);
71 static void ioport_write(int index, uint32_t address, uint32_t data)
73 static IOPortWriteFunc * const default_func[3] = {
74 default_ioport_writeb,
75 default_ioport_writew,
76 default_ioport_writel
78 IOPortWriteFunc *func = ioport_write_table[index][address];
79 if (!func)
80 func = default_func[index];
81 func(ioport_opaque[address], address, data);
84 static uint32_t default_ioport_readb(void *opaque, uint32_t address)
86 LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
87 return 0xff;
90 static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
92 LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
93 address, data);
96 /* default is to make two byte accesses */
97 static uint32_t default_ioport_readw(void *opaque, uint32_t address)
99 uint32_t data;
100 data = ioport_read(0, address);
101 address = (address + 1) & IOPORTS_MASK;
102 data |= ioport_read(0, address) << 8;
103 return data;
106 static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
108 ioport_write(0, address, data & 0xff);
109 address = (address + 1) & IOPORTS_MASK;
110 ioport_write(0, address, (data >> 8) & 0xff);
113 static uint32_t default_ioport_readl(void *opaque, uint32_t address)
115 LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
116 return 0xffffffff;
119 static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
121 LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
122 address, data);
125 static int ioport_bsize(int size, int *bsize)
127 if (size == 1) {
128 *bsize = 0;
129 } else if (size == 2) {
130 *bsize = 1;
131 } else if (size == 4) {
132 *bsize = 2;
133 } else {
134 return -1;
136 return 0;
139 /* size is the word size in byte */
140 int register_ioport_read(pio_addr_t start, int length, int size,
141 IOPortReadFunc *func, void *opaque)
143 int i, bsize;
145 if (ioport_bsize(size, &bsize)) {
146 hw_error("register_ioport_read: invalid size");
147 return -1;
149 for(i = start; i < start + length; i += size) {
150 ioport_read_table[bsize][i] = func;
151 if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
152 hw_error("register_ioport_read: invalid opaque for address 0x%x",
154 ioport_opaque[i] = opaque;
156 return 0;
159 /* size is the word size in byte */
160 int register_ioport_write(pio_addr_t start, int length, int size,
161 IOPortWriteFunc *func, void *opaque)
163 int i, bsize;
165 if (ioport_bsize(size, &bsize)) {
166 hw_error("register_ioport_write: invalid size");
167 return -1;
169 for(i = start; i < start + length; i += size) {
170 ioport_write_table[bsize][i] = func;
171 if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
172 hw_error("register_ioport_write: invalid opaque for address 0x%x",
174 ioport_opaque[i] = opaque;
176 return 0;
179 static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
181 IORange *ioport = opaque;
182 uint64_t data;
184 ioport->ops->read(ioport, addr - ioport->base, 1, &data);
185 return data;
188 static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
190 IORange *ioport = opaque;
191 uint64_t data;
193 ioport->ops->read(ioport, addr - ioport->base, 2, &data);
194 return data;
197 static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
199 IORange *ioport = opaque;
200 uint64_t data;
202 ioport->ops->read(ioport, addr - ioport->base, 4, &data);
203 return data;
206 static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
208 IORange *ioport = opaque;
210 ioport->ops->write(ioport, addr - ioport->base, 1, data);
213 static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
215 IORange *ioport = opaque;
217 ioport->ops->write(ioport, addr - ioport->base, 2, data);
220 static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
222 IORange *ioport = opaque;
224 ioport->ops->write(ioport, addr - ioport->base, 4, data);
227 void ioport_register(IORange *ioport)
229 register_ioport_read(ioport->base, ioport->len, 1,
230 ioport_readb_thunk, ioport);
231 register_ioport_read(ioport->base, ioport->len, 2,
232 ioport_readw_thunk, ioport);
233 register_ioport_read(ioport->base, ioport->len, 4,
234 ioport_readl_thunk, ioport);
235 register_ioport_write(ioport->base, ioport->len, 1,
236 ioport_writeb_thunk, ioport);
237 register_ioport_write(ioport->base, ioport->len, 2,
238 ioport_writew_thunk, ioport);
239 register_ioport_write(ioport->base, ioport->len, 4,
240 ioport_writel_thunk, ioport);
243 void isa_unassign_ioport(pio_addr_t start, int length)
245 int i;
247 for(i = start; i < start + length; i++) {
248 ioport_read_table[0][i] = default_ioport_readb;
249 ioport_read_table[1][i] = default_ioport_readw;
250 ioport_read_table[2][i] = default_ioport_readl;
252 ioport_write_table[0][i] = default_ioport_writeb;
253 ioport_write_table[1][i] = default_ioport_writew;
254 ioport_write_table[2][i] = default_ioport_writel;
256 ioport_opaque[i] = NULL;
260 /***********************************************************/
262 void cpu_outb(pio_addr_t addr, uint8_t val)
264 LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
265 trace_cpu_out(addr, val);
266 ioport_write(0, addr, val);
269 void cpu_outw(pio_addr_t addr, uint16_t val)
271 LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
272 trace_cpu_out(addr, val);
273 ioport_write(1, addr, val);
276 void cpu_outl(pio_addr_t addr, uint32_t val)
278 LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
279 trace_cpu_out(addr, val);
280 ioport_write(2, addr, val);
283 uint8_t cpu_inb(pio_addr_t addr)
285 uint8_t val;
286 val = ioport_read(0, addr);
287 trace_cpu_in(addr, val);
288 LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
289 return val;
292 uint16_t cpu_inw(pio_addr_t addr)
294 uint16_t val;
295 val = ioport_read(1, addr);
296 trace_cpu_in(addr, val);
297 LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
298 return val;
301 uint32_t cpu_inl(pio_addr_t addr)
303 uint32_t val;
304 val = ioport_read(2, addr);
305 trace_cpu_in(addr, val);
306 LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
307 return val;