char/cadence_uart: Fix can_receive logic
[qemu.git] / hw / intc / arm_gic_kvm.c
blobf71397542a64b69646eafe84ad4de2ac445f8ee7
1 /*
2 * ARM Generic Interrupt Controller using KVM in-kernel support
4 * Copyright (c) 2012 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "hw/sysbus.h"
22 #include "sysemu/kvm.h"
23 #include "kvm_arm.h"
24 #include "gic_internal.h"
26 #define TYPE_KVM_ARM_GIC "kvm-arm-gic"
27 #define KVM_ARM_GIC(obj) \
28 OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
29 #define KVM_ARM_GIC_CLASS(klass) \
30 OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
31 #define KVM_ARM_GIC_GET_CLASS(obj) \
32 OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
34 typedef struct KVMARMGICClass {
35 ARMGICCommonClass parent_class;
36 DeviceRealize parent_realize;
37 void (*parent_reset)(DeviceState *dev);
38 } KVMARMGICClass;
40 static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
42 /* Meaning of the 'irq' parameter:
43 * [0..N-1] : external interrupts
44 * [N..N+31] : PPI (internal) interrupts for CPU 0
45 * [N+32..N+63] : PPI (internal interrupts for CPU 1
46 * ...
47 * Convert this to the kernel's desired encoding, which
48 * has separate fields in the irq number for type,
49 * CPU number and interrupt number.
51 GICState *s = (GICState *)opaque;
52 int kvm_irq, irqtype, cpu;
54 if (irq < (s->num_irq - GIC_INTERNAL)) {
55 /* External interrupt. The kernel numbers these like the GIC
56 * hardware, with external interrupt IDs starting after the
57 * internal ones.
59 irqtype = KVM_ARM_IRQ_TYPE_SPI;
60 cpu = 0;
61 irq += GIC_INTERNAL;
62 } else {
63 /* Internal interrupt: decode into (cpu, interrupt id) */
64 irqtype = KVM_ARM_IRQ_TYPE_PPI;
65 irq -= (s->num_irq - GIC_INTERNAL);
66 cpu = irq / GIC_INTERNAL;
67 irq %= GIC_INTERNAL;
69 kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
70 | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
72 kvm_set_irq(kvm_state, kvm_irq, !!level);
75 static void kvm_arm_gic_put(GICState *s)
77 /* TODO: there isn't currently a kernel interface to set the GIC state */
80 static void kvm_arm_gic_get(GICState *s)
82 /* TODO: there isn't currently a kernel interface to get the GIC state */
85 static void kvm_arm_gic_reset(DeviceState *dev)
87 GICState *s = ARM_GIC_COMMON(dev);
88 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
90 kgc->parent_reset(dev);
91 kvm_arm_gic_put(s);
94 static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
96 int i;
97 GICState *s = KVM_ARM_GIC(dev);
98 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
99 KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
101 kgc->parent_realize(dev, errp);
102 if (error_is_set(errp)) {
103 return;
106 i = s->num_irq - GIC_INTERNAL;
107 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
108 * GPIO array layout is thus:
109 * [0..N-1] SPIs
110 * [N..N+31] PPIs for CPU 0
111 * [N+32..N+63] PPIs for CPU 1
112 * ...
114 i += (GIC_INTERNAL * s->num_cpu);
115 qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i);
116 /* We never use our outbound IRQ lines but provide them so that
117 * we maintain the same interface as the non-KVM GIC.
119 for (i = 0; i < s->num_cpu; i++) {
120 sysbus_init_irq(sbd, &s->parent_irq[i]);
122 /* Distributor */
123 memory_region_init_reservation(&s->iomem, OBJECT(s),
124 "kvm-gic_dist", 0x1000);
125 sysbus_init_mmio(sbd, &s->iomem);
126 kvm_arm_register_device(&s->iomem,
127 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
128 | KVM_VGIC_V2_ADDR_TYPE_DIST);
129 /* CPU interface for current core. Unlike arm_gic, we don't
130 * provide the "interface for core #N" memory regions, because
131 * cores with a VGIC don't have those.
133 memory_region_init_reservation(&s->cpuiomem[0], OBJECT(s),
134 "kvm-gic_cpu", 0x1000);
135 sysbus_init_mmio(sbd, &s->cpuiomem[0]);
136 kvm_arm_register_device(&s->cpuiomem[0],
137 (KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
138 | KVM_VGIC_V2_ADDR_TYPE_CPU);
141 static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
143 DeviceClass *dc = DEVICE_CLASS(klass);
144 ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
145 KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
147 agcc->pre_save = kvm_arm_gic_get;
148 agcc->post_load = kvm_arm_gic_put;
149 kgc->parent_realize = dc->realize;
150 kgc->parent_reset = dc->reset;
151 dc->realize = kvm_arm_gic_realize;
152 dc->reset = kvm_arm_gic_reset;
153 dc->no_user = 1;
156 static const TypeInfo kvm_arm_gic_info = {
157 .name = TYPE_KVM_ARM_GIC,
158 .parent = TYPE_ARM_GIC_COMMON,
159 .instance_size = sizeof(GICState),
160 .class_init = kvm_arm_gic_class_init,
161 .class_size = sizeof(KVMARMGICClass),
164 static void kvm_arm_gic_register_types(void)
166 type_register_static(&kvm_arm_gic_info);
169 type_init(kvm_arm_gic_register_types)