hw/lance.c

   1 /*
   2  * QEMU AMD PC-Net II (Am79C970A) emulation
   3  *
   4  * Copyright (c) 2004 Antony T Curtis
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* This software was written to be compatible with the specification:
  26  * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
  27  * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
  28  */
  29
  30 /*
  31  * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
  32  * produced as NCR89C100. See
  33  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34  * and
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
  36  */
  37
  38 #include "sysbus.h"
  39 #include "net.h"
  40 #include "qemu-timer.h"
  41 #include "qemu_socket.h"
  42 #include "sun4m.h"
  43 #include "pcnet.h"
  44 #include "trace.h"
  45
  46 typedef struct {
  47     SysBusDevice busdev;
  48     PCNetState state;
  49 } SysBusPCNetState;
  50
  51 static void parent_lance_reset(void *opaque, int irq, int level)
  52 {
  53     SysBusPCNetState *d = opaque;
  54     if (level)
  55         pcnet_h_reset(&d->state);
  56 }
  57
  58 static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
  59                              uint32_t val)
  60 {
  61     SysBusPCNetState *d = opaque;
  62
  63     trace_lance_mem_writew(addr, val & 0xffff);
  64     pcnet_ioport_writew(&d->state, addr, val & 0xffff);
  65 }
  66
  67 static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
  68 {
  69     SysBusPCNetState *d = opaque;
  70     uint32_t val;
  71
  72     val = pcnet_ioport_readw(&d->state, addr);
  73     trace_lance_mem_readw(addr, val & 0xffff);
  74     return val & 0xffff;
  75 }
  76
  77 static CPUReadMemoryFunc * const lance_mem_read[3] = {
  78     NULL,
  79     lance_mem_readw,
  80     NULL,
  81 };
  82
  83 static CPUWriteMemoryFunc * const lance_mem_write[3] = {
  84     NULL,
  85     lance_mem_writew,
  86     NULL,
  87 };
  88
  89 static void lance_cleanup(VLANClientState *nc)
  90 {
  91     PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
  92
  93     pcnet_common_cleanup(d);
  94 }
  95
  96 static NetClientInfo net_lance_info = {
  97     .type = NET_CLIENT_TYPE_NIC,
  98     .size = sizeof(NICState),
  99     .can_receive = pcnet_can_receive,
 100     .receive = pcnet_receive,
 101     .cleanup = lance_cleanup,
 102 };
 103
 104 static const VMStateDescription vmstate_lance = {
 105     .name = "pcnet",
 106     .version_id = 3,
 107     .minimum_version_id = 2,
 108     .minimum_version_id_old = 2,
 109     .fields      = (VMStateField []) {
 110         VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
 111         VMSTATE_END_OF_LIST()
 112     }
 113 };
 114
 115 static int lance_init(SysBusDevice *dev)
 116 {
 117     SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
 118     PCNetState *s = &d->state;
 119
 120     s->mmio_index =
 121         cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
 122
 123     qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
 124
 125     sysbus_init_mmio(dev, 4, s->mmio_index);
 126
 127     sysbus_init_irq(dev, &s->irq);
 128
 129     s->phys_mem_read = ledma_memory_read;
 130     s->phys_mem_write = ledma_memory_write;
 131     return pcnet_common_init(&dev->qdev, s, &net_lance_info);
 132 }
 133
 134 static void lance_reset(DeviceState *dev)
 135 {
 136     SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
 137
 138     pcnet_h_reset(&d->state);
 139 }
 140
 141 static SysBusDeviceInfo lance_info = {
 142     .init       = lance_init,
 143     .qdev.name  = "lance",
 144     .qdev.size  = sizeof(SysBusPCNetState),
 145     .qdev.reset = lance_reset,
 146     .qdev.vmsd  = &vmstate_lance,
 147     .qdev.props = (Property[]) {
 148         DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
 149         DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
 150         DEFINE_PROP_END_OF_LIST(),
 151     }
 152 };
 153
 154 static void lance_register_devices(void)
 155 {
 156     sysbus_register_withprop(&lance_info);
 157 }
 158 device_init(lance_register_devices)