hw/scsi/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "hw/irq.h"
  30 #include "hw/scsi/esp.h"
  31 #include "trace.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34
  35 /*
  36  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  37  * also produced as NCR89C100. See
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  39  * and
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  41  */
  42
  43 static void esp_raise_irq(ESPState *s)
  44 {
  45     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
  46         s->rregs[ESP_RSTAT] |= STAT_INT;
  47         qemu_irq_raise(s->irq);
  48         trace_esp_raise_irq();
  49     }
  50 }
  51
  52 static void esp_lower_irq(ESPState *s)
  53 {
  54     if (s->rregs[ESP_RSTAT] & STAT_INT) {
  55         s->rregs[ESP_RSTAT] &= ~STAT_INT;
  56         qemu_irq_lower(s->irq);
  57         trace_esp_lower_irq();
  58     }
  59 }
  60
  61 void esp_dma_enable(ESPState *s, int irq, int level)
  62 {
  63     if (level) {
  64         s->dma_enabled = 1;
  65         trace_esp_dma_enable();
  66         if (s->dma_cb) {
  67             s->dma_cb(s);
  68             s->dma_cb = NULL;
  69         }
  70     } else {
  71         trace_esp_dma_disable();
  72         s->dma_enabled = 0;
  73     }
  74 }
  75
  76 void esp_request_cancelled(SCSIRequest *req)
  77 {
  78     ESPState *s = req->hba_private;
  79
  80     if (req == s->current_req) {
  81         scsi_req_unref(s->current_req);
  82         s->current_req = NULL;
  83         s->current_dev = NULL;
  84     }
  85 }
  86
  87 static int get_cmd_cb(ESPState *s)
  88 {
  89     int target;
  90
  91     target = s->wregs[ESP_WBUSID] & BUSID_DID;
  92
  93     s->ti_size = 0;
  94     s->ti_rptr = 0;
  95     s->ti_wptr = 0;
  96
  97     if (s->current_req) {
  98         /* Started a new command before the old one finished.  Cancel it.  */
  99         scsi_req_cancel(s->current_req);
 100         s->async_len = 0;
 101     }
 102
 103     s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
 104     if (!s->current_dev) {
 105         /* No such drive */
 106         s->rregs[ESP_RSTAT] = 0;
 107         s->rregs[ESP_RINTR] = INTR_DC;
 108         s->rregs[ESP_RSEQ] = SEQ_0;
 109         esp_raise_irq(s);
 110         return -1;
 111     }
 112     return 0;
 113 }
 114
 115 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
 116 {
 117     uint32_t dmalen;
 118     int target;
 119
 120     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 121     if (s->dma) {
 122         dmalen = s->rregs[ESP_TCLO];
 123         dmalen |= s->rregs[ESP_TCMID] << 8;
 124         dmalen |= s->rregs[ESP_TCHI] << 16;
 125         if (dmalen > buflen) {
 126             return 0;
 127         }
 128         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 129     } else {
 130         dmalen = s->ti_size;
 131         if (dmalen > TI_BUFSZ) {
 132             return 0;
 133         }
 134         memcpy(buf, s->ti_buf, dmalen);
 135         buf[0] = buf[2] >> 5;
 136     }
 137     trace_esp_get_cmd(dmalen, target);
 138
 139     if (get_cmd_cb(s) < 0) {
 140         return 0;
 141     }
 142     return dmalen;
 143 }
 144
 145 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 146 {
 147     int32_t datalen;
 148     int lun;
 149     SCSIDevice *current_lun;
 150
 151     trace_esp_do_busid_cmd(busid);
 152     lun = busid & 7;
 153     current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
 154     s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
 155     datalen = scsi_req_enqueue(s->current_req);
 156     s->ti_size = datalen;
 157     if (datalen != 0) {
 158         s->rregs[ESP_RSTAT] = STAT_TC;
 159         s->dma_left = 0;
 160         s->dma_counter = 0;
 161         if (datalen > 0) {
 162             s->rregs[ESP_RSTAT] |= STAT_DI;
 163         } else {
 164             s->rregs[ESP_RSTAT] |= STAT_DO;
 165         }
 166         scsi_req_continue(s->current_req);
 167     }
 168     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 169     s->rregs[ESP_RSEQ] = SEQ_CD;
 170     esp_raise_irq(s);
 171 }
 172
 173 static void do_cmd(ESPState *s, uint8_t *buf)
 174 {
 175     uint8_t busid = buf[0];
 176
 177     do_busid_cmd(s, &buf[1], busid);
 178 }
 179
 180 static void handle_satn(ESPState *s)
 181 {
 182     uint8_t buf[32];
 183     int len;
 184
 185     if (s->dma && !s->dma_enabled) {
 186         s->dma_cb = handle_satn;
 187         return;
 188     }
 189     len = get_cmd(s, buf, sizeof(buf));
 190     if (len)
 191         do_cmd(s, buf);
 192 }
 193
 194 static void handle_s_without_atn(ESPState *s)
 195 {
 196     uint8_t buf[32];
 197     int len;
 198
 199     if (s->dma && !s->dma_enabled) {
 200         s->dma_cb = handle_s_without_atn;
 201         return;
 202     }
 203     len = get_cmd(s, buf, sizeof(buf));
 204     if (len) {
 205         do_busid_cmd(s, buf, 0);
 206     }
 207 }
 208
 209 static void handle_satn_stop(ESPState *s)
 210 {
 211     if (s->dma && !s->dma_enabled) {
 212         s->dma_cb = handle_satn_stop;
 213         return;
 214     }
 215     s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
 216     if (s->cmdlen) {
 217         trace_esp_handle_satn_stop(s->cmdlen);
 218         s->do_cmd = 1;
 219         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 220         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 221         s->rregs[ESP_RSEQ] = SEQ_CD;
 222         esp_raise_irq(s);
 223     }
 224 }
 225
 226 static void write_response(ESPState *s)
 227 {
 228     trace_esp_write_response(s->status);
 229     s->ti_buf[0] = s->status;
 230     s->ti_buf[1] = 0;
 231     if (s->dma) {
 232         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 233         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 234         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 235         s->rregs[ESP_RSEQ] = SEQ_CD;
 236     } else {
 237         s->ti_size = 2;
 238         s->ti_rptr = 0;
 239         s->ti_wptr = 2;
 240         s->rregs[ESP_RFLAGS] = 2;
 241     }
 242     esp_raise_irq(s);
 243 }
 244
 245 static void esp_dma_done(ESPState *s)
 246 {
 247     s->rregs[ESP_RSTAT] |= STAT_TC;
 248     s->rregs[ESP_RINTR] = INTR_BS;
 249     s->rregs[ESP_RSEQ] = 0;
 250     s->rregs[ESP_RFLAGS] = 0;
 251     s->rregs[ESP_TCLO] = 0;
 252     s->rregs[ESP_TCMID] = 0;
 253     s->rregs[ESP_TCHI] = 0;
 254     esp_raise_irq(s);
 255 }
 256
 257 static void esp_do_dma(ESPState *s)
 258 {
 259     uint32_t len;
 260     int to_device;
 261
 262     len = s->dma_left;
 263     if (s->do_cmd) {
 264         /*
 265          * handle_ti_cmd() case: esp_do_dma() is called only from
 266          * handle_ti_cmd() with do_cmd != NULL (see the assert())
 267          */
 268         trace_esp_do_dma(s->cmdlen, len);
 269         assert (s->cmdlen <= sizeof(s->cmdbuf) &&
 270                 len <= sizeof(s->cmdbuf) - s->cmdlen);
 271         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 272         trace_esp_handle_ti_cmd(s->cmdlen);
 273         s->ti_size = 0;
 274         s->cmdlen = 0;
 275         s->do_cmd = 0;
 276         do_cmd(s, s->cmdbuf);
 277         return;
 278     }
 279     if (s->async_len == 0) {
 280         /* Defer until data is available.  */
 281         return;
 282     }
 283     if (len > s->async_len) {
 284         len = s->async_len;
 285     }
 286     to_device = (s->ti_size < 0);
 287     if (to_device) {
 288         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 289     } else {
 290         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 291     }
 292     s->dma_left -= len;
 293     s->async_buf += len;
 294     s->async_len -= len;
 295     if (to_device)
 296         s->ti_size += len;
 297     else
 298         s->ti_size -= len;
 299     if (s->async_len == 0) {
 300         scsi_req_continue(s->current_req);
 301         /* If there is still data to be read from the device then
 302            complete the DMA operation immediately.  Otherwise defer
 303            until the scsi layer has completed.  */
 304         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 305             return;
 306         }
 307     }
 308
 309     /* Partially filled a scsi buffer. Complete immediately.  */
 310     esp_dma_done(s);
 311 }
 312
 313 static void esp_report_command_complete(ESPState *s, uint32_t status)
 314 {
 315     trace_esp_command_complete();
 316     if (s->ti_size != 0) {
 317         trace_esp_command_complete_unexpected();
 318     }
 319     s->ti_size = 0;
 320     s->dma_left = 0;
 321     s->async_len = 0;
 322     if (status) {
 323         trace_esp_command_complete_fail();
 324     }
 325     s->status = status;
 326     s->rregs[ESP_RSTAT] = STAT_ST;
 327     esp_dma_done(s);
 328     if (s->current_req) {
 329         scsi_req_unref(s->current_req);
 330         s->current_req = NULL;
 331         s->current_dev = NULL;
 332     }
 333 }
 334
 335 void esp_command_complete(SCSIRequest *req, uint32_t status,
 336                           size_t resid)
 337 {
 338     ESPState *s = req->hba_private;
 339
 340     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 341         /* Defer handling command complete until the previous
 342          * interrupt has been handled.
 343          */
 344         trace_esp_command_complete_deferred();
 345         s->deferred_status = status;
 346         s->deferred_complete = true;
 347         return;
 348     }
 349     esp_report_command_complete(s, status);
 350 }
 351
 352 void esp_transfer_data(SCSIRequest *req, uint32_t len)
 353 {
 354     ESPState *s = req->hba_private;
 355
 356     assert(!s->do_cmd);
 357     trace_esp_transfer_data(s->dma_left, s->ti_size);
 358     s->async_len = len;
 359     s->async_buf = scsi_req_get_buf(req);
 360     if (s->dma_left) {
 361         esp_do_dma(s);
 362     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 363         /* If this was the last part of a DMA transfer then the
 364            completion interrupt is deferred to here.  */
 365         esp_dma_done(s);
 366     }
 367 }
 368
 369 static void handle_ti(ESPState *s)
 370 {
 371     uint32_t dmalen, minlen;
 372
 373     if (s->dma && !s->dma_enabled) {
 374         s->dma_cb = handle_ti;
 375         return;
 376     }
 377
 378     dmalen = s->rregs[ESP_TCLO];
 379     dmalen |= s->rregs[ESP_TCMID] << 8;
 380     dmalen |= s->rregs[ESP_TCHI] << 16;
 381     if (dmalen==0) {
 382       dmalen=0x10000;
 383     }
 384     s->dma_counter = dmalen;
 385
 386     if (s->do_cmd)
 387         minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ;
 388     else if (s->ti_size < 0)
 389         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 390     else
 391         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 392     trace_esp_handle_ti(minlen);
 393     if (s->dma) {
 394         s->dma_left = minlen;
 395         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 396         esp_do_dma(s);
 397     } else if (s->do_cmd) {
 398         trace_esp_handle_ti_cmd(s->cmdlen);
 399         s->ti_size = 0;
 400         s->cmdlen = 0;
 401         s->do_cmd = 0;
 402         do_cmd(s, s->cmdbuf);
 403     }
 404 }
 405
 406 void esp_hard_reset(ESPState *s)
 407 {
 408     memset(s->rregs, 0, ESP_REGS);
 409     memset(s->wregs, 0, ESP_REGS);
 410     s->tchi_written = 0;
 411     s->ti_size = 0;
 412     s->ti_rptr = 0;
 413     s->ti_wptr = 0;
 414     s->dma = 0;
 415     s->do_cmd = 0;
 416     s->dma_cb = NULL;
 417
 418     s->rregs[ESP_CFG1] = 7;
 419 }
 420
 421 static void esp_soft_reset(ESPState *s)
 422 {
 423     qemu_irq_lower(s->irq);
 424     esp_hard_reset(s);
 425 }
 426
 427 static void parent_esp_reset(ESPState *s, int irq, int level)
 428 {
 429     if (level) {
 430         esp_soft_reset(s);
 431     }
 432 }
 433
 434 uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
 435 {
 436     uint32_t old_val;
 437
 438     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 439     switch (saddr) {
 440     case ESP_FIFO:
 441         if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 442             /* Data out.  */
 443             qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n");
 444             s->rregs[ESP_FIFO] = 0;
 445         } else if (s->ti_rptr < s->ti_wptr) {
 446             s->ti_size--;
 447             s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 448         }
 449         if (s->ti_rptr == s->ti_wptr) {
 450             s->ti_rptr = 0;
 451             s->ti_wptr = 0;
 452         }
 453         break;
 454     case ESP_RINTR:
 455         /* Clear sequence step, interrupt register and all status bits
 456            except TC */
 457         old_val = s->rregs[ESP_RINTR];
 458         s->rregs[ESP_RINTR] = 0;
 459         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 460         s->rregs[ESP_RSEQ] = SEQ_CD;
 461         esp_lower_irq(s);
 462         if (s->deferred_complete) {
 463             esp_report_command_complete(s, s->deferred_status);
 464             s->deferred_complete = false;
 465         }
 466         return old_val;
 467     case ESP_TCHI:
 468         /* Return the unique id if the value has never been written */
 469         if (!s->tchi_written) {
 470             return s->chip_id;
 471         }
 472     default:
 473         break;
 474     }
 475     return s->rregs[saddr];
 476 }
 477
 478 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
 479 {
 480     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 481     switch (saddr) {
 482     case ESP_TCHI:
 483         s->tchi_written = true;
 484         /* fall through */
 485     case ESP_TCLO:
 486     case ESP_TCMID:
 487         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 488         break;
 489     case ESP_FIFO:
 490         if (s->do_cmd) {
 491             if (s->cmdlen < ESP_CMDBUF_SZ) {
 492                 s->cmdbuf[s->cmdlen++] = val & 0xff;
 493             } else {
 494                 trace_esp_error_fifo_overrun();
 495             }
 496         } else if (s->ti_wptr == TI_BUFSZ - 1) {
 497             trace_esp_error_fifo_overrun();
 498         } else {
 499             s->ti_size++;
 500             s->ti_buf[s->ti_wptr++] = val & 0xff;
 501         }
 502         break;
 503     case ESP_CMD:
 504         s->rregs[saddr] = val;
 505         if (val & CMD_DMA) {
 506             s->dma = 1;
 507             /* Reload DMA counter.  */
 508             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 509             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 510             s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
 511         } else {
 512             s->dma = 0;
 513         }
 514         switch(val & CMD_CMD) {
 515         case CMD_NOP:
 516             trace_esp_mem_writeb_cmd_nop(val);
 517             break;
 518         case CMD_FLUSH:
 519             trace_esp_mem_writeb_cmd_flush(val);
 520             //s->ti_size = 0;
 521             s->rregs[ESP_RINTR] = INTR_FC;
 522             s->rregs[ESP_RSEQ] = 0;
 523             s->rregs[ESP_RFLAGS] = 0;
 524             break;
 525         case CMD_RESET:
 526             trace_esp_mem_writeb_cmd_reset(val);
 527             esp_soft_reset(s);
 528             break;
 529         case CMD_BUSRESET:
 530             trace_esp_mem_writeb_cmd_bus_reset(val);
 531             s->rregs[ESP_RINTR] = INTR_RST;
 532             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 533                 esp_raise_irq(s);
 534             }
 535             break;
 536         case CMD_TI:
 537             handle_ti(s);
 538             break;
 539         case CMD_ICCS:
 540             trace_esp_mem_writeb_cmd_iccs(val);
 541             write_response(s);
 542             s->rregs[ESP_RINTR] = INTR_FC;
 543             s->rregs[ESP_RSTAT] |= STAT_MI;
 544             break;
 545         case CMD_MSGACC:
 546             trace_esp_mem_writeb_cmd_msgacc(val);
 547             s->rregs[ESP_RINTR] = INTR_DC;
 548             s->rregs[ESP_RSEQ] = 0;
 549             s->rregs[ESP_RFLAGS] = 0;
 550             esp_raise_irq(s);
 551             break;
 552         case CMD_PAD:
 553             trace_esp_mem_writeb_cmd_pad(val);
 554             s->rregs[ESP_RSTAT] = STAT_TC;
 555             s->rregs[ESP_RINTR] = INTR_FC;
 556             s->rregs[ESP_RSEQ] = 0;
 557             break;
 558         case CMD_SATN:
 559             trace_esp_mem_writeb_cmd_satn(val);
 560             break;
 561         case CMD_RSTATN:
 562             trace_esp_mem_writeb_cmd_rstatn(val);
 563             break;
 564         case CMD_SEL:
 565             trace_esp_mem_writeb_cmd_sel(val);
 566             handle_s_without_atn(s);
 567             break;
 568         case CMD_SELATN:
 569             trace_esp_mem_writeb_cmd_selatn(val);
 570             handle_satn(s);
 571             break;
 572         case CMD_SELATNS:
 573             trace_esp_mem_writeb_cmd_selatns(val);
 574             handle_satn_stop(s);
 575             break;
 576         case CMD_ENSEL:
 577             trace_esp_mem_writeb_cmd_ensel(val);
 578             s->rregs[ESP_RINTR] = 0;
 579             break;
 580         case CMD_DISSEL:
 581             trace_esp_mem_writeb_cmd_dissel(val);
 582             s->rregs[ESP_RINTR] = 0;
 583             esp_raise_irq(s);
 584             break;
 585         default:
 586             trace_esp_error_unhandled_command(val);
 587             break;
 588         }
 589         break;
 590     case ESP_WBUSID ... ESP_WSYNO:
 591         break;
 592     case ESP_CFG1:
 593     case ESP_CFG2: case ESP_CFG3:
 594     case ESP_RES3: case ESP_RES4:
 595         s->rregs[saddr] = val;
 596         break;
 597     case ESP_WCCF ... ESP_WTEST:
 598         break;
 599     default:
 600         trace_esp_error_invalid_write(val, saddr);
 601         return;
 602     }
 603     s->wregs[saddr] = val;
 604 }
 605
 606 static bool esp_mem_accepts(void *opaque, hwaddr addr,
 607                             unsigned size, bool is_write,
 608                             MemTxAttrs attrs)
 609 {
 610     return (size == 1) || (is_write && size == 4);
 611 }
 612
 613 const VMStateDescription vmstate_esp = {
 614     .name ="esp",
 615     .version_id = 4,
 616     .minimum_version_id = 3,
 617     .fields = (VMStateField[]) {
 618         VMSTATE_BUFFER(rregs, ESPState),
 619         VMSTATE_BUFFER(wregs, ESPState),
 620         VMSTATE_INT32(ti_size, ESPState),
 621         VMSTATE_UINT32(ti_rptr, ESPState),
 622         VMSTATE_UINT32(ti_wptr, ESPState),
 623         VMSTATE_BUFFER(ti_buf, ESPState),
 624         VMSTATE_UINT32(status, ESPState),
 625         VMSTATE_UINT32(deferred_status, ESPState),
 626         VMSTATE_BOOL(deferred_complete, ESPState),
 627         VMSTATE_UINT32(dma, ESPState),
 628         VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16),
 629         VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4),
 630         VMSTATE_UINT32(cmdlen, ESPState),
 631         VMSTATE_UINT32(do_cmd, ESPState),
 632         VMSTATE_UINT32(dma_left, ESPState),
 633         VMSTATE_END_OF_LIST()
 634     }
 635 };
 636
 637 static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
 638                                  uint64_t val, unsigned int size)
 639 {
 640     SysBusESPState *sysbus = opaque;
 641     uint32_t saddr;
 642
 643     saddr = addr >> sysbus->it_shift;
 644     esp_reg_write(&sysbus->esp, saddr, val);
 645 }
 646
 647 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
 648                                     unsigned int size)
 649 {
 650     SysBusESPState *sysbus = opaque;
 651     uint32_t saddr;
 652
 653     saddr = addr >> sysbus->it_shift;
 654     return esp_reg_read(&sysbus->esp, saddr);
 655 }
 656
 657 static const MemoryRegionOps sysbus_esp_mem_ops = {
 658     .read = sysbus_esp_mem_read,
 659     .write = sysbus_esp_mem_write,
 660     .endianness = DEVICE_NATIVE_ENDIAN,
 661     .valid.accepts = esp_mem_accepts,
 662 };
 663
 664 static const struct SCSIBusInfo esp_scsi_info = {
 665     .tcq = false,
 666     .max_target = ESP_MAX_DEVS,
 667     .max_lun = 7,
 668
 669     .transfer_data = esp_transfer_data,
 670     .complete = esp_command_complete,
 671     .cancel = esp_request_cancelled
 672 };
 673
 674 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
 675 {
 676     SysBusESPState *sysbus = ESP_STATE(opaque);
 677     ESPState *s = &sysbus->esp;
 678
 679     switch (irq) {
 680     case 0:
 681         parent_esp_reset(s, irq, level);
 682         break;
 683     case 1:
 684         esp_dma_enable(opaque, irq, level);
 685         break;
 686     }
 687 }
 688
 689 static void sysbus_esp_realize(DeviceState *dev, Error **errp)
 690 {
 691     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 692     SysBusESPState *sysbus = ESP_STATE(dev);
 693     ESPState *s = &sysbus->esp;
 694
 695     sysbus_init_irq(sbd, &s->irq);
 696     assert(sysbus->it_shift != -1);
 697
 698     s->chip_id = TCHI_FAS100A;
 699     memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
 700                           sysbus, "esp", ESP_REGS << sysbus->it_shift);
 701     sysbus_init_mmio(sbd, &sysbus->iomem);
 702
 703     qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
 704
 705     scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
 706 }
 707
 708 static void sysbus_esp_hard_reset(DeviceState *dev)
 709 {
 710     SysBusESPState *sysbus = ESP_STATE(dev);
 711     esp_hard_reset(&sysbus->esp);
 712 }
 713
 714 static const VMStateDescription vmstate_sysbus_esp_scsi = {
 715     .name = "sysbusespscsi",
 716     .version_id = 1,
 717     .minimum_version_id = 1,
 718     .fields = (VMStateField[]) {
 719         VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
 720         VMSTATE_END_OF_LIST()
 721     }
 722 };
 723
 724 static void sysbus_esp_class_init(ObjectClass *klass, void *data)
 725 {
 726     DeviceClass *dc = DEVICE_CLASS(klass);
 727
 728     dc->realize = sysbus_esp_realize;
 729     dc->reset = sysbus_esp_hard_reset;
 730     dc->vmsd = &vmstate_sysbus_esp_scsi;
 731     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 732 }
 733
 734 static const TypeInfo sysbus_esp_info = {
 735     .name          = TYPE_ESP,
 736     .parent        = TYPE_SYS_BUS_DEVICE,
 737     .instance_size = sizeof(SysBusESPState),
 738     .class_init    = sysbus_esp_class_init,
 739 };
 740
 741 static void esp_register_types(void)
 742 {
 743     type_register_static(&sysbus_esp_info);
 744 }
 745
 746 type_init(esp_register_types)