hw/intc/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "qemu/thread.h"
  20 #include "hw/i386/apic_internal.h"
  21 #include "hw/i386/apic.h"
  22 #include "hw/i386/ioapic.h"
  23 #include "hw/pci/msi.h"
  24 #include "qemu/host-utils.h"
  25 #include "trace.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/i386/apic-msidef.h"
  28
  29 #define MAX_APIC_WORDS 8
  30
  31 #define SYNC_FROM_VAPIC                 0x1
  32 #define SYNC_TO_VAPIC                   0x2
  33 #define SYNC_ISR_IRR_TO_VAPIC           0x4
  34
  35 static APICCommonState *local_apics[MAX_APICS + 1];
  36
  37 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
  38 static void apic_update_irq(APICCommonState *s);
  39 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  40                                       uint8_t dest, uint8_t dest_mode);
  41
  42 /* Find first bit starting from msb */
  43 static int apic_fls_bit(uint32_t value)
  44 {
  45     return 31 - clz32(value);
  46 }
  47
  48 /* Find first bit starting from lsb */
  49 static int apic_ffs_bit(uint32_t value)
  50 {
  51     return ctz32(value);
  52 }
  53
  54 static inline void apic_set_bit(uint32_t *tab, int index)
  55 {
  56     int i, mask;
  57     i = index >> 5;
  58     mask = 1 << (index & 0x1f);
  59     tab[i] |= mask;
  60 }
  61
  62 static inline void apic_reset_bit(uint32_t *tab, int index)
  63 {
  64     int i, mask;
  65     i = index >> 5;
  66     mask = 1 << (index & 0x1f);
  67     tab[i] &= ~mask;
  68 }
  69
  70 static inline int apic_get_bit(uint32_t *tab, int index)
  71 {
  72     int i, mask;
  73     i = index >> 5;
  74     mask = 1 << (index & 0x1f);
  75     return !!(tab[i] & mask);
  76 }
  77
  78 /* return -1 if no bit is set */
  79 static int get_highest_priority_int(uint32_t *tab)
  80 {
  81     int i;
  82     for (i = 7; i >= 0; i--) {
  83         if (tab[i] != 0) {
  84             return i * 32 + apic_fls_bit(tab[i]);
  85         }
  86     }
  87     return -1;
  88 }
  89
  90 static void apic_sync_vapic(APICCommonState *s, int sync_type)
  91 {
  92     VAPICState vapic_state;
  93     size_t length;
  94     off_t start;
  95     int vector;
  96
  97     if (!s->vapic_paddr) {
  98         return;
  99     }
 100     if (sync_type & SYNC_FROM_VAPIC) {
 101         cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
 102                                  sizeof(vapic_state));
 103         s->tpr = vapic_state.tpr;
 104     }
 105     if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
 106         start = offsetof(VAPICState, isr);
 107         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
 108
 109         if (sync_type & SYNC_TO_VAPIC) {
 110             assert(qemu_cpu_is_self(CPU(s->cpu)));
 111
 112             vapic_state.tpr = s->tpr;
 113             vapic_state.enabled = 1;
 114             start = 0;
 115             length = sizeof(VAPICState);
 116         }
 117
 118         vector = get_highest_priority_int(s->isr);
 119         if (vector < 0) {
 120             vector = 0;
 121         }
 122         vapic_state.isr = vector & 0xf0;
 123
 124         vapic_state.zero = 0;
 125
 126         vector = get_highest_priority_int(s->irr);
 127         if (vector < 0) {
 128             vector = 0;
 129         }
 130         vapic_state.irr = vector & 0xff;
 131
 132         cpu_physical_memory_write_rom(&address_space_memory,
 133                                       s->vapic_paddr + start,
 134                                       ((void *)&vapic_state) + start, length);
 135     }
 136 }
 137
 138 static void apic_vapic_base_update(APICCommonState *s)
 139 {
 140     apic_sync_vapic(s, SYNC_TO_VAPIC);
 141 }
 142
 143 static void apic_local_deliver(APICCommonState *s, int vector)
 144 {
 145     uint32_t lvt = s->lvt[vector];
 146     int trigger_mode;
 147
 148     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 149
 150     if (lvt & APIC_LVT_MASKED)
 151         return;
 152
 153     switch ((lvt >> 8) & 7) {
 154     case APIC_DM_SMI:
 155         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
 156         break;
 157
 158     case APIC_DM_NMI:
 159         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
 160         break;
 161
 162     case APIC_DM_EXTINT:
 163         cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
 164         break;
 165
 166     case APIC_DM_FIXED:
 167         trigger_mode = APIC_TRIGGER_EDGE;
 168         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 169             (lvt & APIC_LVT_LEVEL_TRIGGER))
 170             trigger_mode = APIC_TRIGGER_LEVEL;
 171         apic_set_irq(s, lvt & 0xff, trigger_mode);
 172     }
 173 }
 174
 175 void apic_deliver_pic_intr(DeviceState *dev, int level)
 176 {
 177     APICCommonState *s = APIC_COMMON(dev);
 178
 179     if (level) {
 180         apic_local_deliver(s, APIC_LVT_LINT0);
 181     } else {
 182         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 183
 184         switch ((lvt >> 8) & 7) {
 185         case APIC_DM_FIXED:
 186             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 187                 break;
 188             apic_reset_bit(s->irr, lvt & 0xff);
 189             /* fall through */
 190         case APIC_DM_EXTINT:
 191             cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
 192             break;
 193         }
 194     }
 195 }
 196
 197 static void apic_external_nmi(APICCommonState *s)
 198 {
 199     apic_local_deliver(s, APIC_LVT_LINT1);
 200 }
 201
 202 #define foreach_apic(apic, deliver_bitmask, code) \
 203 {\
 204     int __i, __j;\
 205     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 206         uint32_t __mask = deliver_bitmask[__i];\
 207         if (__mask) {\
 208             for(__j = 0; __j < 32; __j++) {\
 209                 if (__mask & (1U << __j)) {\
 210                     apic = local_apics[__i * 32 + __j];\
 211                     if (apic) {\
 212                         code;\
 213                     }\
 214                 }\
 215             }\
 216         }\
 217     }\
 218 }
 219
 220 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 221                              uint8_t delivery_mode, uint8_t vector_num,
 222                              uint8_t trigger_mode)
 223 {
 224     APICCommonState *apic_iter;
 225
 226     switch (delivery_mode) {
 227         case APIC_DM_LOWPRI:
 228             /* XXX: search for focus processor, arbitration */
 229             {
 230                 int i, d;
 231                 d = -1;
 232                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 233                     if (deliver_bitmask[i]) {
 234                         d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
 235                         break;
 236                     }
 237                 }
 238                 if (d >= 0) {
 239                     apic_iter = local_apics[d];
 240                     if (apic_iter) {
 241                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 242                     }
 243                 }
 244             }
 245             return;
 246
 247         case APIC_DM_FIXED:
 248             break;
 249
 250         case APIC_DM_SMI:
 251             foreach_apic(apic_iter, deliver_bitmask,
 252                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
 253             );
 254             return;
 255
 256         case APIC_DM_NMI:
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                 cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
 259             );
 260             return;
 261
 262         case APIC_DM_INIT:
 263             /* normal INIT IPI sent to processors */
 264             foreach_apic(apic_iter, deliver_bitmask,
 265                          cpu_interrupt(CPU(apic_iter->cpu),
 266                                        CPU_INTERRUPT_INIT)
 267             );
 268             return;
 269
 270         case APIC_DM_EXTINT:
 271             /* handled in I/O APIC code */
 272             break;
 273
 274         default:
 275             return;
 276     }
 277
 278     foreach_apic(apic_iter, deliver_bitmask,
 279                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 280 }
 281
 282 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 283                       uint8_t vector_num, uint8_t trigger_mode)
 284 {
 285     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 286
 287     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 288                            trigger_mode);
 289
 290     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 291     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 292 }
 293
 294 static void apic_set_base(APICCommonState *s, uint64_t val)
 295 {
 296     s->apicbase = (val & 0xfffff000) |
 297         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 298     /* if disabled, cannot be enabled again */
 299     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 300         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 301         cpu_clear_apic_feature(&s->cpu->env);
 302         s->spurious_vec &= ~APIC_SV_ENABLE;
 303     }
 304 }
 305
 306 static void apic_set_tpr(APICCommonState *s, uint8_t val)
 307 {
 308     /* Updates from cr8 are ignored while the VAPIC is active */
 309     if (!s->vapic_paddr) {
 310         s->tpr = val << 4;
 311         apic_update_irq(s);
 312     }
 313 }
 314
 315 static uint8_t apic_get_tpr(APICCommonState *s)
 316 {
 317     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 318     return s->tpr >> 4;
 319 }
 320
 321 static int apic_get_ppr(APICCommonState *s)
 322 {
 323     int tpr, isrv, ppr;
 324
 325     tpr = (s->tpr >> 4);
 326     isrv = get_highest_priority_int(s->isr);
 327     if (isrv < 0)
 328         isrv = 0;
 329     isrv >>= 4;
 330     if (tpr >= isrv)
 331         ppr = s->tpr;
 332     else
 333         ppr = isrv << 4;
 334     return ppr;
 335 }
 336
 337 static int apic_get_arb_pri(APICCommonState *s)
 338 {
 339     /* XXX: arbitration */
 340     return 0;
 341 }
 342
 343
 344 /*
 345  * <0 - low prio interrupt,
 346  * 0  - no interrupt,
 347  * >0 - interrupt number
 348  */
 349 static int apic_irq_pending(APICCommonState *s)
 350 {
 351     int irrv, ppr;
 352
 353     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 354         return 0;
 355     }
 356
 357     irrv = get_highest_priority_int(s->irr);
 358     if (irrv < 0) {
 359         return 0;
 360     }
 361     ppr = apic_get_ppr(s);
 362     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 363         return -1;
 364     }
 365
 366     return irrv;
 367 }
 368
 369 /* signal the CPU if an irq is pending */
 370 static void apic_update_irq(APICCommonState *s)
 371 {
 372     CPUState *cpu;
 373
 374     cpu = CPU(s->cpu);
 375     if (!qemu_cpu_is_self(cpu)) {
 376         cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
 377     } else if (apic_irq_pending(s) > 0) {
 378         cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
 379     }
 380 }
 381
 382 void apic_poll_irq(DeviceState *dev)
 383 {
 384     APICCommonState *s = APIC_COMMON(dev);
 385
 386     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 387     apic_update_irq(s);
 388 }
 389
 390 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
 391 {
 392     apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
 393
 394     apic_set_bit(s->irr, vector_num);
 395     if (trigger_mode)
 396         apic_set_bit(s->tmr, vector_num);
 397     else
 398         apic_reset_bit(s->tmr, vector_num);
 399     if (s->vapic_paddr) {
 400         apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
 401         /*
 402          * The vcpu thread needs to see the new IRR before we pull its current
 403          * TPR value. That way, if we miss a lowering of the TRP, the guest
 404          * has the chance to notice the new IRR and poll for IRQs on its own.
 405          */
 406         smp_wmb();
 407         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 408     }
 409     apic_update_irq(s);
 410 }
 411
 412 static void apic_eoi(APICCommonState *s)
 413 {
 414     int isrv;
 415     isrv = get_highest_priority_int(s->isr);
 416     if (isrv < 0)
 417         return;
 418     apic_reset_bit(s->isr, isrv);
 419     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
 420         ioapic_eoi_broadcast(isrv);
 421     }
 422     apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
 423     apic_update_irq(s);
 424 }
 425
 426 static int apic_find_dest(uint8_t dest)
 427 {
 428     APICCommonState *apic = local_apics[dest];
 429     int i;
 430
 431     if (apic && apic->id == dest)
 432         return dest;  /* shortcut in case apic->id == apic->idx */
 433
 434     for (i = 0; i < MAX_APICS; i++) {
 435         apic = local_apics[i];
 436         if (apic && apic->id == dest)
 437             return i;
 438         if (!apic)
 439             break;
 440     }
 441
 442     return -1;
 443 }
 444
 445 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 446                                       uint8_t dest, uint8_t dest_mode)
 447 {
 448     APICCommonState *apic_iter;
 449     int i;
 450
 451     if (dest_mode == 0) {
 452         if (dest == 0xff) {
 453             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 454         } else {
 455             int idx = apic_find_dest(dest);
 456             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 457             if (idx >= 0)
 458                 apic_set_bit(deliver_bitmask, idx);
 459         }
 460     } else {
 461         /* XXX: cluster mode */
 462         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 463         for(i = 0; i < MAX_APICS; i++) {
 464             apic_iter = local_apics[i];
 465             if (apic_iter) {
 466                 if (apic_iter->dest_mode == 0xf) {
 467                     if (dest & apic_iter->log_dest)
 468                         apic_set_bit(deliver_bitmask, i);
 469                 } else if (apic_iter->dest_mode == 0x0) {
 470                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 471                         (dest & apic_iter->log_dest & 0x0f)) {
 472                         apic_set_bit(deliver_bitmask, i);
 473                     }
 474                 }
 475             } else {
 476                 break;
 477             }
 478         }
 479     }
 480 }
 481
 482 static void apic_startup(APICCommonState *s, int vector_num)
 483 {
 484     s->sipi_vector = vector_num;
 485     cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 486 }
 487
 488 void apic_sipi(DeviceState *dev)
 489 {
 490     APICCommonState *s = APIC_COMMON(dev);
 491
 492     cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
 493
 494     if (!s->wait_for_sipi)
 495         return;
 496     cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
 497     s->wait_for_sipi = 0;
 498 }
 499
 500 static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
 501                          uint8_t delivery_mode, uint8_t vector_num,
 502                          uint8_t trigger_mode)
 503 {
 504     APICCommonState *s = APIC_COMMON(dev);
 505     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 506     int dest_shorthand = (s->icr[0] >> 18) & 3;
 507     APICCommonState *apic_iter;
 508
 509     switch (dest_shorthand) {
 510     case 0:
 511         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 512         break;
 513     case 1:
 514         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 515         apic_set_bit(deliver_bitmask, s->idx);
 516         break;
 517     case 2:
 518         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 519         break;
 520     case 3:
 521         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 522         apic_reset_bit(deliver_bitmask, s->idx);
 523         break;
 524     }
 525
 526     switch (delivery_mode) {
 527         case APIC_DM_INIT:
 528             {
 529                 int trig_mode = (s->icr[0] >> 15) & 1;
 530                 int level = (s->icr[0] >> 14) & 1;
 531                 if (level == 0 && trig_mode == 1) {
 532                     foreach_apic(apic_iter, deliver_bitmask,
 533                                  apic_iter->arb_id = apic_iter->id );
 534                     return;
 535                 }
 536             }
 537             break;
 538
 539         case APIC_DM_SIPI:
 540             foreach_apic(apic_iter, deliver_bitmask,
 541                          apic_startup(apic_iter, vector_num) );
 542             return;
 543     }
 544
 545     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 546 }
 547
 548 static bool apic_check_pic(APICCommonState *s)
 549 {
 550     if (!apic_accept_pic_intr(&s->busdev.qdev) || !pic_get_output(isa_pic)) {
 551         return false;
 552     }
 553     apic_deliver_pic_intr(&s->busdev.qdev, 1);
 554     return true;
 555 }
 556
 557 int apic_get_interrupt(DeviceState *dev)
 558 {
 559     APICCommonState *s = APIC_COMMON(dev);
 560     int intno;
 561
 562     /* if the APIC is installed or enabled, we let the 8259 handle the
 563        IRQs */
 564     if (!s)
 565         return -1;
 566     if (!(s->spurious_vec & APIC_SV_ENABLE))
 567         return -1;
 568
 569     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 570     intno = apic_irq_pending(s);
 571
 572     if (intno == 0) {
 573         apic_sync_vapic(s, SYNC_TO_VAPIC);
 574         return -1;
 575     } else if (intno < 0) {
 576         apic_sync_vapic(s, SYNC_TO_VAPIC);
 577         return s->spurious_vec & 0xff;
 578     }
 579     apic_reset_bit(s->irr, intno);
 580     apic_set_bit(s->isr, intno);
 581     apic_sync_vapic(s, SYNC_TO_VAPIC);
 582
 583     /* re-inject if there is still a pending PIC interrupt */
 584     apic_check_pic(s);
 585
 586     apic_update_irq(s);
 587
 588     return intno;
 589 }
 590
 591 int apic_accept_pic_intr(DeviceState *dev)
 592 {
 593     APICCommonState *s = APIC_COMMON(dev);
 594     uint32_t lvt0;
 595
 596     if (!s)
 597         return -1;
 598
 599     lvt0 = s->lvt[APIC_LVT_LINT0];
 600
 601     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 602         (lvt0 & APIC_LVT_MASKED) == 0)
 603         return 1;
 604
 605     return 0;
 606 }
 607
 608 static uint32_t apic_get_current_count(APICCommonState *s)
 609 {
 610     int64_t d;
 611     uint32_t val;
 612     d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
 613         s->count_shift;
 614     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 615         /* periodic */
 616         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 617     } else {
 618         if (d >= s->initial_count)
 619             val = 0;
 620         else
 621             val = s->initial_count - d;
 622     }
 623     return val;
 624 }
 625
 626 static void apic_timer_update(APICCommonState *s, int64_t current_time)
 627 {
 628     if (apic_next_timer(s, current_time)) {
 629         timer_mod(s->timer, s->next_time);
 630     } else {
 631         timer_del(s->timer);
 632     }
 633 }
 634
 635 static void apic_timer(void *opaque)
 636 {
 637     APICCommonState *s = opaque;
 638
 639     apic_local_deliver(s, APIC_LVT_TIMER);
 640     apic_timer_update(s, s->next_time);
 641 }
 642
 643 static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
 644 {
 645     return 0;
 646 }
 647
 648 static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
 649 {
 650     return 0;
 651 }
 652
 653 static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
 654 {
 655 }
 656
 657 static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
 658 {
 659 }
 660
 661 static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
 662 {
 663     DeviceState *dev;
 664     APICCommonState *s;
 665     uint32_t val;
 666     int index;
 667
 668     dev = cpu_get_current_apic();
 669     if (!dev) {
 670         return 0;
 671     }
 672     s = APIC_COMMON(dev);
 673
 674     index = (addr >> 4) & 0xff;
 675     switch(index) {
 676     case 0x02: /* id */
 677         val = s->id << 24;
 678         break;
 679     case 0x03: /* version */
 680         val = s->version | ((APIC_LVT_NB - 1) << 16);
 681         break;
 682     case 0x08:
 683         apic_sync_vapic(s, SYNC_FROM_VAPIC);
 684         if (apic_report_tpr_access) {
 685             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
 686         }
 687         val = s->tpr;
 688         break;
 689     case 0x09:
 690         val = apic_get_arb_pri(s);
 691         break;
 692     case 0x0a:
 693         /* ppr */
 694         val = apic_get_ppr(s);
 695         break;
 696     case 0x0b:
 697         val = 0;
 698         break;
 699     case 0x0d:
 700         val = s->log_dest << 24;
 701         break;
 702     case 0x0e:
 703         val = (s->dest_mode << 28) | 0xfffffff;
 704         break;
 705     case 0x0f:
 706         val = s->spurious_vec;
 707         break;
 708     case 0x10 ... 0x17:
 709         val = s->isr[index & 7];
 710         break;
 711     case 0x18 ... 0x1f:
 712         val = s->tmr[index & 7];
 713         break;
 714     case 0x20 ... 0x27:
 715         val = s->irr[index & 7];
 716         break;
 717     case 0x28:
 718         val = s->esr;
 719         break;
 720     case 0x30:
 721     case 0x31:
 722         val = s->icr[index & 1];
 723         break;
 724     case 0x32 ... 0x37:
 725         val = s->lvt[index - 0x32];
 726         break;
 727     case 0x38:
 728         val = s->initial_count;
 729         break;
 730     case 0x39:
 731         val = apic_get_current_count(s);
 732         break;
 733     case 0x3e:
 734         val = s->divide_conf;
 735         break;
 736     default:
 737         s->esr |= ESR_ILLEGAL_ADDRESS;
 738         val = 0;
 739         break;
 740     }
 741     trace_apic_mem_readl(addr, val);
 742     return val;
 743 }
 744
 745 static void apic_send_msi(hwaddr addr, uint32_t data)
 746 {
 747     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 748     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 749     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 750     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 751     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 752     /* XXX: Ignore redirection hint. */
 753     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 754 }
 755
 756 static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
 757 {
 758     DeviceState *dev;
 759     APICCommonState *s;
 760     int index = (addr >> 4) & 0xff;
 761     if (addr > 0xfff || !index) {
 762         /* MSI and MMIO APIC are at the same memory location,
 763          * but actually not on the global bus: MSI is on PCI bus
 764          * APIC is connected directly to the CPU.
 765          * Mapping them on the global bus happens to work because
 766          * MSI registers are reserved in APIC MMIO and vice versa. */
 767         apic_send_msi(addr, val);
 768         return;
 769     }
 770
 771     dev = cpu_get_current_apic();
 772     if (!dev) {
 773         return;
 774     }
 775     s = APIC_COMMON(dev);
 776
 777     trace_apic_mem_writel(addr, val);
 778
 779     switch(index) {
 780     case 0x02:
 781         s->id = (val >> 24);
 782         break;
 783     case 0x03:
 784         break;
 785     case 0x08:
 786         if (apic_report_tpr_access) {
 787             cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
 788         }
 789         s->tpr = val;
 790         apic_sync_vapic(s, SYNC_TO_VAPIC);
 791         apic_update_irq(s);
 792         break;
 793     case 0x09:
 794     case 0x0a:
 795         break;
 796     case 0x0b: /* EOI */
 797         apic_eoi(s);
 798         break;
 799     case 0x0d:
 800         s->log_dest = val >> 24;
 801         break;
 802     case 0x0e:
 803         s->dest_mode = val >> 28;
 804         break;
 805     case 0x0f:
 806         s->spurious_vec = val & 0x1ff;
 807         apic_update_irq(s);
 808         break;
 809     case 0x10 ... 0x17:
 810     case 0x18 ... 0x1f:
 811     case 0x20 ... 0x27:
 812     case 0x28:
 813         break;
 814     case 0x30:
 815         s->icr[0] = val;
 816         apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 817                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 818                      (s->icr[0] >> 15) & 1);
 819         break;
 820     case 0x31:
 821         s->icr[1] = val;
 822         break;
 823     case 0x32 ... 0x37:
 824         {
 825             int n = index - 0x32;
 826             s->lvt[n] = val;
 827             if (n == APIC_LVT_TIMER) {
 828                 apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 829             } else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
 830                 apic_update_irq(s);
 831             }
 832         }
 833         break;
 834     case 0x38:
 835         s->initial_count = val;
 836         s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 837         apic_timer_update(s, s->initial_count_load_time);
 838         break;
 839     case 0x39:
 840         break;
 841     case 0x3e:
 842         {
 843             int v;
 844             s->divide_conf = val & 0xb;
 845             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 846             s->count_shift = (v + 1) & 7;
 847         }
 848         break;
 849     default:
 850         s->esr |= ESR_ILLEGAL_ADDRESS;
 851         break;
 852     }
 853 }
 854
 855 static void apic_pre_save(APICCommonState *s)
 856 {
 857     apic_sync_vapic(s, SYNC_FROM_VAPIC);
 858 }
 859
 860 static void apic_post_load(APICCommonState *s)
 861 {
 862     if (s->timer_expiry != -1) {
 863         timer_mod(s->timer, s->timer_expiry);
 864     } else {
 865         timer_del(s->timer);
 866     }
 867 }
 868
 869 static const MemoryRegionOps apic_io_ops = {
 870     .old_mmio = {
 871         .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
 872         .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
 873     },
 874     .endianness = DEVICE_NATIVE_ENDIAN,
 875 };
 876
 877 static void apic_realize(DeviceState *dev, Error **errp)
 878 {
 879     APICCommonState *s = APIC_COMMON(dev);
 880
 881     memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
 882                           APIC_SPACE_SIZE);
 883
 884     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
 885     local_apics[s->idx] = s;
 886
 887     msi_supported = true;
 888 }
 889
 890 static void apic_class_init(ObjectClass *klass, void *data)
 891 {
 892     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 893
 894     k->realize = apic_realize;
 895     k->set_base = apic_set_base;
 896     k->set_tpr = apic_set_tpr;
 897     k->get_tpr = apic_get_tpr;
 898     k->vapic_base_update = apic_vapic_base_update;
 899     k->external_nmi = apic_external_nmi;
 900     k->pre_save = apic_pre_save;
 901     k->post_load = apic_post_load;
 902 }
 903
 904 static const TypeInfo apic_info = {
 905     .name          = "apic",
 906     .instance_size = sizeof(APICCommonState),
 907     .parent        = TYPE_APIC_COMMON,
 908     .class_init    = apic_class_init,
 909 };
 910
 911 static void apic_register_types(void)
 912 {
 913     type_register_static(&apic_info);
 914 }
 915
 916 type_init(apic_register_types)