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acpi: add interface to access user-installed tables
[qemu.git] / hw / display / vmware_vga.c
bloba6a8cdc2e18cd8f61052f5d76b7732aba5d3dbec
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/loader.h"
26 #include "ui/console.h"
27 #include "hw/pci/pci.h"
28
29 #undef VERBOSE
30 #define HW_RECT_ACCEL
31 #define HW_FILL_ACCEL
32 #define HW_MOUSE_ACCEL
33
34 #include "vga_int.h"
35
36 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
37
38 struct vmsvga_state_s {
39 VGACommonState vga;
40
41 int invalidated;
42 int enable;
43 int config;
44 struct {
45 int id;
46 int x;
47 int y;
48 int on;
49 } cursor;
50
51 int index;
52 int scratch_size;
53 uint32_t *scratch;
54 int new_width;
55 int new_height;
56 int new_depth;
57 uint32_t guest;
58 uint32_t svgaid;
59 int syncing;
60
61 MemoryRegion fifo_ram;
62 uint8_t *fifo_ptr;
63 unsigned int fifo_size;
64
65 union {
66 uint32_t *fifo;
67 struct QEMU_PACKED {
68 uint32_t min;
69 uint32_t max;
70 uint32_t next_cmd;
71 uint32_t stop;
72 /* Add registers here when adding capabilities. */
73 uint32_t fifo[0];
74 } *cmd;
75 };
76
77 #define REDRAW_FIFO_LEN 512
78 struct vmsvga_rect_s {
79 int x, y, w, h;
80 } redraw_fifo[REDRAW_FIFO_LEN];
81 int redraw_fifo_first, redraw_fifo_last;
82 };
83
84 #define TYPE_VMWARE_SVGA "vmware-svga"
85
86 #define VMWARE_SVGA(obj) \
87 OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
88
89 struct pci_vmsvga_state_s {
90 /*< private >*/
91 PCIDevice parent_obj;
92 /*< public >*/
93
94 struct vmsvga_state_s chip;
95 MemoryRegion io_bar;
96 };
97
98 #define SVGA_MAGIC 0x900000UL
99 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
100 #define SVGA_ID_0 SVGA_MAKE_ID(0)
101 #define SVGA_ID_1 SVGA_MAKE_ID(1)
102 #define SVGA_ID_2 SVGA_MAKE_ID(2)
103
104 #define SVGA_LEGACY_BASE_PORT 0x4560
105 #define SVGA_INDEX_PORT 0x0
106 #define SVGA_VALUE_PORT 0x1
107 #define SVGA_BIOS_PORT 0x2
108
109 #define SVGA_VERSION_2
110
111 #ifdef SVGA_VERSION_2
112 # define SVGA_ID SVGA_ID_2
113 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
114 # define SVGA_IO_MUL 1
115 # define SVGA_FIFO_SIZE 0x10000
116 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
117 #else
118 # define SVGA_ID SVGA_ID_1
119 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
120 # define SVGA_IO_MUL 4
121 # define SVGA_FIFO_SIZE 0x10000
122 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
123 #endif
124
125 enum {
126 /* ID 0, 1 and 2 registers */
127 SVGA_REG_ID = 0,
128 SVGA_REG_ENABLE = 1,
129 SVGA_REG_WIDTH = 2,
130 SVGA_REG_HEIGHT = 3,
131 SVGA_REG_MAX_WIDTH = 4,
132 SVGA_REG_MAX_HEIGHT = 5,
133 SVGA_REG_DEPTH = 6,
134 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
135 SVGA_REG_PSEUDOCOLOR = 8,
136 SVGA_REG_RED_MASK = 9,
137 SVGA_REG_GREEN_MASK = 10,
138 SVGA_REG_BLUE_MASK = 11,
139 SVGA_REG_BYTES_PER_LINE = 12,
140 SVGA_REG_FB_START = 13,
141 SVGA_REG_FB_OFFSET = 14,
142 SVGA_REG_VRAM_SIZE = 15,
143 SVGA_REG_FB_SIZE = 16,
144
145 /* ID 1 and 2 registers */
146 SVGA_REG_CAPABILITIES = 17,
147 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
148 SVGA_REG_MEM_SIZE = 19,
149 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
150 SVGA_REG_SYNC = 21, /* Write to force synchronization */
151 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
152 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
153 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
154 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
155 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
156 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
157 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
158 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
159 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
160 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
161 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
162
163 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
164 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
165 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
166 };
167
168 #define SVGA_CAP_NONE 0
169 #define SVGA_CAP_RECT_FILL (1 << 0)
170 #define SVGA_CAP_RECT_COPY (1 << 1)
171 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
172 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
173 #define SVGA_CAP_RASTER_OP (1 << 4)
174 #define SVGA_CAP_CURSOR (1 << 5)
175 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
176 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
177 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
178 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
179 #define SVGA_CAP_GLYPH (1 << 10)
180 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
181 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
182 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
183 #define SVGA_CAP_3D (1 << 14)
184 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
185 #define SVGA_CAP_MULTIMON (1 << 16)
186 #define SVGA_CAP_PITCHLOCK (1 << 17)
187
188 /*
189 * FIFO offsets (seen as an array of 32-bit words)
190 */
191 enum {
192 /*
193 * The original defined FIFO offsets
194 */
195 SVGA_FIFO_MIN = 0,
196 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
197 SVGA_FIFO_NEXT_CMD,
198 SVGA_FIFO_STOP,
199
200 /*
201 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
202 */
203 SVGA_FIFO_CAPABILITIES = 4,
204 SVGA_FIFO_FLAGS,
205 SVGA_FIFO_FENCE,
206 SVGA_FIFO_3D_HWVERSION,
207 SVGA_FIFO_PITCHLOCK,
208 };
209
210 #define SVGA_FIFO_CAP_NONE 0
211 #define SVGA_FIFO_CAP_FENCE (1 << 0)
212 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
213 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
214
215 #define SVGA_FIFO_FLAG_NONE 0
216 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
217
218 /* These values can probably be changed arbitrarily. */
219 #define SVGA_SCRATCH_SIZE 0x8000
220 #define SVGA_MAX_WIDTH 2360
221 #define SVGA_MAX_HEIGHT 1770
222
223 #ifdef VERBOSE
224 # define GUEST_OS_BASE 0x5001
225 static const char *vmsvga_guest_id[] = {
226 [0x00] = "Dos",
227 [0x01] = "Windows 3.1",
228 [0x02] = "Windows 95",
229 [0x03] = "Windows 98",
230 [0x04] = "Windows ME",
231 [0x05] = "Windows NT",
232 [0x06] = "Windows 2000",
233 [0x07] = "Linux",
234 [0x08] = "OS/2",
235 [0x09] = "an unknown OS",
236 [0x0a] = "BSD",
237 [0x0b] = "Whistler",
238 [0x0c] = "an unknown OS",
239 [0x0d] = "an unknown OS",
240 [0x0e] = "an unknown OS",
241 [0x0f] = "an unknown OS",
242 [0x10] = "an unknown OS",
243 [0x11] = "an unknown OS",
244 [0x12] = "an unknown OS",
245 [0x13] = "an unknown OS",
246 [0x14] = "an unknown OS",
247 [0x15] = "Windows 2003",
248 };
249 #endif
250
251 enum {
252 SVGA_CMD_INVALID_CMD = 0,
253 SVGA_CMD_UPDATE = 1,
254 SVGA_CMD_RECT_FILL = 2,
255 SVGA_CMD_RECT_COPY = 3,
256 SVGA_CMD_DEFINE_BITMAP = 4,
257 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
258 SVGA_CMD_DEFINE_PIXMAP = 6,
259 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
260 SVGA_CMD_RECT_BITMAP_FILL = 8,
261 SVGA_CMD_RECT_PIXMAP_FILL = 9,
262 SVGA_CMD_RECT_BITMAP_COPY = 10,
263 SVGA_CMD_RECT_PIXMAP_COPY = 11,
264 SVGA_CMD_FREE_OBJECT = 12,
265 SVGA_CMD_RECT_ROP_FILL = 13,
266 SVGA_CMD_RECT_ROP_COPY = 14,
267 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
268 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
269 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
270 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
271 SVGA_CMD_DEFINE_CURSOR = 19,
272 SVGA_CMD_DISPLAY_CURSOR = 20,
273 SVGA_CMD_MOVE_CURSOR = 21,
274 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
275 SVGA_CMD_DRAW_GLYPH = 23,
276 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
277 SVGA_CMD_UPDATE_VERBOSE = 25,
278 SVGA_CMD_SURFACE_FILL = 26,
279 SVGA_CMD_SURFACE_COPY = 27,
280 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
281 SVGA_CMD_FRONT_ROP_FILL = 29,
282 SVGA_CMD_FENCE = 30,
283 };
284
285 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
286 enum {
287 SVGA_CURSOR_ON_HIDE = 0,
288 SVGA_CURSOR_ON_SHOW = 1,
289 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
290 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
291 };
292
293 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
294 int x, int y, int w, int h)
295 {
296 DisplaySurface *surface = qemu_console_surface(s->vga.con);
297 int line;
298 int bypl;
299 int width;
300 int start;
301 uint8_t *src;
302 uint8_t *dst;
303
304 if (x < 0) {
305 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x);
306 w += x;
307 x = 0;
308 }
309 if (w < 0) {
310 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w);
311 w = 0;
312 }
313 if (x + w > surface_width(surface)) {
314 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
315 __func__, x, w);
316 x = MIN(x, surface_width(surface));
317 w = surface_width(surface) - x;
318 }
319
320 if (y < 0) {
321 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y);
322 h += y;
323 y = 0;
324 }
325 if (h < 0) {
326 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h);
327 h = 0;
328 }
329 if (y + h > surface_height(surface)) {
330 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
331 __func__, y, h);
332 y = MIN(y, surface_height(surface));
333 h = surface_height(surface) - y;
334 }
335
336 bypl = surface_stride(surface);
337 width = surface_bytes_per_pixel(surface) * w;
338 start = surface_bytes_per_pixel(surface) * x + bypl * y;
339 src = s->vga.vram_ptr + start;
340 dst = surface_data(surface) + start;
341
342 for (line = h; line > 0; line--, src += bypl, dst += bypl) {
343 memcpy(dst, src, width);
344 }
345 dpy_gfx_update(s->vga.con, x, y, w, h);
346 }
347
348 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
349 int x, int y, int w, int h)
350 {
351 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
352
353 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
354 rect->x = x;
355 rect->y = y;
356 rect->w = w;
357 rect->h = h;
358 }
359
360 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
361 {
362 struct vmsvga_rect_s *rect;
363
364 if (s->invalidated) {
365 s->redraw_fifo_first = s->redraw_fifo_last;
366 return;
367 }
368 /* Overlapping region updates can be optimised out here - if someone
369 * knows a smart algorithm to do that, please share. */
370 while (s->redraw_fifo_first != s->redraw_fifo_last) {
371 rect = &s->redraw_fifo[s->redraw_fifo_first++];
372 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
373 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
374 }
375 }
376
377 #ifdef HW_RECT_ACCEL
378 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
379 int x0, int y0, int x1, int y1, int w, int h)
380 {
381 DisplaySurface *surface = qemu_console_surface(s->vga.con);
382 uint8_t *vram = s->vga.vram_ptr;
383 int bypl = surface_stride(surface);
384 int bypp = surface_bytes_per_pixel(surface);
385 int width = bypp * w;
386 int line = h;
387 uint8_t *ptr[2];
388
389 if (y1 > y0) {
390 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
391 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
392 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
393 memmove(ptr[1], ptr[0], width);
394 }
395 } else {
396 ptr[0] = vram + bypp * x0 + bypl * y0;
397 ptr[1] = vram + bypp * x1 + bypl * y1;
398 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
399 memmove(ptr[1], ptr[0], width);
400 }
401 }
402
403 vmsvga_update_rect_delayed(s, x1, y1, w, h);
404 }
405 #endif
406
407 #ifdef HW_FILL_ACCEL
408 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
409 uint32_t c, int x, int y, int w, int h)
410 {
411 DisplaySurface *surface = qemu_console_surface(s->vga.con);
412 int bypl = surface_stride(surface);
413 int width = surface_bytes_per_pixel(surface) * w;
414 int line = h;
415 int column;
416 uint8_t *fst;
417 uint8_t *dst;
418 uint8_t *src;
419 uint8_t col[4];
420
421 col[0] = c;
422 col[1] = c >> 8;
423 col[2] = c >> 16;
424 col[3] = c >> 24;
425
426 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
427
428 if (line--) {
429 dst = fst;
430 src = col;
431 for (column = width; column > 0; column--) {
432 *(dst++) = *(src++);
433 if (src - col == surface_bytes_per_pixel(surface)) {
434 src = col;
435 }
436 }
437 dst = fst;
438 for (; line > 0; line--) {
439 dst += bypl;
440 memcpy(dst, fst, width);
441 }
442 }
443
444 vmsvga_update_rect_delayed(s, x, y, w, h);
445 }
446 #endif
447
448 struct vmsvga_cursor_definition_s {
449 int width;
450 int height;
451 int id;
452 int bpp;
453 int hot_x;
454 int hot_y;
455 uint32_t mask[1024];
456 uint32_t image[4096];
457 };
458
459 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
460 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
461
462 #ifdef HW_MOUSE_ACCEL
463 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
464 struct vmsvga_cursor_definition_s *c)
465 {
466 QEMUCursor *qc;
467 int i, pixels;
468
469 qc = cursor_alloc(c->width, c->height);
470 qc->hot_x = c->hot_x;
471 qc->hot_y = c->hot_y;
472 switch (c->bpp) {
473 case 1:
474 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
475 1, (void *)c->mask);
476 #ifdef DEBUG
477 cursor_print_ascii_art(qc, "vmware/mono");
478 #endif
479 break;
480 case 32:
481 /* fill alpha channel from mask, set color to zero */
482 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
483 1, (void *)c->mask);
484 /* add in rgb values */
485 pixels = c->width * c->height;
486 for (i = 0; i < pixels; i++) {
487 qc->data[i] |= c->image[i] & 0xffffff;
488 }
489 #ifdef DEBUG
490 cursor_print_ascii_art(qc, "vmware/32bit");
491 #endif
492 break;
493 default:
494 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
495 __func__, c->bpp);
496 cursor_put(qc);
497 qc = cursor_builtin_left_ptr();
498 }
499
500 dpy_cursor_define(s->vga.con, qc);
501 cursor_put(qc);
502 }
503 #endif
504
505 #define CMD(f) le32_to_cpu(s->cmd->f)
506
507 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
508 {
509 int num;
510
511 if (!s->config || !s->enable) {
512 return 0;
513 }
514 num = CMD(next_cmd) - CMD(stop);
515 if (num < 0) {
516 num += CMD(max) - CMD(min);
517 }
518 return num >> 2;
519 }
520
521 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
522 {
523 uint32_t cmd = s->fifo[CMD(stop) >> 2];
524
525 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
526 if (CMD(stop) >= CMD(max)) {
527 s->cmd->stop = s->cmd->min;
528 }
529 return cmd;
530 }
531
532 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
533 {
534 return le32_to_cpu(vmsvga_fifo_read_raw(s));
535 }
536
537 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
538 {
539 uint32_t cmd, colour;
540 int args, len;
541 int x, y, dx, dy, width, height;
542 struct vmsvga_cursor_definition_s cursor;
543 uint32_t cmd_start;
544
545 len = vmsvga_fifo_length(s);
546 while (len > 0) {
547 /* May need to go back to the start of the command if incomplete */
548 cmd_start = s->cmd->stop;
549
550 switch (cmd = vmsvga_fifo_read(s)) {
551 case SVGA_CMD_UPDATE:
552 case SVGA_CMD_UPDATE_VERBOSE:
553 len -= 5;
554 if (len < 0) {
555 goto rewind;
556 }
557
558 x = vmsvga_fifo_read(s);
559 y = vmsvga_fifo_read(s);
560 width = vmsvga_fifo_read(s);
561 height = vmsvga_fifo_read(s);
562 vmsvga_update_rect_delayed(s, x, y, width, height);
563 break;
564
565 case SVGA_CMD_RECT_FILL:
566 len -= 6;
567 if (len < 0) {
568 goto rewind;
569 }
570
571 colour = vmsvga_fifo_read(s);
572 x = vmsvga_fifo_read(s);
573 y = vmsvga_fifo_read(s);
574 width = vmsvga_fifo_read(s);
575 height = vmsvga_fifo_read(s);
576 #ifdef HW_FILL_ACCEL
577 vmsvga_fill_rect(s, colour, x, y, width, height);
578 break;
579 #else
580 args = 0;
581 goto badcmd;
582 #endif
583
584 case SVGA_CMD_RECT_COPY:
585 len -= 7;
586 if (len < 0) {
587 goto rewind;
588 }
589
590 x = vmsvga_fifo_read(s);
591 y = vmsvga_fifo_read(s);
592 dx = vmsvga_fifo_read(s);
593 dy = vmsvga_fifo_read(s);
594 width = vmsvga_fifo_read(s);
595 height = vmsvga_fifo_read(s);
596 #ifdef HW_RECT_ACCEL
597 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
598 break;
599 #else
600 args = 0;
601 goto badcmd;
602 #endif
603
604 case SVGA_CMD_DEFINE_CURSOR:
605 len -= 8;
606 if (len < 0) {
607 goto rewind;
608 }
609
610 cursor.id = vmsvga_fifo_read(s);
611 cursor.hot_x = vmsvga_fifo_read(s);
612 cursor.hot_y = vmsvga_fifo_read(s);
613 cursor.width = x = vmsvga_fifo_read(s);
614 cursor.height = y = vmsvga_fifo_read(s);
615 vmsvga_fifo_read(s);
616 cursor.bpp = vmsvga_fifo_read(s);
617
618 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
619 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
620 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
621 goto badcmd;
622 }
623
624 len -= args;
625 if (len < 0) {
626 goto rewind;
627 }
628
629 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
630 cursor.mask[args] = vmsvga_fifo_read_raw(s);
631 }
632 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
633 cursor.image[args] = vmsvga_fifo_read_raw(s);
634 }
635 #ifdef HW_MOUSE_ACCEL
636 vmsvga_cursor_define(s, &cursor);
637 break;
638 #else
639 args = 0;
640 goto badcmd;
641 #endif
642
643 /*
644 * Other commands that we at least know the number of arguments
645 * for so we can avoid FIFO desync if driver uses them illegally.
646 */
647 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
648 len -= 6;
649 if (len < 0) {
650 goto rewind;
651 }
652 vmsvga_fifo_read(s);
653 vmsvga_fifo_read(s);
654 vmsvga_fifo_read(s);
655 x = vmsvga_fifo_read(s);
656 y = vmsvga_fifo_read(s);
657 args = x * y;
658 goto badcmd;
659 case SVGA_CMD_RECT_ROP_FILL:
660 args = 6;
661 goto badcmd;
662 case SVGA_CMD_RECT_ROP_COPY:
663 args = 7;
664 goto badcmd;
665 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
666 len -= 4;
667 if (len < 0) {
668 goto rewind;
669 }
670 vmsvga_fifo_read(s);
671 vmsvga_fifo_read(s);
672 args = 7 + (vmsvga_fifo_read(s) >> 2);
673 goto badcmd;
674 case SVGA_CMD_SURFACE_ALPHA_BLEND:
675 args = 12;
676 goto badcmd;
677
678 /*
679 * Other commands that are not listed as depending on any
680 * CAPABILITIES bits, but are not described in the README either.
681 */
682 case SVGA_CMD_SURFACE_FILL:
683 case SVGA_CMD_SURFACE_COPY:
684 case SVGA_CMD_FRONT_ROP_FILL:
685 case SVGA_CMD_FENCE:
686 case SVGA_CMD_INVALID_CMD:
687 break; /* Nop */
688
689 default:
690 args = 0;
691 badcmd:
692 len -= args;
693 if (len < 0) {
694 goto rewind;
695 }
696 while (args--) {
697 vmsvga_fifo_read(s);
698 }
699 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
700 __func__, cmd);
701 break;
702
703 rewind:
704 s->cmd->stop = cmd_start;
705 break;
706 }
707 }
708
709 s->syncing = 0;
710 }
711
712 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
713 {
714 struct vmsvga_state_s *s = opaque;
715
716 return s->index;
717 }
718
719 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
720 {
721 struct vmsvga_state_s *s = opaque;
722
723 s->index = index;
724 }
725
726 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
727 {
728 uint32_t caps;
729 struct vmsvga_state_s *s = opaque;
730 DisplaySurface *surface = qemu_console_surface(s->vga.con);
731 PixelFormat pf;
732 uint32_t ret;
733
734 switch (s->index) {
735 case SVGA_REG_ID:
736 ret = s->svgaid;
737 break;
738
739 case SVGA_REG_ENABLE:
740 ret = s->enable;
741 break;
742
743 case SVGA_REG_WIDTH:
744 ret = s->new_width ? s->new_width : surface_width(surface);
745 break;
746
747 case SVGA_REG_HEIGHT:
748 ret = s->new_height ? s->new_height : surface_height(surface);
749 break;
750
751 case SVGA_REG_MAX_WIDTH:
752 ret = SVGA_MAX_WIDTH;
753 break;
754
755 case SVGA_REG_MAX_HEIGHT:
756 ret = SVGA_MAX_HEIGHT;
757 break;
758
759 case SVGA_REG_DEPTH:
760 ret = (s->new_depth == 32) ? 24 : s->new_depth;
761 break;
762
763 case SVGA_REG_BITS_PER_PIXEL:
764 case SVGA_REG_HOST_BITS_PER_PIXEL:
765 ret = s->new_depth;
766 break;
767
768 case SVGA_REG_PSEUDOCOLOR:
769 ret = 0x0;
770 break;
771
772 case SVGA_REG_RED_MASK:
773 pf = qemu_default_pixelformat(s->new_depth);
774 ret = pf.rmask;
775 break;
776
777 case SVGA_REG_GREEN_MASK:
778 pf = qemu_default_pixelformat(s->new_depth);
779 ret = pf.gmask;
780 break;
781
782 case SVGA_REG_BLUE_MASK:
783 pf = qemu_default_pixelformat(s->new_depth);
784 ret = pf.bmask;
785 break;
786
787 case SVGA_REG_BYTES_PER_LINE:
788 if (s->new_width) {
789 ret = (s->new_depth * s->new_width) / 8;
790 } else {
791 ret = surface_stride(surface);
792 }
793 break;
794
795 case SVGA_REG_FB_START: {
796 struct pci_vmsvga_state_s *pci_vmsvga
797 = container_of(s, struct pci_vmsvga_state_s, chip);
798 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
799 break;
800 }
801
802 case SVGA_REG_FB_OFFSET:
803 ret = 0x0;
804 break;
805
806 case SVGA_REG_VRAM_SIZE:
807 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
808 break;
809
810 case SVGA_REG_FB_SIZE:
811 ret = s->vga.vram_size;
812 break;
813
814 case SVGA_REG_CAPABILITIES:
815 caps = SVGA_CAP_NONE;
816 #ifdef HW_RECT_ACCEL
817 caps |= SVGA_CAP_RECT_COPY;
818 #endif
819 #ifdef HW_FILL_ACCEL
820 caps |= SVGA_CAP_RECT_FILL;
821 #endif
822 #ifdef HW_MOUSE_ACCEL
823 if (dpy_cursor_define_supported(s->vga.con)) {
824 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
825 SVGA_CAP_CURSOR_BYPASS;
826 }
827 #endif
828 ret = caps;
829 break;
830
831 case SVGA_REG_MEM_START: {
832 struct pci_vmsvga_state_s *pci_vmsvga
833 = container_of(s, struct pci_vmsvga_state_s, chip);
834 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
835 break;
836 }
837
838 case SVGA_REG_MEM_SIZE:
839 ret = s->fifo_size;
840 break;
841
842 case SVGA_REG_CONFIG_DONE:
843 ret = s->config;
844 break;
845
846 case SVGA_REG_SYNC:
847 case SVGA_REG_BUSY:
848 ret = s->syncing;
849 break;
850
851 case SVGA_REG_GUEST_ID:
852 ret = s->guest;
853 break;
854
855 case SVGA_REG_CURSOR_ID:
856 ret = s->cursor.id;
857 break;
858
859 case SVGA_REG_CURSOR_X:
860 ret = s->cursor.x;
861 break;
862
863 case SVGA_REG_CURSOR_Y:
864 ret = s->cursor.x;
865 break;
866
867 case SVGA_REG_CURSOR_ON:
868 ret = s->cursor.on;
869 break;
870
871 case SVGA_REG_SCRATCH_SIZE:
872 ret = s->scratch_size;
873 break;
874
875 case SVGA_REG_MEM_REGS:
876 case SVGA_REG_NUM_DISPLAYS:
877 case SVGA_REG_PITCHLOCK:
878 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
879 ret = 0;
880 break;
881
882 default:
883 if (s->index >= SVGA_SCRATCH_BASE &&
884 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
885 ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
886 break;
887 }
888 printf("%s: Bad register %02x\n", __func__, s->index);
889 ret = 0;
890 break;
891 }
892
893 if (s->index >= SVGA_SCRATCH_BASE) {
894 trace_vmware_scratch_read(s->index, ret);
895 } else if (s->index >= SVGA_PALETTE_BASE) {
896 trace_vmware_palette_read(s->index, ret);
897 } else {
898 trace_vmware_value_read(s->index, ret);
899 }
900 return ret;
901 }
902
903 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
904 {
905 struct vmsvga_state_s *s = opaque;
906
907 if (s->index >= SVGA_SCRATCH_BASE) {
908 trace_vmware_scratch_write(s->index, value);
909 } else if (s->index >= SVGA_PALETTE_BASE) {
910 trace_vmware_palette_write(s->index, value);
911 } else {
912 trace_vmware_value_write(s->index, value);
913 }
914 switch (s->index) {
915 case SVGA_REG_ID:
916 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
917 s->svgaid = value;
918 }
919 break;
920
921 case SVGA_REG_ENABLE:
922 s->enable = !!value;
923 s->invalidated = 1;
924 s->vga.hw_ops->invalidate(&s->vga);
925 if (s->enable && s->config) {
926 vga_dirty_log_stop(&s->vga);
927 } else {
928 vga_dirty_log_start(&s->vga);
929 }
930 break;
931
932 case SVGA_REG_WIDTH:
933 if (value <= SVGA_MAX_WIDTH) {
934 s->new_width = value;
935 s->invalidated = 1;
936 } else {
937 printf("%s: Bad width: %i\n", __func__, value);
938 }
939 break;
940
941 case SVGA_REG_HEIGHT:
942 if (value <= SVGA_MAX_HEIGHT) {
943 s->new_height = value;
944 s->invalidated = 1;
945 } else {
946 printf("%s: Bad height: %i\n", __func__, value);
947 }
948 break;
949
950 case SVGA_REG_BITS_PER_PIXEL:
951 if (value != 32) {
952 printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
953 s->config = 0;
954 s->invalidated = 1;
955 }
956 break;
957
958 case SVGA_REG_CONFIG_DONE:
959 if (value) {
960 s->fifo = (uint32_t *) s->fifo_ptr;
961 /* Check range and alignment. */
962 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
963 break;
964 }
965 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
966 break;
967 }
968 if (CMD(max) > SVGA_FIFO_SIZE) {
969 break;
970 }
971 if (CMD(max) < CMD(min) + 10 * 1024) {
972 break;
973 }
974 vga_dirty_log_stop(&s->vga);
975 }
976 s->config = !!value;
977 break;
978
979 case SVGA_REG_SYNC:
980 s->syncing = 1;
981 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
982 break;
983
984 case SVGA_REG_GUEST_ID:
985 s->guest = value;
986 #ifdef VERBOSE
987 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
988 ARRAY_SIZE(vmsvga_guest_id)) {
989 printf("%s: guest runs %s.\n", __func__,
990 vmsvga_guest_id[value - GUEST_OS_BASE]);
991 }
992 #endif
993 break;
994
995 case SVGA_REG_CURSOR_ID:
996 s->cursor.id = value;
997 break;
998
999 case SVGA_REG_CURSOR_X:
1000 s->cursor.x = value;
1001 break;
1002
1003 case SVGA_REG_CURSOR_Y:
1004 s->cursor.y = value;
1005 break;
1006
1007 case SVGA_REG_CURSOR_ON:
1008 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
1009 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
1010 #ifdef HW_MOUSE_ACCEL
1011 if (value <= SVGA_CURSOR_ON_SHOW) {
1012 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
1013 }
1014 #endif
1015 break;
1016
1017 case SVGA_REG_DEPTH:
1018 case SVGA_REG_MEM_REGS:
1019 case SVGA_REG_NUM_DISPLAYS:
1020 case SVGA_REG_PITCHLOCK:
1021 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
1022 break;
1023
1024 default:
1025 if (s->index >= SVGA_SCRATCH_BASE &&
1026 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
1027 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
1028 break;
1029 }
1030 printf("%s: Bad register %02x\n", __func__, s->index);
1031 }
1032 }
1033
1034 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
1035 {
1036 printf("%s: what are we supposed to return?\n", __func__);
1037 return 0xcafe;
1038 }
1039
1040 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
1041 {
1042 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
1043 }
1044
1045 static inline void vmsvga_check_size(struct vmsvga_state_s *s)
1046 {
1047 DisplaySurface *surface = qemu_console_surface(s->vga.con);
1048
1049 if (s->new_width != surface_width(surface) ||
1050 s->new_height != surface_height(surface) ||
1051 s->new_depth != surface_bits_per_pixel(surface)) {
1052 int stride = (s->new_depth * s->new_width) / 8;
1053 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
1054 surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
1055 s->new_depth, stride,
1056 s->vga.vram_ptr, false);
1057 dpy_gfx_replace_surface(s->vga.con, surface);
1058 s->invalidated = 1;
1059 }
1060 }
1061
1062 static void vmsvga_update_display(void *opaque)
1063 {
1064 struct vmsvga_state_s *s = opaque;
1065 DisplaySurface *surface;
1066 bool dirty = false;
1067
1068 if (!s->enable) {
1069 s->vga.hw_ops->gfx_update(&s->vga);
1070 return;
1071 }
1072
1073 vmsvga_check_size(s);
1074 surface = qemu_console_surface(s->vga.con);
1075
1076 vmsvga_fifo_run(s);
1077 vmsvga_update_rect_flush(s);
1078
1079 /*
1080 * Is it more efficient to look at vram VGA-dirty bits or wait
1081 * for the driver to issue SVGA_CMD_UPDATE?
1082 */
1083 if (memory_region_is_logging(&s->vga.vram)) {
1084 vga_sync_dirty_bitmap(&s->vga);
1085 dirty = memory_region_get_dirty(&s->vga.vram, 0,
1086 surface_stride(surface) * surface_height(surface),
1087 DIRTY_MEMORY_VGA);
1088 }
1089 if (s->invalidated || dirty) {
1090 s->invalidated = 0;
1091 dpy_gfx_update(s->vga.con, 0, 0,
1092 surface_width(surface), surface_height(surface));
1093 }
1094 if (dirty) {
1095 memory_region_reset_dirty(&s->vga.vram, 0,
1096 surface_stride(surface) * surface_height(surface),
1097 DIRTY_MEMORY_VGA);
1098 }
1099 }
1100
1101 static void vmsvga_reset(DeviceState *dev)
1102 {
1103 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
1104 struct vmsvga_state_s *s = &pci->chip;
1105
1106 s->index = 0;
1107 s->enable = 0;
1108 s->config = 0;
1109 s->svgaid = SVGA_ID;
1110 s->cursor.on = 0;
1111 s->redraw_fifo_first = 0;
1112 s->redraw_fifo_last = 0;
1113 s->syncing = 0;
1114
1115 vga_dirty_log_start(&s->vga);
1116 }
1117
1118 static void vmsvga_invalidate_display(void *opaque)
1119 {
1120 struct vmsvga_state_s *s = opaque;
1121 if (!s->enable) {
1122 s->vga.hw_ops->invalidate(&s->vga);
1123 return;
1124 }
1125
1126 s->invalidated = 1;
1127 }
1128
1129 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1130 {
1131 struct vmsvga_state_s *s = opaque;
1132
1133 if (s->vga.hw_ops->text_update) {
1134 s->vga.hw_ops->text_update(&s->vga, chardata);
1135 }
1136 }
1137
1138 static int vmsvga_post_load(void *opaque, int version_id)
1139 {
1140 struct vmsvga_state_s *s = opaque;
1141
1142 s->invalidated = 1;
1143 if (s->config) {
1144 s->fifo = (uint32_t *) s->fifo_ptr;
1145 }
1146 return 0;
1147 }
1148
1149 static const VMStateDescription vmstate_vmware_vga_internal = {
1150 .name = "vmware_vga_internal",
1151 .version_id = 0,
1152 .minimum_version_id = 0,
1153 .minimum_version_id_old = 0,
1154 .post_load = vmsvga_post_load,
1155 .fields = (VMStateField[]) {
1156 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s),
1157 VMSTATE_INT32(enable, struct vmsvga_state_s),
1158 VMSTATE_INT32(config, struct vmsvga_state_s),
1159 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1160 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1161 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1162 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1163 VMSTATE_INT32(index, struct vmsvga_state_s),
1164 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1165 scratch_size, 0, vmstate_info_uint32, uint32_t),
1166 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1167 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1168 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1169 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1170 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1171 VMSTATE_UNUSED(4), /* was fb_size */
1172 VMSTATE_END_OF_LIST()
1173 }
1174 };
1175
1176 static const VMStateDescription vmstate_vmware_vga = {
1177 .name = "vmware_vga",
1178 .version_id = 0,
1179 .minimum_version_id = 0,
1180 .minimum_version_id_old = 0,
1181 .fields = (VMStateField[]) {
1182 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
1183 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1184 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1185 VMSTATE_END_OF_LIST()
1186 }
1187 };
1188
1189 static const GraphicHwOps vmsvga_ops = {
1190 .invalidate = vmsvga_invalidate_display,
1191 .gfx_update = vmsvga_update_display,
1192 .text_update = vmsvga_text_update,
1193 };
1194
1195 static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
1196 MemoryRegion *address_space, MemoryRegion *io)
1197 {
1198 s->scratch_size = SVGA_SCRATCH_SIZE;
1199 s->scratch = g_malloc(s->scratch_size * 4);
1200
1201 s->vga.con = graphic_console_init(dev, &vmsvga_ops, s);
1202
1203 s->fifo_size = SVGA_FIFO_SIZE;
1204 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size);
1205 vmstate_register_ram_global(&s->fifo_ram);
1206 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1207
1208 vga_common_init(&s->vga, OBJECT(dev));
1209 vga_init(&s->vga, OBJECT(dev), address_space, io, true);
1210 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1211 s->new_depth = 32;
1212 }
1213
1214 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
1215 {
1216 struct vmsvga_state_s *s = opaque;
1217
1218 switch (addr) {
1219 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1220 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1221 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1222 default: return -1u;
1223 }
1224 }
1225
1226 static void vmsvga_io_write(void *opaque, hwaddr addr,
1227 uint64_t data, unsigned size)
1228 {
1229 struct vmsvga_state_s *s = opaque;
1230
1231 switch (addr) {
1232 case SVGA_IO_MUL * SVGA_INDEX_PORT:
1233 vmsvga_index_write(s, addr, data);
1234 break;
1235 case SVGA_IO_MUL * SVGA_VALUE_PORT:
1236 vmsvga_value_write(s, addr, data);
1237 break;
1238 case SVGA_IO_MUL * SVGA_BIOS_PORT:
1239 vmsvga_bios_write(s, addr, data);
1240 break;
1241 }
1242 }
1243
1244 static const MemoryRegionOps vmsvga_io_ops = {
1245 .read = vmsvga_io_read,
1246 .write = vmsvga_io_write,
1247 .endianness = DEVICE_LITTLE_ENDIAN,
1248 .valid = {
1249 .min_access_size = 4,
1250 .max_access_size = 4,
1251 .unaligned = true,
1252 },
1253 .impl = {
1254 .unaligned = true,
1255 },
1256 };
1257
1258 static int pci_vmsvga_initfn(PCIDevice *dev)
1259 {
1260 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
1261
1262 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
1263 dev->config[PCI_LATENCY_TIMER] = 0x40;
1264 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
1265
1266 memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
1267 "vmsvga-io", 0x10);
1268 memory_region_set_flush_coalesced(&s->io_bar);
1269 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1270
1271 vmsvga_init(DEVICE(dev), &s->chip,
1272 pci_address_space(dev), pci_address_space_io(dev));
1273
1274 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1275 &s->chip.vga.vram);
1276 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1277 &s->chip.fifo_ram);
1278
1279 if (!dev->rom_bar) {
1280 /* compatibility with pc-0.13 and older */
1281 vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
1282 }
1283
1284 return 0;
1285 }
1286
1287 static Property vga_vmware_properties[] = {
1288 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1289 chip.vga.vram_size_mb, 16),
1290 DEFINE_PROP_END_OF_LIST(),
1291 };
1292
1293 static void vmsvga_class_init(ObjectClass *klass, void *data)
1294 {
1295 DeviceClass *dc = DEVICE_CLASS(klass);
1296 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1297
1298 k->no_hotplug = 1;
1299 k->init = pci_vmsvga_initfn;
1300 k->romfile = "vgabios-vmware.bin";
1301 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1302 k->device_id = SVGA_PCI_DEVICE_ID;
1303 k->class_id = PCI_CLASS_DISPLAY_VGA;
1304 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1305 k->subsystem_id = SVGA_PCI_DEVICE_ID;
1306 dc->reset = vmsvga_reset;
1307 dc->vmsd = &vmstate_vmware_vga;
1308 dc->props = vga_vmware_properties;
1309 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
1310 }
1311
1312 static const TypeInfo vmsvga_info = {
1313 .name = TYPE_VMWARE_SVGA,
1314 .parent = TYPE_PCI_DEVICE,
1315 .instance_size = sizeof(struct pci_vmsvga_state_s),
1316 .class_init = vmsvga_class_init,
1317 };
1318
1319 static void vmsvga_register_types(void)
1320 {
1321 type_register_static(&vmsvga_info);
1322 }
1323
1324 type_init(vmsvga_register_types)
QEmu