2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-common.h"
26 #include "ui/console.h"
27 #include "ui/pixel_ops.h"
28 #include "hw/sysbus.h"
32 #define TCX_DAC_NREGS 16
33 #define TCX_THC_NREGS_8 0x081c
34 #define TCX_THC_NREGS_24 0x1000
35 #define TCX_TEC_NREGS 0x1000
37 #define TYPE_TCX "SUNW,tcx"
38 #define TCX(obj) OBJECT_CHECK(TCXState, (obj), TYPE_TCX)
40 typedef struct TCXState
{
41 SysBusDevice parent_obj
;
45 uint32_t *vram24
, *cplane
;
46 MemoryRegion vram_mem
;
47 MemoryRegion vram_8bit
;
48 MemoryRegion vram_24bit
;
49 MemoryRegion vram_cplane
;
54 ram_addr_t vram24_offset
, cplane_offset
;
56 uint32_t palette
[256];
57 uint8_t r
[256], g
[256], b
[256];
58 uint16_t width
, height
, depth
;
59 uint8_t dac_index
, dac_state
;
62 static void tcx_set_dirty(TCXState
*s
)
64 memory_region_set_dirty(&s
->vram_mem
, 0, MAXX
* MAXY
);
67 static void tcx24_set_dirty(TCXState
*s
)
69 memory_region_set_dirty(&s
->vram_mem
, s
->vram24_offset
, MAXX
* MAXY
* 4);
70 memory_region_set_dirty(&s
->vram_mem
, s
->cplane_offset
, MAXX
* MAXY
* 4);
73 static void update_palette_entries(TCXState
*s
, int start
, int end
)
75 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
78 for (i
= start
; i
< end
; i
++) {
79 switch (surface_bits_per_pixel(surface
)) {
82 s
->palette
[i
] = rgb_to_pixel8(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
85 s
->palette
[i
] = rgb_to_pixel15(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
88 s
->palette
[i
] = rgb_to_pixel16(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
91 if (is_surface_bgr(surface
)) {
92 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
94 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
106 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
107 const uint8_t *s
, int width
)
111 uint32_t *p
= (uint32_t *)d
;
113 for(x
= 0; x
< width
; x
++) {
115 *p
++ = s1
->palette
[val
];
119 static void tcx_draw_line16(TCXState
*s1
, uint8_t *d
,
120 const uint8_t *s
, int width
)
124 uint16_t *p
= (uint16_t *)d
;
126 for(x
= 0; x
< width
; x
++) {
128 *p
++ = s1
->palette
[val
];
132 static void tcx_draw_line8(TCXState
*s1
, uint8_t *d
,
133 const uint8_t *s
, int width
)
138 for(x
= 0; x
< width
; x
++) {
140 *d
++ = s1
->palette
[val
];
145 XXX Could be much more optimal:
146 * detect if line/page/whole screen is in 24 bit mode
147 * if destination is also BGR, use memcpy
149 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
150 const uint8_t *s
, int width
,
151 const uint32_t *cplane
,
154 DisplaySurface
*surface
= qemu_console_surface(s1
->con
);
157 uint32_t *p
= (uint32_t *)d
;
160 bgr
= is_surface_bgr(surface
);
161 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
162 if ((be32_to_cpu(*cplane
++) & 0xff000000) == 0x03000000) {
163 // 24-bit direct, BGR order
170 dval
= rgb_to_pixel32bgr(r
, g
, b
);
172 dval
= rgb_to_pixel32(r
, g
, b
);
175 dval
= s1
->palette
[val
];
181 static inline int check_dirty(TCXState
*s
, ram_addr_t page
, ram_addr_t page24
,
186 ret
= memory_region_get_dirty(&s
->vram_mem
, page
, TARGET_PAGE_SIZE
,
188 ret
|= memory_region_get_dirty(&s
->vram_mem
, page24
, TARGET_PAGE_SIZE
* 4,
190 ret
|= memory_region_get_dirty(&s
->vram_mem
, cpage
, TARGET_PAGE_SIZE
* 4,
195 static inline void reset_dirty(TCXState
*ts
, ram_addr_t page_min
,
196 ram_addr_t page_max
, ram_addr_t page24
,
199 memory_region_reset_dirty(&ts
->vram_mem
,
201 (page_max
- page_min
) + TARGET_PAGE_SIZE
,
203 memory_region_reset_dirty(&ts
->vram_mem
,
204 page24
+ page_min
* 4,
205 (page_max
- page_min
) * 4 + TARGET_PAGE_SIZE
,
207 memory_region_reset_dirty(&ts
->vram_mem
,
208 cpage
+ page_min
* 4,
209 (page_max
- page_min
) * 4 + TARGET_PAGE_SIZE
,
213 /* Fixed line length 1024 allows us to do nice tricks not possible on
215 static void tcx_update_display(void *opaque
)
217 TCXState
*ts
= opaque
;
218 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
219 ram_addr_t page
, page_min
, page_max
;
220 int y
, y_start
, dd
, ds
;
222 void (*f
)(TCXState
*s1
, uint8_t *dst
, const uint8_t *src
, int width
);
224 if (surface_bits_per_pixel(surface
) == 0) {
232 d
= surface_data(surface
);
234 dd
= surface_stride(surface
);
237 switch (surface_bits_per_pixel(surface
)) {
253 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
) {
254 if (memory_region_get_dirty(&ts
->vram_mem
, page
, TARGET_PAGE_SIZE
,
262 f(ts
, d
, s
, ts
->width
);
265 f(ts
, d
, s
, ts
->width
);
268 f(ts
, d
, s
, ts
->width
);
271 f(ts
, d
, s
, ts
->width
);
276 /* flush to display */
277 dpy_gfx_update(ts
->con
, 0, y_start
,
278 ts
->width
, y
- y_start
);
286 /* flush to display */
287 dpy_gfx_update(ts
->con
, 0, y_start
,
288 ts
->width
, y
- y_start
);
290 /* reset modified pages */
291 if (page_max
>= page_min
) {
292 memory_region_reset_dirty(&ts
->vram_mem
,
294 (page_max
- page_min
) + TARGET_PAGE_SIZE
,
299 static void tcx24_update_display(void *opaque
)
301 TCXState
*ts
= opaque
;
302 DisplaySurface
*surface
= qemu_console_surface(ts
->con
);
303 ram_addr_t page
, page_min
, page_max
, cpage
, page24
;
304 int y
, y_start
, dd
, ds
;
306 uint32_t *cptr
, *s24
;
308 if (surface_bits_per_pixel(surface
) != 32) {
313 page24
= ts
->vram24_offset
;
314 cpage
= ts
->cplane_offset
;
318 d
= surface_data(surface
);
322 dd
= surface_stride(surface
);
325 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
,
326 page24
+= TARGET_PAGE_SIZE
, cpage
+= TARGET_PAGE_SIZE
) {
327 if (check_dirty(ts
, page
, page24
, cpage
)) {
334 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
339 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
344 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
349 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
356 /* flush to display */
357 dpy_gfx_update(ts
->con
, 0, y_start
,
358 ts
->width
, y
- y_start
);
368 /* flush to display */
369 dpy_gfx_update(ts
->con
, 0, y_start
,
370 ts
->width
, y
- y_start
);
372 /* reset modified pages */
373 if (page_max
>= page_min
) {
374 reset_dirty(ts
, page_min
, page_max
, page24
, cpage
);
378 static void tcx_invalidate_display(void *opaque
)
380 TCXState
*s
= opaque
;
383 qemu_console_resize(s
->con
, s
->width
, s
->height
);
386 static void tcx24_invalidate_display(void *opaque
)
388 TCXState
*s
= opaque
;
392 qemu_console_resize(s
->con
, s
->width
, s
->height
);
395 static int vmstate_tcx_post_load(void *opaque
, int version_id
)
397 TCXState
*s
= opaque
;
399 update_palette_entries(s
, 0, 256);
400 if (s
->depth
== 24) {
409 static const VMStateDescription vmstate_tcx
= {
412 .minimum_version_id
= 4,
413 .minimum_version_id_old
= 4,
414 .post_load
= vmstate_tcx_post_load
,
415 .fields
= (VMStateField
[]) {
416 VMSTATE_UINT16(height
, TCXState
),
417 VMSTATE_UINT16(width
, TCXState
),
418 VMSTATE_UINT16(depth
, TCXState
),
419 VMSTATE_BUFFER(r
, TCXState
),
420 VMSTATE_BUFFER(g
, TCXState
),
421 VMSTATE_BUFFER(b
, TCXState
),
422 VMSTATE_UINT8(dac_index
, TCXState
),
423 VMSTATE_UINT8(dac_state
, TCXState
),
424 VMSTATE_END_OF_LIST()
428 static void tcx_reset(DeviceState
*d
)
430 TCXState
*s
= TCX(d
);
432 /* Initialize palette */
433 memset(s
->r
, 0, 256);
434 memset(s
->g
, 0, 256);
435 memset(s
->b
, 0, 256);
436 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
437 update_palette_entries(s
, 0, 256);
438 memset(s
->vram
, 0, MAXX
*MAXY
);
439 memory_region_reset_dirty(&s
->vram_mem
, 0, MAXX
* MAXY
* (1 + 4 + 4),
445 static uint64_t tcx_dac_readl(void *opaque
, hwaddr addr
,
451 static void tcx_dac_writel(void *opaque
, hwaddr addr
, uint64_t val
,
454 TCXState
*s
= opaque
;
458 s
->dac_index
= val
>> 24;
462 switch (s
->dac_state
) {
464 s
->r
[s
->dac_index
] = val
>> 24;
465 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
469 s
->g
[s
->dac_index
] = val
>> 24;
470 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
474 s
->b
[s
->dac_index
] = val
>> 24;
475 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
476 s
->dac_index
= (s
->dac_index
+ 1) & 255; // Index autoincrement
487 static const MemoryRegionOps tcx_dac_ops
= {
488 .read
= tcx_dac_readl
,
489 .write
= tcx_dac_writel
,
490 .endianness
= DEVICE_NATIVE_ENDIAN
,
492 .min_access_size
= 4,
493 .max_access_size
= 4,
497 static uint64_t dummy_readl(void *opaque
, hwaddr addr
,
503 static void dummy_writel(void *opaque
, hwaddr addr
,
504 uint64_t val
, unsigned size
)
508 static const MemoryRegionOps dummy_ops
= {
510 .write
= dummy_writel
,
511 .endianness
= DEVICE_NATIVE_ENDIAN
,
513 .min_access_size
= 4,
514 .max_access_size
= 4,
518 static const GraphicHwOps tcx_ops
= {
519 .invalidate
= tcx_invalidate_display
,
520 .gfx_update
= tcx_update_display
,
523 static const GraphicHwOps tcx24_ops
= {
524 .invalidate
= tcx24_invalidate_display
,
525 .gfx_update
= tcx24_update_display
,
528 static int tcx_init1(SysBusDevice
*dev
)
530 TCXState
*s
= TCX(dev
);
531 ram_addr_t vram_offset
= 0;
535 memory_region_init_ram(&s
->vram_mem
, OBJECT(s
), "tcx.vram",
536 s
->vram_size
* (1 + 4 + 4));
537 vmstate_register_ram_global(&s
->vram_mem
);
538 vram_base
= memory_region_get_ram_ptr(&s
->vram_mem
);
543 memory_region_init_alias(&s
->vram_8bit
, OBJECT(s
), "tcx.vram.8bit",
544 &s
->vram_mem
, vram_offset
, size
);
545 sysbus_init_mmio(dev
, &s
->vram_8bit
);
550 memory_region_init_io(&s
->dac
, OBJECT(s
), &tcx_dac_ops
, s
,
551 "tcx.dac", TCX_DAC_NREGS
);
552 sysbus_init_mmio(dev
, &s
->dac
);
555 memory_region_init_io(&s
->tec
, OBJECT(s
), &dummy_ops
, s
,
556 "tcx.tec", TCX_TEC_NREGS
);
557 sysbus_init_mmio(dev
, &s
->tec
);
558 /* THC: NetBSD writes here even with 8-bit display: dummy */
559 memory_region_init_io(&s
->thc24
, OBJECT(s
), &dummy_ops
, s
, "tcx.thc24",
561 sysbus_init_mmio(dev
, &s
->thc24
);
563 if (s
->depth
== 24) {
565 size
= s
->vram_size
* 4;
566 s
->vram24
= (uint32_t *)vram_base
;
567 s
->vram24_offset
= vram_offset
;
568 memory_region_init_alias(&s
->vram_24bit
, OBJECT(s
), "tcx.vram.24bit",
569 &s
->vram_mem
, vram_offset
, size
);
570 sysbus_init_mmio(dev
, &s
->vram_24bit
);
575 size
= s
->vram_size
* 4;
576 s
->cplane
= (uint32_t *)vram_base
;
577 s
->cplane_offset
= vram_offset
;
578 memory_region_init_alias(&s
->vram_cplane
, OBJECT(s
), "tcx.vram.cplane",
579 &s
->vram_mem
, vram_offset
, size
);
580 sysbus_init_mmio(dev
, &s
->vram_cplane
);
582 s
->con
= graphic_console_init(DEVICE(dev
), &tcx24_ops
, s
);
584 /* THC 8 bit (dummy) */
585 memory_region_init_io(&s
->thc8
, OBJECT(s
), &dummy_ops
, s
, "tcx.thc8",
587 sysbus_init_mmio(dev
, &s
->thc8
);
589 s
->con
= graphic_console_init(DEVICE(dev
), &tcx_ops
, s
);
592 qemu_console_resize(s
->con
, s
->width
, s
->height
);
596 static Property tcx_properties
[] = {
597 DEFINE_PROP_HEX32("vram_size", TCXState
, vram_size
, -1),
598 DEFINE_PROP_UINT16("width", TCXState
, width
, -1),
599 DEFINE_PROP_UINT16("height", TCXState
, height
, -1),
600 DEFINE_PROP_UINT16("depth", TCXState
, depth
, -1),
601 DEFINE_PROP_END_OF_LIST(),
604 static void tcx_class_init(ObjectClass
*klass
, void *data
)
606 DeviceClass
*dc
= DEVICE_CLASS(klass
);
607 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
610 dc
->reset
= tcx_reset
;
611 dc
->vmsd
= &vmstate_tcx
;
612 dc
->props
= tcx_properties
;
615 static const TypeInfo tcx_info
= {
617 .parent
= TYPE_SYS_BUS_DEVICE
,
618 .instance_size
= sizeof(TCXState
),
619 .class_init
= tcx_class_init
,
622 static void tcx_register_types(void)
624 type_register_static(&tcx_info
);
627 type_init(tcx_register_types
)