hw/riscv/sifive_e.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom E SDK
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * Provides a board compatible with the SiFive Freedom E SDK:
   7  *
   8  * 0) UART
   9  * 1) CLINT (Core Level Interruptor)
  10  * 2) PLIC (Platform Level Interrupt Controller)
  11  * 3) PRCI (Power, Reset, Clock, Interrupt)
  12  * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
  13  * 5) Flash memory emulated as RAM
  14  *
  15  * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
  16  * The OTP ROM and Flash boot code will be emulated in a future version.
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms and conditions of the GNU General Public License,
  20  * version 2 or later, as published by the Free Software Foundation.
  21  *
  22  * This program is distributed in the hope it will be useful, but WITHOUT
  23  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  24  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  25  * more details.
  26  *
  27  * You should have received a copy of the GNU General Public License along with
  28  * this program.  If not, see <http://www.gnu.org/licenses/>.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/cutils.h"
  33 #include "qemu/error-report.h"
  34 #include "qapi/error.h"
  35 #include "hw/boards.h"
  36 #include "hw/loader.h"
  37 #include "hw/sysbus.h"
  38 #include "hw/char/serial.h"
  39 #include "hw/misc/unimp.h"
  40 #include "target/riscv/cpu.h"
  41 #include "hw/riscv/riscv_hart.h"
  42 #include "hw/riscv/sifive_e.h"
  43 #include "hw/riscv/boot.h"
  44 #include "hw/char/sifive_uart.h"
  45 #include "hw/intc/riscv_aclint.h"
  46 #include "hw/intc/sifive_plic.h"
  47 #include "hw/misc/sifive_e_prci.h"
  48 #include "chardev/char.h"
  49 #include "sysemu/sysemu.h"
  50
  51 static const MemMapEntry sifive_e_memmap[] = {
  52     [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
  53     [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
  54     [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
  55     [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
  56     [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
  57     [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
  58     [SIFIVE_E_DEV_PRCI] =     { 0x10008000,     0x8000 },
  59     [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000,     0x1000 },
  60     [SIFIVE_E_DEV_GPIO0] =    { 0x10012000,     0x1000 },
  61     [SIFIVE_E_DEV_UART0] =    { 0x10013000,     0x1000 },
  62     [SIFIVE_E_DEV_QSPI0] =    { 0x10014000,     0x1000 },
  63     [SIFIVE_E_DEV_PWM0] =     { 0x10015000,     0x1000 },
  64     [SIFIVE_E_DEV_UART1] =    { 0x10023000,     0x1000 },
  65     [SIFIVE_E_DEV_QSPI1] =    { 0x10024000,     0x1000 },
  66     [SIFIVE_E_DEV_PWM1] =     { 0x10025000,     0x1000 },
  67     [SIFIVE_E_DEV_QSPI2] =    { 0x10034000,     0x1000 },
  68     [SIFIVE_E_DEV_PWM2] =     { 0x10035000,     0x1000 },
  69     [SIFIVE_E_DEV_XIP] =      { 0x20000000, 0x20000000 },
  70     [SIFIVE_E_DEV_DTIM] =     { 0x80000000,     0x4000 }
  71 };
  72
  73 static void sifive_e_machine_init(MachineState *machine)
  74 {
  75     MachineClass *mc = MACHINE_GET_CLASS(machine);
  76     const MemMapEntry *memmap = sifive_e_memmap;
  77
  78     SiFiveEState *s = RISCV_E_MACHINE(machine);
  79     MemoryRegion *sys_mem = get_system_memory();
  80     int i;
  81
  82     if (machine->ram_size != mc->default_ram_size) {
  83         char *sz = size_to_str(mc->default_ram_size);
  84         error_report("Invalid RAM size, should be %s", sz);
  85         g_free(sz);
  86         exit(EXIT_FAILURE);
  87     }
  88
  89     /* Initialize SoC */
  90     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
  91     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
  92
  93     /* Data Tightly Integrated Memory */
  94     memory_region_add_subregion(sys_mem,
  95         memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
  96
  97     /* Mask ROM reset vector */
  98     uint32_t reset_vec[4];
  99
 100     if (s->revb) {
 101         reset_vec[1] = 0x200102b7;  /* 0x1004: lui     t0,0x20010 */
 102     } else {
 103         reset_vec[1] = 0x204002b7;  /* 0x1004: lui     t0,0x20400 */
 104     }
 105     reset_vec[2] = 0x00028067;      /* 0x1008: jr      t0 */
 106
 107     reset_vec[0] = reset_vec[3] = 0;
 108
 109     /* copy in the reset vector in little_endian byte order */
 110     for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
 111         reset_vec[i] = cpu_to_le32(reset_vec[i]);
 112     }
 113     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
 114                           memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 115
 116     if (machine->kernel_filename) {
 117         riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL);
 118     }
 119 }
 120
 121 static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
 122 {
 123     SiFiveEState *s = RISCV_E_MACHINE(obj);
 124
 125     return s->revb;
 126 }
 127
 128 static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
 129 {
 130     SiFiveEState *s = RISCV_E_MACHINE(obj);
 131
 132     s->revb = value;
 133 }
 134
 135 static void sifive_e_machine_instance_init(Object *obj)
 136 {
 137     SiFiveEState *s = RISCV_E_MACHINE(obj);
 138
 139     s->revb = false;
 140 }
 141
 142 static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
 143 {
 144     MachineClass *mc = MACHINE_CLASS(oc);
 145
 146     mc->desc = "RISC-V Board compatible with SiFive E SDK";
 147     mc->init = sifive_e_machine_init;
 148     mc->max_cpus = 1;
 149     mc->default_cpu_type = SIFIVE_E_CPU;
 150     mc->default_ram_id = "riscv.sifive.e.ram";
 151     mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
 152
 153     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
 154                                    sifive_e_machine_set_revb);
 155     object_class_property_set_description(oc, "revb",
 156                                           "Set on to tell QEMU that it should model "
 157                                           "the revB HiFive1 board");
 158 }
 159
 160 static const TypeInfo sifive_e_machine_typeinfo = {
 161     .name       = MACHINE_TYPE_NAME("sifive_e"),
 162     .parent     = TYPE_MACHINE,
 163     .class_init = sifive_e_machine_class_init,
 164     .instance_init = sifive_e_machine_instance_init,
 165     .instance_size = sizeof(SiFiveEState),
 166 };
 167
 168 static void sifive_e_machine_init_register_types(void)
 169 {
 170     type_register_static(&sifive_e_machine_typeinfo);
 171 }
 172
 173 type_init(sifive_e_machine_init_register_types)
 174
 175 static void sifive_e_soc_init(Object *obj)
 176 {
 177     MachineState *ms = MACHINE(qdev_get_machine());
 178     SiFiveESoCState *s = RISCV_E_SOC(obj);
 179
 180     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 181     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 182                             &error_abort);
 183     object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
 184     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
 185                             TYPE_SIFIVE_GPIO);
 186 }
 187
 188 static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 189 {
 190     MachineState *ms = MACHINE(qdev_get_machine());
 191     const MemMapEntry *memmap = sifive_e_memmap;
 192     SiFiveESoCState *s = RISCV_E_SOC(dev);
 193     MemoryRegion *sys_mem = get_system_memory();
 194
 195     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 196                             &error_abort);
 197     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 198
 199     /* Mask ROM */
 200     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
 201                            memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
 202     memory_region_add_subregion(sys_mem,
 203         memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
 204
 205     /* MMIO */
 206     s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
 207         (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
 208         SIFIVE_E_PLIC_NUM_SOURCES,
 209         SIFIVE_E_PLIC_NUM_PRIORITIES,
 210         SIFIVE_E_PLIC_PRIORITY_BASE,
 211         SIFIVE_E_PLIC_PENDING_BASE,
 212         SIFIVE_E_PLIC_ENABLE_BASE,
 213         SIFIVE_E_PLIC_ENABLE_STRIDE,
 214         SIFIVE_E_PLIC_CONTEXT_BASE,
 215         SIFIVE_E_PLIC_CONTEXT_STRIDE,
 216         memmap[SIFIVE_E_DEV_PLIC].size);
 217     riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
 218         0, ms->smp.cpus, false);
 219     riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
 220             RISCV_ACLINT_SWI_SIZE,
 221         RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
 222         RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
 223         RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
 224     create_unimplemented_device("riscv.sifive.e.aon",
 225         memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
 226     sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
 227
 228     /* GPIO */
 229
 230     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
 231         return;
 232     }
 233
 234     /* Map GPIO registers */
 235     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
 236
 237     /* Pass all GPIOs to the SOC layer so they are available to the board */
 238     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
 239
 240     /* Connect GPIO interrupts to the PLIC */
 241     for (int i = 0; i < 32; i++) {
 242         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
 243                            qdev_get_gpio_in(DEVICE(s->plic),
 244                                             SIFIVE_E_GPIO0_IRQ0 + i));
 245     }
 246
 247     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
 248         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
 249     create_unimplemented_device("riscv.sifive.e.qspi0",
 250         memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
 251     create_unimplemented_device("riscv.sifive.e.pwm0",
 252         memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
 253     sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
 254         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
 255     create_unimplemented_device("riscv.sifive.e.qspi1",
 256         memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
 257     create_unimplemented_device("riscv.sifive.e.pwm1",
 258         memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
 259     create_unimplemented_device("riscv.sifive.e.qspi2",
 260         memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
 261     create_unimplemented_device("riscv.sifive.e.pwm2",
 262         memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
 263
 264     /* Flash memory */
 265     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
 266                            memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
 267     memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
 268         &s->xip_mem);
 269 }
 270
 271 static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
 272 {
 273     DeviceClass *dc = DEVICE_CLASS(oc);
 274
 275     dc->realize = sifive_e_soc_realize;
 276     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 277     dc->user_creatable = false;
 278 }
 279
 280 static const TypeInfo sifive_e_soc_type_info = {
 281     .name = TYPE_RISCV_E_SOC,
 282     .parent = TYPE_DEVICE,
 283     .instance_size = sizeof(SiFiveESoCState),
 284     .instance_init = sifive_e_soc_init,
 285     .class_init = sifive_e_soc_class_init,
 286 };
 287
 288 static void sifive_e_soc_register_types(void)
 289 {
 290     type_register_static(&sifive_e_soc_type_info);
 291 }
 292
 293 type_init(sifive_e_soc_register_types)