hw/riscv/opentitan.c

   1 /*
   2  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * Provides a board compatible with the OpenTitan FPGA platform:
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2 or later, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/cutils.h"
  23 #include "hw/riscv/opentitan.h"
  24 #include "qapi/error.h"
  25 #include "hw/boards.h"
  26 #include "hw/misc/unimp.h"
  27 #include "hw/riscv/boot.h"
  28 #include "qemu/units.h"
  29 #include "sysemu/sysemu.h"
  30
  31 /*
  32  * This version of the OpenTitan machine currently supports
  33  * OpenTitan RTL version:
  34  * <lowRISC/opentitan@d072ac505f82152678d6e04be95c72b728a347b8>
  35  *
  36  * MMIO mapping as per (specified commit):
  37  * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
  38  */
  39 static const MemMapEntry ibex_memmap[] = {
  40     [IBEX_DEV_ROM] =            {  0x00008000,  0x8000 },
  41     [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
  42     [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
  43     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
  44     [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
  45     [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
  46     [IBEX_DEV_I2C] =            {  0x40080000,  0x1000  },
  47     [IBEX_DEV_PATTGEN] =        {  0x400e0000,  0x1000  },
  48     [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
  49     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
  50     [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
  51     [IBEX_DEV_ALERT_HANDLER] =  {  0x40150000,  0x1000  },
  52     [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
  53     [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
  54     [IBEX_DEV_USBDEV] =         {  0x40320000,  0x1000  },
  55     [IBEX_DEV_PWRMGR] =         {  0x40400000,  0x1000  },
  56     [IBEX_DEV_RSTMGR] =         {  0x40410000,  0x1000  },
  57     [IBEX_DEV_CLKMGR] =         {  0x40420000,  0x1000  },
  58     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
  59     [IBEX_DEV_AON_TIMER] =      {  0x40470000,  0x1000  },
  60     [IBEX_DEV_SENSOR_CTRL] =    {  0x40490000,  0x1000  },
  61     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
  62     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
  63     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
  64     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
  65     [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
  66     [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
  67     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
  68     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
  69     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
  70     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
  71     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
  72     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
  73     [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000 },
  74     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
  75 };
  76
  77 static void opentitan_board_init(MachineState *machine)
  78 {
  79     MachineClass *mc = MACHINE_GET_CLASS(machine);
  80     const MemMapEntry *memmap = ibex_memmap;
  81     OpenTitanState *s = g_new0(OpenTitanState, 1);
  82     MemoryRegion *sys_mem = get_system_memory();
  83
  84     if (machine->ram_size != mc->default_ram_size) {
  85         char *sz = size_to_str(mc->default_ram_size);
  86         error_report("Invalid RAM size, should be %s", sz);
  87         g_free(sz);
  88         exit(EXIT_FAILURE);
  89     }
  90
  91     /* Initialize SoC */
  92     object_initialize_child(OBJECT(machine), "soc", &s->soc,
  93                             TYPE_RISCV_IBEX_SOC);
  94     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
  95
  96     memory_region_add_subregion(sys_mem,
  97         memmap[IBEX_DEV_RAM].base, machine->ram);
  98
  99     if (machine->firmware) {
 100         riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
 101     }
 102
 103     if (machine->kernel_filename) {
 104         riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
 105     }
 106 }
 107
 108 static void opentitan_machine_init(MachineClass *mc)
 109 {
 110     mc->desc = "RISC-V Board compatible with OpenTitan";
 111     mc->init = opentitan_board_init;
 112     mc->max_cpus = 1;
 113     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 114     mc->default_ram_id = "riscv.lowrisc.ibex.ram";
 115     mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
 116 }
 117
 118 DEFINE_MACHINE("opentitan", opentitan_machine_init)
 119
 120 static void lowrisc_ibex_soc_init(Object *obj)
 121 {
 122     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
 123
 124     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 125
 126     object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
 127
 128     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 129
 130     object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
 131
 132     for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
 133         object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
 134                                 TYPE_IBEX_SPI_HOST);
 135     }
 136 }
 137
 138 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 139 {
 140     const MemMapEntry *memmap = ibex_memmap;
 141     DeviceState *dev;
 142     SysBusDevice *busdev;
 143     MachineState *ms = MACHINE(qdev_get_machine());
 144     LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
 145     MemoryRegion *sys_mem = get_system_memory();
 146     int i;
 147
 148     object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
 149                             &error_abort);
 150     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
 151                             &error_abort);
 152     object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
 153                             &error_abort);
 154     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 155
 156     /* Boot ROM */
 157     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
 158                            memmap[IBEX_DEV_ROM].size, &error_fatal);
 159     memory_region_add_subregion(sys_mem,
 160         memmap[IBEX_DEV_ROM].base, &s->rom);
 161
 162     /* Flash memory */
 163     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
 164                            memmap[IBEX_DEV_FLASH].size, &error_fatal);
 165     memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
 166                              "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
 167                              memmap[IBEX_DEV_FLASH_VIRTUAL].size);
 168     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
 169                                 &s->flash_mem);
 170     memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
 171                                 &s->flash_alias);
 172
 173     /* PLIC */
 174     qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
 175     qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
 176     qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
 177     qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
 178     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
 179     qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
 180     qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
 181     qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
 182     qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
 183
 184     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
 185         return;
 186     }
 187     sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 188
 189     for (i = 0; i < ms->smp.cpus; i++) {
 190         CPUState *cpu = qemu_get_cpu(i);
 191
 192         qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
 193                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
 194     }
 195
 196     /* UART */
 197     qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
 198     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
 199         return;
 200     }
 201     sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
 202     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 203                        0, qdev_get_gpio_in(DEVICE(&s->plic),
 204                        IBEX_UART0_TX_WATERMARK_IRQ));
 205     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 206                        1, qdev_get_gpio_in(DEVICE(&s->plic),
 207                        IBEX_UART0_RX_WATERMARK_IRQ));
 208     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 209                        2, qdev_get_gpio_in(DEVICE(&s->plic),
 210                        IBEX_UART0_TX_EMPTY_IRQ));
 211     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
 212                        3, qdev_get_gpio_in(DEVICE(&s->plic),
 213                        IBEX_UART0_RX_OVERFLOW_IRQ));
 214
 215     if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
 216         return;
 217     }
 218     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
 219     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
 220                        0, qdev_get_gpio_in(DEVICE(&s->plic),
 221                        IBEX_TIMER_TIMEREXPIRED0_0));
 222     qdev_connect_gpio_out(DEVICE(&s->timer), 0,
 223                           qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
 224                                            IRQ_M_TIMER));
 225
 226     /* SPI-Hosts */
 227     for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
 228         dev = DEVICE(&(s->spi_host[i]));
 229         if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
 230             return;
 231         }
 232         busdev = SYS_BUS_DEVICE(dev);
 233         sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
 234
 235         switch (i) {
 236         case OPENTITAN_SPI_HOST0:
 237             sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
 238                                 IBEX_SPI_HOST0_ERR_IRQ));
 239             sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
 240                                 IBEX_SPI_HOST0_SPI_EVENT_IRQ));
 241             break;
 242         case OPENTITAN_SPI_HOST1:
 243             sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
 244                                 IBEX_SPI_HOST1_ERR_IRQ));
 245             sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
 246                                 IBEX_SPI_HOST1_SPI_EVENT_IRQ));
 247             break;
 248         }
 249     }
 250
 251     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
 252         memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
 253     create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
 254         memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
 255     create_unimplemented_device("riscv.lowrisc.ibex.i2c",
 256         memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
 257     create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
 258         memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
 259     create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
 260         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
 261     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
 262         memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
 263     create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
 264         memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
 265     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
 266         memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
 267     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
 268         memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
 269     create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
 270         memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
 271     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
 272         memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
 273     create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
 274         memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
 275     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
 276         memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
 277     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
 278         memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
 279     create_unimplemented_device("riscv.lowrisc.ibex.aes",
 280         memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
 281     create_unimplemented_device("riscv.lowrisc.ibex.hmac",
 282         memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
 283     create_unimplemented_device("riscv.lowrisc.ibex.kmac",
 284         memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
 285     create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
 286         memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
 287     create_unimplemented_device("riscv.lowrisc.ibex.csrng",
 288         memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
 289     create_unimplemented_device("riscv.lowrisc.ibex.entropy",
 290         memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
 291     create_unimplemented_device("riscv.lowrisc.ibex.edn0",
 292         memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
 293     create_unimplemented_device("riscv.lowrisc.ibex.edn1",
 294         memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
 295     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
 296         memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
 297     create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
 298         memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
 299     create_unimplemented_device("riscv.lowrisc.ibex.otbn",
 300         memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
 301     create_unimplemented_device("riscv.lowrisc.ibex.peri",
 302         memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
 303 }
 304
 305 static Property lowrisc_ibex_soc_props[] = {
 306     DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
 307     DEFINE_PROP_END_OF_LIST()
 308 };
 309
 310 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
 311 {
 312     DeviceClass *dc = DEVICE_CLASS(oc);
 313
 314     device_class_set_props(dc, lowrisc_ibex_soc_props);
 315     dc->realize = lowrisc_ibex_soc_realize;
 316     /* Reason: Uses serial_hds in realize function, thus can't be used twice */
 317     dc->user_creatable = false;
 318 }
 319
 320 static const TypeInfo lowrisc_ibex_soc_type_info = {
 321     .name = TYPE_RISCV_IBEX_SOC,
 322     .parent = TYPE_DEVICE,
 323     .instance_size = sizeof(LowRISCIbexSoCState),
 324     .instance_init = lowrisc_ibex_soc_init,
 325     .class_init = lowrisc_ibex_soc_class_init,
 326 };
 327
 328 static void lowrisc_ibex_soc_register_types(void)
 329 {
 330     type_register_static(&lowrisc_ibex_soc_type_info);
 331 }
 332
 333 type_init(lowrisc_ibex_soc_register_types)