qemu-img bench: Fix uninitialised writethrough mode
[qemu.git] / tcg / aarch64 / tcg-target.h
blob19a04a6e75e75a60d8d57d5baf045b3e7fc76811
1 /*
2 * Initial TCG Implementation for aarch64
4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
5 * Written by Claudio Fontana
7 * This work is licensed under the terms of the GNU GPL, version 2 or
8 * (at your option) any later version.
10 * See the COPYING file in the top-level directory for details.
13 #ifndef TCG_TARGET_AARCH64
14 #define TCG_TARGET_AARCH64 1
16 #define TCG_TARGET_INSN_UNIT_SIZE 4
17 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
18 #undef TCG_TARGET_STACK_GROWSUP
20 typedef enum {
21 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
22 TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
23 TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
24 TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
25 TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
26 TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
27 TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
28 TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
30 /* X31 is either the stack pointer or zero, depending on context. */
31 TCG_REG_SP = 31,
32 TCG_REG_XZR = 31,
34 /* Aliases. */
35 TCG_REG_FP = TCG_REG_X29,
36 TCG_REG_LR = TCG_REG_X30,
37 TCG_AREG0 = TCG_REG_X19,
38 } TCGReg;
40 #define TCG_TARGET_NB_REGS 32
42 /* used for function call generation */
43 #define TCG_REG_CALL_STACK TCG_REG_SP
44 #define TCG_TARGET_STACK_ALIGN 16
45 #define TCG_TARGET_CALL_ALIGN_ARGS 1
46 #define TCG_TARGET_CALL_STACK_OFFSET 0
48 /* optional instructions */
49 #define TCG_TARGET_HAS_div_i32 1
50 #define TCG_TARGET_HAS_rem_i32 1
51 #define TCG_TARGET_HAS_ext8s_i32 1
52 #define TCG_TARGET_HAS_ext16s_i32 1
53 #define TCG_TARGET_HAS_ext8u_i32 1
54 #define TCG_TARGET_HAS_ext16u_i32 1
55 #define TCG_TARGET_HAS_bswap16_i32 1
56 #define TCG_TARGET_HAS_bswap32_i32 1
57 #define TCG_TARGET_HAS_not_i32 1
58 #define TCG_TARGET_HAS_neg_i32 1
59 #define TCG_TARGET_HAS_rot_i32 1
60 #define TCG_TARGET_HAS_andc_i32 1
61 #define TCG_TARGET_HAS_orc_i32 1
62 #define TCG_TARGET_HAS_eqv_i32 1
63 #define TCG_TARGET_HAS_nand_i32 0
64 #define TCG_TARGET_HAS_nor_i32 0
65 #define TCG_TARGET_HAS_deposit_i32 1
66 #define TCG_TARGET_HAS_movcond_i32 1
67 #define TCG_TARGET_HAS_add2_i32 1
68 #define TCG_TARGET_HAS_sub2_i32 1
69 #define TCG_TARGET_HAS_mulu2_i32 0
70 #define TCG_TARGET_HAS_muls2_i32 0
71 #define TCG_TARGET_HAS_muluh_i32 0
72 #define TCG_TARGET_HAS_mulsh_i32 0
73 #define TCG_TARGET_HAS_extrl_i64_i32 0
74 #define TCG_TARGET_HAS_extrh_i64_i32 0
76 #define TCG_TARGET_HAS_div_i64 1
77 #define TCG_TARGET_HAS_rem_i64 1
78 #define TCG_TARGET_HAS_ext8s_i64 1
79 #define TCG_TARGET_HAS_ext16s_i64 1
80 #define TCG_TARGET_HAS_ext32s_i64 1
81 #define TCG_TARGET_HAS_ext8u_i64 1
82 #define TCG_TARGET_HAS_ext16u_i64 1
83 #define TCG_TARGET_HAS_ext32u_i64 1
84 #define TCG_TARGET_HAS_bswap16_i64 1
85 #define TCG_TARGET_HAS_bswap32_i64 1
86 #define TCG_TARGET_HAS_bswap64_i64 1
87 #define TCG_TARGET_HAS_not_i64 1
88 #define TCG_TARGET_HAS_neg_i64 1
89 #define TCG_TARGET_HAS_rot_i64 1
90 #define TCG_TARGET_HAS_andc_i64 1
91 #define TCG_TARGET_HAS_orc_i64 1
92 #define TCG_TARGET_HAS_eqv_i64 1
93 #define TCG_TARGET_HAS_nand_i64 0
94 #define TCG_TARGET_HAS_nor_i64 0
95 #define TCG_TARGET_HAS_deposit_i64 1
96 #define TCG_TARGET_HAS_movcond_i64 1
97 #define TCG_TARGET_HAS_add2_i64 1
98 #define TCG_TARGET_HAS_sub2_i64 1
99 #define TCG_TARGET_HAS_mulu2_i64 0
100 #define TCG_TARGET_HAS_muls2_i64 0
101 #define TCG_TARGET_HAS_muluh_i64 1
102 #define TCG_TARGET_HAS_mulsh_i64 1
104 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
106 __builtin___clear_cache((char *)start, (char *)stop);
109 #endif /* TCG_TARGET_AARCH64 */