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disable automatic loading of sgabios when -nographic
[qemu.git] / gdbstub.c
bloba25f4044303822dcf5f670a6aae2ad6a55a5fa33
1 /*
2 * gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <stdarg.h>
25 #include <string.h>
26 #include <errno.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "qemu.h"
31 #else
32 #include "monitor.h"
33 #include "qemu-char.h"
34 #include "sysemu.h"
35 #include "gdbstub.h"
36 #endif
37
38 #define MAX_PACKET_LENGTH 4096
39
40 #include "cpu.h"
41 #include "qemu_socket.h"
42 #include "kvm.h"
43
44 #ifndef TARGET_CPU_MEMORY_RW_DEBUG
45 static inline int target_memory_rw_debug(CPUState *env, target_ulong addr,
46 uint8_t *buf, int len, int is_write)
47 {
48 return cpu_memory_rw_debug(env, addr, buf, len, is_write);
49 }
50 #else
51 /* target_memory_rw_debug() defined in cpu.h */
52 #endif
53
54 enum {
55 GDB_SIGNAL_0 = 0,
56 GDB_SIGNAL_INT = 2,
57 GDB_SIGNAL_QUIT = 3,
58 GDB_SIGNAL_TRAP = 5,
59 GDB_SIGNAL_ABRT = 6,
60 GDB_SIGNAL_ALRM = 14,
61 GDB_SIGNAL_IO = 23,
62 GDB_SIGNAL_XCPU = 24,
63 GDB_SIGNAL_UNKNOWN = 143
64 };
65
66 #ifdef CONFIG_USER_ONLY
67
68 /* Map target signal numbers to GDB protocol signal numbers and vice
69 * versa. For user emulation's currently supported systems, we can
70 * assume most signals are defined.
71 */
72
73 static int gdb_signal_table[] = {
74 0,
75 TARGET_SIGHUP,
76 TARGET_SIGINT,
77 TARGET_SIGQUIT,
78 TARGET_SIGILL,
79 TARGET_SIGTRAP,
80 TARGET_SIGABRT,
81 -1, /* SIGEMT */
82 TARGET_SIGFPE,
83 TARGET_SIGKILL,
84 TARGET_SIGBUS,
85 TARGET_SIGSEGV,
86 TARGET_SIGSYS,
87 TARGET_SIGPIPE,
88 TARGET_SIGALRM,
89 TARGET_SIGTERM,
90 TARGET_SIGURG,
91 TARGET_SIGSTOP,
92 TARGET_SIGTSTP,
93 TARGET_SIGCONT,
94 TARGET_SIGCHLD,
95 TARGET_SIGTTIN,
96 TARGET_SIGTTOU,
97 TARGET_SIGIO,
98 TARGET_SIGXCPU,
99 TARGET_SIGXFSZ,
100 TARGET_SIGVTALRM,
101 TARGET_SIGPROF,
102 TARGET_SIGWINCH,
103 -1, /* SIGLOST */
104 TARGET_SIGUSR1,
105 TARGET_SIGUSR2,
106 #ifdef TARGET_SIGPWR
107 TARGET_SIGPWR,
108 #else
109 -1,
110 #endif
111 -1, /* SIGPOLL */
112 -1,
113 -1,
114 -1,
115 -1,
116 -1,
117 -1,
118 -1,
119 -1,
120 -1,
121 -1,
122 -1,
123 #ifdef __SIGRTMIN
124 __SIGRTMIN + 1,
125 __SIGRTMIN + 2,
126 __SIGRTMIN + 3,
127 __SIGRTMIN + 4,
128 __SIGRTMIN + 5,
129 __SIGRTMIN + 6,
130 __SIGRTMIN + 7,
131 __SIGRTMIN + 8,
132 __SIGRTMIN + 9,
133 __SIGRTMIN + 10,
134 __SIGRTMIN + 11,
135 __SIGRTMIN + 12,
136 __SIGRTMIN + 13,
137 __SIGRTMIN + 14,
138 __SIGRTMIN + 15,
139 __SIGRTMIN + 16,
140 __SIGRTMIN + 17,
141 __SIGRTMIN + 18,
142 __SIGRTMIN + 19,
143 __SIGRTMIN + 20,
144 __SIGRTMIN + 21,
145 __SIGRTMIN + 22,
146 __SIGRTMIN + 23,
147 __SIGRTMIN + 24,
148 __SIGRTMIN + 25,
149 __SIGRTMIN + 26,
150 __SIGRTMIN + 27,
151 __SIGRTMIN + 28,
152 __SIGRTMIN + 29,
153 __SIGRTMIN + 30,
154 __SIGRTMIN + 31,
155 -1, /* SIGCANCEL */
156 __SIGRTMIN,
157 __SIGRTMIN + 32,
158 __SIGRTMIN + 33,
159 __SIGRTMIN + 34,
160 __SIGRTMIN + 35,
161 __SIGRTMIN + 36,
162 __SIGRTMIN + 37,
163 __SIGRTMIN + 38,
164 __SIGRTMIN + 39,
165 __SIGRTMIN + 40,
166 __SIGRTMIN + 41,
167 __SIGRTMIN + 42,
168 __SIGRTMIN + 43,
169 __SIGRTMIN + 44,
170 __SIGRTMIN + 45,
171 __SIGRTMIN + 46,
172 __SIGRTMIN + 47,
173 __SIGRTMIN + 48,
174 __SIGRTMIN + 49,
175 __SIGRTMIN + 50,
176 __SIGRTMIN + 51,
177 __SIGRTMIN + 52,
178 __SIGRTMIN + 53,
179 __SIGRTMIN + 54,
180 __SIGRTMIN + 55,
181 __SIGRTMIN + 56,
182 __SIGRTMIN + 57,
183 __SIGRTMIN + 58,
184 __SIGRTMIN + 59,
185 __SIGRTMIN + 60,
186 __SIGRTMIN + 61,
187 __SIGRTMIN + 62,
188 __SIGRTMIN + 63,
189 __SIGRTMIN + 64,
190 __SIGRTMIN + 65,
191 __SIGRTMIN + 66,
192 __SIGRTMIN + 67,
193 __SIGRTMIN + 68,
194 __SIGRTMIN + 69,
195 __SIGRTMIN + 70,
196 __SIGRTMIN + 71,
197 __SIGRTMIN + 72,
198 __SIGRTMIN + 73,
199 __SIGRTMIN + 74,
200 __SIGRTMIN + 75,
201 __SIGRTMIN + 76,
202 __SIGRTMIN + 77,
203 __SIGRTMIN + 78,
204 __SIGRTMIN + 79,
205 __SIGRTMIN + 80,
206 __SIGRTMIN + 81,
207 __SIGRTMIN + 82,
208 __SIGRTMIN + 83,
209 __SIGRTMIN + 84,
210 __SIGRTMIN + 85,
211 __SIGRTMIN + 86,
212 __SIGRTMIN + 87,
213 __SIGRTMIN + 88,
214 __SIGRTMIN + 89,
215 __SIGRTMIN + 90,
216 __SIGRTMIN + 91,
217 __SIGRTMIN + 92,
218 __SIGRTMIN + 93,
219 __SIGRTMIN + 94,
220 __SIGRTMIN + 95,
221 -1, /* SIGINFO */
222 -1, /* UNKNOWN */
223 -1, /* DEFAULT */
224 -1,
225 -1,
226 -1,
227 -1,
228 -1,
229 -1
230 #endif
231 };
232 #else
233 /* In system mode we only need SIGINT and SIGTRAP; other signals
234 are not yet supported. */
235
236 enum {
237 TARGET_SIGINT = 2,
238 TARGET_SIGTRAP = 5
239 };
240
241 static int gdb_signal_table[] = {
242 -1,
243 -1,
244 TARGET_SIGINT,
245 -1,
246 -1,
247 TARGET_SIGTRAP
248 };
249 #endif
250
251 #ifdef CONFIG_USER_ONLY
252 static int target_signal_to_gdb (int sig)
253 {
254 int i;
255 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
256 if (gdb_signal_table[i] == sig)
257 return i;
258 return GDB_SIGNAL_UNKNOWN;
259 }
260 #endif
261
262 static int gdb_signal_to_target (int sig)
263 {
264 if (sig < ARRAY_SIZE (gdb_signal_table))
265 return gdb_signal_table[sig];
266 else
267 return -1;
268 }
269
270 //#define DEBUG_GDB
271
272 typedef struct GDBRegisterState {
273 int base_reg;
274 int num_regs;
275 gdb_reg_cb get_reg;
276 gdb_reg_cb set_reg;
277 const char *xml;
278 struct GDBRegisterState *next;
279 } GDBRegisterState;
280
281 enum RSState {
282 RS_INACTIVE,
283 RS_IDLE,
284 RS_GETLINE,
285 RS_CHKSUM1,
286 RS_CHKSUM2,
287 RS_SYSCALL,
288 };
289 typedef struct GDBState {
290 CPUState *c_cpu; /* current CPU for step/continue ops */
291 CPUState *g_cpu; /* current CPU for other ops */
292 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
293 enum RSState state; /* parsing state */
294 char line_buf[MAX_PACKET_LENGTH];
295 int line_buf_index;
296 int line_csum;
297 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
298 int last_packet_len;
299 int signal;
300 #ifdef CONFIG_USER_ONLY
301 int fd;
302 int running_state;
303 #else
304 CharDriverState *chr;
305 CharDriverState *mon_chr;
306 #endif
307 } GDBState;
308
309 /* By default use no IRQs and no timers while single stepping so as to
310 * make single stepping like an ICE HW step.
311 */
312 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
313
314 static GDBState *gdbserver_state;
315
316 /* This is an ugly hack to cope with both new and old gdb.
317 If gdb sends qXfer:features:read then assume we're talking to a newish
318 gdb that understands target descriptions. */
319 static int gdb_has_xml;
320
321 #ifdef CONFIG_USER_ONLY
322 /* XXX: This is not thread safe. Do we care? */
323 static int gdbserver_fd = -1;
324
325 static int get_char(GDBState *s)
326 {
327 uint8_t ch;
328 int ret;
329
330 for(;;) {
331 ret = qemu_recv(s->fd, &ch, 1, 0);
332 if (ret < 0) {
333 if (errno == ECONNRESET)
334 s->fd = -1;
335 if (errno != EINTR && errno != EAGAIN)
336 return -1;
337 } else if (ret == 0) {
338 close(s->fd);
339 s->fd = -1;
340 return -1;
341 } else {
342 break;
343 }
344 }
345 return ch;
346 }
347 #endif
348
349 static gdb_syscall_complete_cb gdb_current_syscall_cb;
350
351 static enum {
352 GDB_SYS_UNKNOWN,
353 GDB_SYS_ENABLED,
354 GDB_SYS_DISABLED,
355 } gdb_syscall_mode;
356
357 /* If gdb is connected when the first semihosting syscall occurs then use
358 remote gdb syscalls. Otherwise use native file IO. */
359 int use_gdb_syscalls(void)
360 {
361 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
362 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
363 : GDB_SYS_DISABLED);
364 }
365 return gdb_syscall_mode == GDB_SYS_ENABLED;
366 }
367
368 /* Resume execution. */
369 static inline void gdb_continue(GDBState *s)
370 {
371 #ifdef CONFIG_USER_ONLY
372 s->running_state = 1;
373 #else
374 vm_start();
375 #endif
376 }
377
378 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
379 {
380 #ifdef CONFIG_USER_ONLY
381 int ret;
382
383 while (len > 0) {
384 ret = send(s->fd, buf, len, 0);
385 if (ret < 0) {
386 if (errno != EINTR && errno != EAGAIN)
387 return;
388 } else {
389 buf += ret;
390 len -= ret;
391 }
392 }
393 #else
394 qemu_chr_fe_write(s->chr, buf, len);
395 #endif
396 }
397
398 static inline int fromhex(int v)
399 {
400 if (v >= '0' && v <= '9')
401 return v - '0';
402 else if (v >= 'A' && v <= 'F')
403 return v - 'A' + 10;
404 else if (v >= 'a' && v <= 'f')
405 return v - 'a' + 10;
406 else
407 return 0;
408 }
409
410 static inline int tohex(int v)
411 {
412 if (v < 10)
413 return v + '0';
414 else
415 return v - 10 + 'a';
416 }
417
418 static void memtohex(char *buf, const uint8_t *mem, int len)
419 {
420 int i, c;
421 char *q;
422 q = buf;
423 for(i = 0; i < len; i++) {
424 c = mem[i];
425 *q++ = tohex(c >> 4);
426 *q++ = tohex(c & 0xf);
427 }
428 *q = '\0';
429 }
430
431 static void hextomem(uint8_t *mem, const char *buf, int len)
432 {
433 int i;
434
435 for(i = 0; i < len; i++) {
436 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
437 buf += 2;
438 }
439 }
440
441 /* return -1 if error, 0 if OK */
442 static int put_packet_binary(GDBState *s, const char *buf, int len)
443 {
444 int csum, i;
445 uint8_t *p;
446
447 for(;;) {
448 p = s->last_packet;
449 *(p++) = '$';
450 memcpy(p, buf, len);
451 p += len;
452 csum = 0;
453 for(i = 0; i < len; i++) {
454 csum += buf[i];
455 }
456 *(p++) = '#';
457 *(p++) = tohex((csum >> 4) & 0xf);
458 *(p++) = tohex((csum) & 0xf);
459
460 s->last_packet_len = p - s->last_packet;
461 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
462
463 #ifdef CONFIG_USER_ONLY
464 i = get_char(s);
465 if (i < 0)
466 return -1;
467 if (i == '+')
468 break;
469 #else
470 break;
471 #endif
472 }
473 return 0;
474 }
475
476 /* return -1 if error, 0 if OK */
477 static int put_packet(GDBState *s, const char *buf)
478 {
479 #ifdef DEBUG_GDB
480 printf("reply='%s'\n", buf);
481 #endif
482
483 return put_packet_binary(s, buf, strlen(buf));
484 }
485
486 /* The GDB remote protocol transfers values in target byte order. This means
487 we can use the raw memory access routines to access the value buffer.
488 Conveniently, these also handle the case where the buffer is mis-aligned.
489 */
490 #define GET_REG8(val) do { \
491 stb_p(mem_buf, val); \
492 return 1; \
493 } while(0)
494 #define GET_REG16(val) do { \
495 stw_p(mem_buf, val); \
496 return 2; \
497 } while(0)
498 #define GET_REG32(val) do { \
499 stl_p(mem_buf, val); \
500 return 4; \
501 } while(0)
502 #define GET_REG64(val) do { \
503 stq_p(mem_buf, val); \
504 return 8; \
505 } while(0)
506
507 #if TARGET_LONG_BITS == 64
508 #define GET_REGL(val) GET_REG64(val)
509 #define ldtul_p(addr) ldq_p(addr)
510 #else
511 #define GET_REGL(val) GET_REG32(val)
512 #define ldtul_p(addr) ldl_p(addr)
513 #endif
514
515 #if defined(TARGET_I386)
516
517 #ifdef TARGET_X86_64
518 static const int gpr_map[16] = {
519 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
520 8, 9, 10, 11, 12, 13, 14, 15
521 };
522 #else
523 #define gpr_map gpr_map32
524 #endif
525 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
526
527 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
528
529 #define IDX_IP_REG CPU_NB_REGS
530 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
531 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
532 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
533 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
534 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
535
536 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
537 {
538 if (n < CPU_NB_REGS) {
539 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
540 GET_REG64(env->regs[gpr_map[n]]);
541 } else if (n < CPU_NB_REGS32) {
542 GET_REG32(env->regs[gpr_map32[n]]);
543 }
544 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
545 #ifdef USE_X86LDOUBLE
546 /* FIXME: byteswap float values - after fixing fpregs layout. */
547 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
548 #else
549 memset(mem_buf, 0, 10);
550 #endif
551 return 10;
552 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
553 n -= IDX_XMM_REGS;
554 if (n < CPU_NB_REGS32 ||
555 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
556 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
557 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
558 return 16;
559 }
560 } else {
561 switch (n) {
562 case IDX_IP_REG:
563 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
564 GET_REG64(env->eip);
565 } else {
566 GET_REG32(env->eip);
567 }
568 case IDX_FLAGS_REG: GET_REG32(env->eflags);
569
570 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
571 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
572 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
573 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
574 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
575 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
576
577 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
578 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
579 (env->fpstt & 0x7) << 11);
580 case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
581 case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
582 case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
583 case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
584 case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
585 case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
586
587 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
588 }
589 }
590 return 0;
591 }
592
593 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
594 {
595 uint16_t selector = ldl_p(mem_buf);
596
597 if (selector != env->segs[sreg].selector) {
598 #if defined(CONFIG_USER_ONLY)
599 cpu_x86_load_seg(env, sreg, selector);
600 #else
601 unsigned int limit, flags;
602 target_ulong base;
603
604 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
605 base = selector << 4;
606 limit = 0xffff;
607 flags = 0;
608 } else {
609 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
610 return 4;
611 }
612 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
613 #endif
614 }
615 return 4;
616 }
617
618 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
619 {
620 uint32_t tmp;
621
622 if (n < CPU_NB_REGS) {
623 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
624 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
625 return sizeof(target_ulong);
626 } else if (n < CPU_NB_REGS32) {
627 n = gpr_map32[n];
628 env->regs[n] &= ~0xffffffffUL;
629 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
630 return 4;
631 }
632 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
633 #ifdef USE_X86LDOUBLE
634 /* FIXME: byteswap float values - after fixing fpregs layout. */
635 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
636 #endif
637 return 10;
638 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
639 n -= IDX_XMM_REGS;
640 if (n < CPU_NB_REGS32 ||
641 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
642 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
643 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
644 return 16;
645 }
646 } else {
647 switch (n) {
648 case IDX_IP_REG:
649 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
650 env->eip = ldq_p(mem_buf);
651 return 8;
652 } else {
653 env->eip &= ~0xffffffffUL;
654 env->eip |= (uint32_t)ldl_p(mem_buf);
655 return 4;
656 }
657 case IDX_FLAGS_REG:
658 env->eflags = ldl_p(mem_buf);
659 return 4;
660
661 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
662 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
663 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
664 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
665 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
666 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
667
668 case IDX_FP_REGS + 8:
669 env->fpuc = ldl_p(mem_buf);
670 return 4;
671 case IDX_FP_REGS + 9:
672 tmp = ldl_p(mem_buf);
673 env->fpstt = (tmp >> 11) & 7;
674 env->fpus = tmp & ~0x3800;
675 return 4;
676 case IDX_FP_REGS + 10: /* ftag */ return 4;
677 case IDX_FP_REGS + 11: /* fiseg */ return 4;
678 case IDX_FP_REGS + 12: /* fioff */ return 4;
679 case IDX_FP_REGS + 13: /* foseg */ return 4;
680 case IDX_FP_REGS + 14: /* fooff */ return 4;
681 case IDX_FP_REGS + 15: /* fop */ return 4;
682
683 case IDX_MXCSR_REG:
684 env->mxcsr = ldl_p(mem_buf);
685 return 4;
686 }
687 }
688 /* Unrecognised register. */
689 return 0;
690 }
691
692 #elif defined (TARGET_PPC)
693
694 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
695 expects whatever the target description contains. Due to a
696 historical mishap the FP registers appear in between core integer
697 regs and PC, MSR, CR, and so forth. We hack round this by giving the
698 FP regs zero size when talking to a newer gdb. */
699 #define NUM_CORE_REGS 71
700 #if defined (TARGET_PPC64)
701 #define GDB_CORE_XML "power64-core.xml"
702 #else
703 #define GDB_CORE_XML "power-core.xml"
704 #endif
705
706 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
707 {
708 if (n < 32) {
709 /* gprs */
710 GET_REGL(env->gpr[n]);
711 } else if (n < 64) {
712 /* fprs */
713 if (gdb_has_xml)
714 return 0;
715 stfq_p(mem_buf, env->fpr[n-32]);
716 return 8;
717 } else {
718 switch (n) {
719 case 64: GET_REGL(env->nip);
720 case 65: GET_REGL(env->msr);
721 case 66:
722 {
723 uint32_t cr = 0;
724 int i;
725 for (i = 0; i < 8; i++)
726 cr |= env->crf[i] << (32 - ((i + 1) * 4));
727 GET_REG32(cr);
728 }
729 case 67: GET_REGL(env->lr);
730 case 68: GET_REGL(env->ctr);
731 case 69: GET_REGL(env->xer);
732 case 70:
733 {
734 if (gdb_has_xml)
735 return 0;
736 GET_REG32(env->fpscr);
737 }
738 }
739 }
740 return 0;
741 }
742
743 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
744 {
745 if (n < 32) {
746 /* gprs */
747 env->gpr[n] = ldtul_p(mem_buf);
748 return sizeof(target_ulong);
749 } else if (n < 64) {
750 /* fprs */
751 if (gdb_has_xml)
752 return 0;
753 env->fpr[n-32] = ldfq_p(mem_buf);
754 return 8;
755 } else {
756 switch (n) {
757 case 64:
758 env->nip = ldtul_p(mem_buf);
759 return sizeof(target_ulong);
760 case 65:
761 ppc_store_msr(env, ldtul_p(mem_buf));
762 return sizeof(target_ulong);
763 case 66:
764 {
765 uint32_t cr = ldl_p(mem_buf);
766 int i;
767 for (i = 0; i < 8; i++)
768 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
769 return 4;
770 }
771 case 67:
772 env->lr = ldtul_p(mem_buf);
773 return sizeof(target_ulong);
774 case 68:
775 env->ctr = ldtul_p(mem_buf);
776 return sizeof(target_ulong);
777 case 69:
778 env->xer = ldtul_p(mem_buf);
779 return sizeof(target_ulong);
780 case 70:
781 /* fpscr */
782 if (gdb_has_xml)
783 return 0;
784 return 4;
785 }
786 }
787 return 0;
788 }
789
790 #elif defined (TARGET_SPARC)
791
792 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
793 #define NUM_CORE_REGS 86
794 #else
795 #define NUM_CORE_REGS 72
796 #endif
797
798 #ifdef TARGET_ABI32
799 #define GET_REGA(val) GET_REG32(val)
800 #else
801 #define GET_REGA(val) GET_REGL(val)
802 #endif
803
804 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
805 {
806 if (n < 8) {
807 /* g0..g7 */
808 GET_REGA(env->gregs[n]);
809 }
810 if (n < 32) {
811 /* register window */
812 GET_REGA(env->regwptr[n - 8]);
813 }
814 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
815 if (n < 64) {
816 /* fprs */
817 if (n & 1) {
818 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
819 } else {
820 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
821 }
822 }
823 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
824 switch (n) {
825 case 64: GET_REGA(env->y);
826 case 65: GET_REGA(cpu_get_psr(env));
827 case 66: GET_REGA(env->wim);
828 case 67: GET_REGA(env->tbr);
829 case 68: GET_REGA(env->pc);
830 case 69: GET_REGA(env->npc);
831 case 70: GET_REGA(env->fsr);
832 case 71: GET_REGA(0); /* csr */
833 default: GET_REGA(0);
834 }
835 #else
836 if (n < 64) {
837 /* f0-f31 */
838 if (n & 1) {
839 GET_REG32(env->fpr[(n - 32) / 2].l.lower);
840 } else {
841 GET_REG32(env->fpr[(n - 32) / 2].l.upper);
842 }
843 }
844 if (n < 80) {
845 /* f32-f62 (double width, even numbers only) */
846 GET_REG64(env->fpr[(n - 32) / 2].ll);
847 }
848 switch (n) {
849 case 80: GET_REGL(env->pc);
850 case 81: GET_REGL(env->npc);
851 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
852 ((env->asi & 0xff) << 24) |
853 ((env->pstate & 0xfff) << 8) |
854 cpu_get_cwp64(env));
855 case 83: GET_REGL(env->fsr);
856 case 84: GET_REGL(env->fprs);
857 case 85: GET_REGL(env->y);
858 }
859 #endif
860 return 0;
861 }
862
863 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
864 {
865 #if defined(TARGET_ABI32)
866 abi_ulong tmp;
867
868 tmp = ldl_p(mem_buf);
869 #else
870 target_ulong tmp;
871
872 tmp = ldtul_p(mem_buf);
873 #endif
874
875 if (n < 8) {
876 /* g0..g7 */
877 env->gregs[n] = tmp;
878 } else if (n < 32) {
879 /* register window */
880 env->regwptr[n - 8] = tmp;
881 }
882 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
883 else if (n < 64) {
884 /* fprs */
885 /* f0-f31 */
886 if (n & 1) {
887 env->fpr[(n - 32) / 2].l.lower = tmp;
888 } else {
889 env->fpr[(n - 32) / 2].l.upper = tmp;
890 }
891 } else {
892 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
893 switch (n) {
894 case 64: env->y = tmp; break;
895 case 65: cpu_put_psr(env, tmp); break;
896 case 66: env->wim = tmp; break;
897 case 67: env->tbr = tmp; break;
898 case 68: env->pc = tmp; break;
899 case 69: env->npc = tmp; break;
900 case 70: env->fsr = tmp; break;
901 default: return 0;
902 }
903 }
904 return 4;
905 #else
906 else if (n < 64) {
907 /* f0-f31 */
908 tmp = ldl_p(mem_buf);
909 if (n & 1) {
910 env->fpr[(n - 32) / 2].l.lower = tmp;
911 } else {
912 env->fpr[(n - 32) / 2].l.upper = tmp;
913 }
914 return 4;
915 } else if (n < 80) {
916 /* f32-f62 (double width, even numbers only) */
917 env->fpr[(n - 32) / 2].ll = tmp;
918 } else {
919 switch (n) {
920 case 80: env->pc = tmp; break;
921 case 81: env->npc = tmp; break;
922 case 82:
923 cpu_put_ccr(env, tmp >> 32);
924 env->asi = (tmp >> 24) & 0xff;
925 env->pstate = (tmp >> 8) & 0xfff;
926 cpu_put_cwp64(env, tmp & 0xff);
927 break;
928 case 83: env->fsr = tmp; break;
929 case 84: env->fprs = tmp; break;
930 case 85: env->y = tmp; break;
931 default: return 0;
932 }
933 }
934 return 8;
935 #endif
936 }
937 #elif defined (TARGET_ARM)
938
939 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
940 whatever the target description contains. Due to a historical mishap
941 the FPA registers appear in between core integer regs and the CPSR.
942 We hack round this by giving the FPA regs zero size when talking to a
943 newer gdb. */
944 #define NUM_CORE_REGS 26
945 #define GDB_CORE_XML "arm-core.xml"
946
947 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
948 {
949 if (n < 16) {
950 /* Core integer register. */
951 GET_REG32(env->regs[n]);
952 }
953 if (n < 24) {
954 /* FPA registers. */
955 if (gdb_has_xml)
956 return 0;
957 memset(mem_buf, 0, 12);
958 return 12;
959 }
960 switch (n) {
961 case 24:
962 /* FPA status register. */
963 if (gdb_has_xml)
964 return 0;
965 GET_REG32(0);
966 case 25:
967 /* CPSR */
968 GET_REG32(cpsr_read(env));
969 }
970 /* Unknown register. */
971 return 0;
972 }
973
974 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
975 {
976 uint32_t tmp;
977
978 tmp = ldl_p(mem_buf);
979
980 /* Mask out low bit of PC to workaround gdb bugs. This will probably
981 cause problems if we ever implement the Jazelle DBX extensions. */
982 if (n == 15)
983 tmp &= ~1;
984
985 if (n < 16) {
986 /* Core integer register. */
987 env->regs[n] = tmp;
988 return 4;
989 }
990 if (n < 24) { /* 16-23 */
991 /* FPA registers (ignored). */
992 if (gdb_has_xml)
993 return 0;
994 return 12;
995 }
996 switch (n) {
997 case 24:
998 /* FPA status register (ignored). */
999 if (gdb_has_xml)
1000 return 0;
1001 return 4;
1002 case 25:
1003 /* CPSR */
1004 cpsr_write (env, tmp, 0xffffffff);
1005 return 4;
1006 }
1007 /* Unknown register. */
1008 return 0;
1009 }
1010
1011 #elif defined (TARGET_M68K)
1012
1013 #define NUM_CORE_REGS 18
1014
1015 #define GDB_CORE_XML "cf-core.xml"
1016
1017 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1018 {
1019 if (n < 8) {
1020 /* D0-D7 */
1021 GET_REG32(env->dregs[n]);
1022 } else if (n < 16) {
1023 /* A0-A7 */
1024 GET_REG32(env->aregs[n - 8]);
1025 } else {
1026 switch (n) {
1027 case 16: GET_REG32(env->sr);
1028 case 17: GET_REG32(env->pc);
1029 }
1030 }
1031 /* FP registers not included here because they vary between
1032 ColdFire and m68k. Use XML bits for these. */
1033 return 0;
1034 }
1035
1036 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1037 {
1038 uint32_t tmp;
1039
1040 tmp = ldl_p(mem_buf);
1041
1042 if (n < 8) {
1043 /* D0-D7 */
1044 env->dregs[n] = tmp;
1045 } else if (n < 16) {
1046 /* A0-A7 */
1047 env->aregs[n - 8] = tmp;
1048 } else {
1049 switch (n) {
1050 case 16: env->sr = tmp; break;
1051 case 17: env->pc = tmp; break;
1052 default: return 0;
1053 }
1054 }
1055 return 4;
1056 }
1057 #elif defined (TARGET_MIPS)
1058
1059 #define NUM_CORE_REGS 73
1060
1061 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1062 {
1063 if (n < 32) {
1064 GET_REGL(env->active_tc.gpr[n]);
1065 }
1066 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1067 if (n >= 38 && n < 70) {
1068 if (env->CP0_Status & (1 << CP0St_FR))
1069 GET_REGL(env->active_fpu.fpr[n - 38].d);
1070 else
1071 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1072 }
1073 switch (n) {
1074 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1075 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1076 }
1077 }
1078 switch (n) {
1079 case 32: GET_REGL((int32_t)env->CP0_Status);
1080 case 33: GET_REGL(env->active_tc.LO[0]);
1081 case 34: GET_REGL(env->active_tc.HI[0]);
1082 case 35: GET_REGL(env->CP0_BadVAddr);
1083 case 36: GET_REGL((int32_t)env->CP0_Cause);
1084 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1085 case 72: GET_REGL(0); /* fp */
1086 case 89: GET_REGL((int32_t)env->CP0_PRid);
1087 }
1088 if (n >= 73 && n <= 88) {
1089 /* 16 embedded regs. */
1090 GET_REGL(0);
1091 }
1092
1093 return 0;
1094 }
1095
1096 /* convert MIPS rounding mode in FCR31 to IEEE library */
1097 static unsigned int ieee_rm[] =
1098 {
1099 float_round_nearest_even,
1100 float_round_to_zero,
1101 float_round_up,
1102 float_round_down
1103 };
1104 #define RESTORE_ROUNDING_MODE \
1105 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1106
1107 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1108 {
1109 target_ulong tmp;
1110
1111 tmp = ldtul_p(mem_buf);
1112
1113 if (n < 32) {
1114 env->active_tc.gpr[n] = tmp;
1115 return sizeof(target_ulong);
1116 }
1117 if (env->CP0_Config1 & (1 << CP0C1_FP)
1118 && n >= 38 && n < 73) {
1119 if (n < 70) {
1120 if (env->CP0_Status & (1 << CP0St_FR))
1121 env->active_fpu.fpr[n - 38].d = tmp;
1122 else
1123 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1124 }
1125 switch (n) {
1126 case 70:
1127 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1128 /* set rounding mode */
1129 RESTORE_ROUNDING_MODE;
1130 break;
1131 case 71: env->active_fpu.fcr0 = tmp; break;
1132 }
1133 return sizeof(target_ulong);
1134 }
1135 switch (n) {
1136 case 32: env->CP0_Status = tmp; break;
1137 case 33: env->active_tc.LO[0] = tmp; break;
1138 case 34: env->active_tc.HI[0] = tmp; break;
1139 case 35: env->CP0_BadVAddr = tmp; break;
1140 case 36: env->CP0_Cause = tmp; break;
1141 case 37:
1142 env->active_tc.PC = tmp & ~(target_ulong)1;
1143 if (tmp & 1) {
1144 env->hflags |= MIPS_HFLAG_M16;
1145 } else {
1146 env->hflags &= ~(MIPS_HFLAG_M16);
1147 }
1148 break;
1149 case 72: /* fp, ignored */ break;
1150 default:
1151 if (n > 89)
1152 return 0;
1153 /* Other registers are readonly. Ignore writes. */
1154 break;
1155 }
1156
1157 return sizeof(target_ulong);
1158 }
1159 #elif defined (TARGET_SH4)
1160
1161 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1162 /* FIXME: We should use XML for this. */
1163
1164 #define NUM_CORE_REGS 59
1165
1166 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1167 {
1168 if (n < 8) {
1169 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1170 GET_REGL(env->gregs[n + 16]);
1171 } else {
1172 GET_REGL(env->gregs[n]);
1173 }
1174 } else if (n < 16) {
1175 GET_REGL(env->gregs[n]);
1176 } else if (n >= 25 && n < 41) {
1177 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1178 } else if (n >= 43 && n < 51) {
1179 GET_REGL(env->gregs[n - 43]);
1180 } else if (n >= 51 && n < 59) {
1181 GET_REGL(env->gregs[n - (51 - 16)]);
1182 }
1183 switch (n) {
1184 case 16: GET_REGL(env->pc);
1185 case 17: GET_REGL(env->pr);
1186 case 18: GET_REGL(env->gbr);
1187 case 19: GET_REGL(env->vbr);
1188 case 20: GET_REGL(env->mach);
1189 case 21: GET_REGL(env->macl);
1190 case 22: GET_REGL(env->sr);
1191 case 23: GET_REGL(env->fpul);
1192 case 24: GET_REGL(env->fpscr);
1193 case 41: GET_REGL(env->ssr);
1194 case 42: GET_REGL(env->spc);
1195 }
1196
1197 return 0;
1198 }
1199
1200 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1201 {
1202 uint32_t tmp;
1203
1204 tmp = ldl_p(mem_buf);
1205
1206 if (n < 8) {
1207 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1208 env->gregs[n + 16] = tmp;
1209 } else {
1210 env->gregs[n] = tmp;
1211 }
1212 return 4;
1213 } else if (n < 16) {
1214 env->gregs[n] = tmp;
1215 return 4;
1216 } else if (n >= 25 && n < 41) {
1217 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1218 return 4;
1219 } else if (n >= 43 && n < 51) {
1220 env->gregs[n - 43] = tmp;
1221 return 4;
1222 } else if (n >= 51 && n < 59) {
1223 env->gregs[n - (51 - 16)] = tmp;
1224 return 4;
1225 }
1226 switch (n) {
1227 case 16: env->pc = tmp; break;
1228 case 17: env->pr = tmp; break;
1229 case 18: env->gbr = tmp; break;
1230 case 19: env->vbr = tmp; break;
1231 case 20: env->mach = tmp; break;
1232 case 21: env->macl = tmp; break;
1233 case 22: env->sr = tmp; break;
1234 case 23: env->fpul = tmp; break;
1235 case 24: env->fpscr = tmp; break;
1236 case 41: env->ssr = tmp; break;
1237 case 42: env->spc = tmp; break;
1238 default: return 0;
1239 }
1240
1241 return 4;
1242 }
1243 #elif defined (TARGET_MICROBLAZE)
1244
1245 #define NUM_CORE_REGS (32 + 5)
1246
1247 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1248 {
1249 if (n < 32) {
1250 GET_REG32(env->regs[n]);
1251 } else {
1252 GET_REG32(env->sregs[n - 32]);
1253 }
1254 return 0;
1255 }
1256
1257 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1258 {
1259 uint32_t tmp;
1260
1261 if (n > NUM_CORE_REGS)
1262 return 0;
1263
1264 tmp = ldl_p(mem_buf);
1265
1266 if (n < 32) {
1267 env->regs[n] = tmp;
1268 } else {
1269 env->sregs[n - 32] = tmp;
1270 }
1271 return 4;
1272 }
1273 #elif defined (TARGET_CRIS)
1274
1275 #define NUM_CORE_REGS 49
1276
1277 static int
1278 read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
1279 {
1280 if (n < 15) {
1281 GET_REG32(env->regs[n]);
1282 }
1283
1284 if (n == 15) {
1285 GET_REG32(env->pc);
1286 }
1287
1288 if (n < 32) {
1289 switch (n) {
1290 case 16:
1291 GET_REG8(env->pregs[n - 16]);
1292 break;
1293 case 17:
1294 GET_REG8(env->pregs[n - 16]);
1295 break;
1296 case 20:
1297 case 21:
1298 GET_REG16(env->pregs[n - 16]);
1299 break;
1300 default:
1301 if (n >= 23) {
1302 GET_REG32(env->pregs[n - 16]);
1303 }
1304 break;
1305 }
1306 }
1307 return 0;
1308 }
1309
1310 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1311 {
1312 uint8_t srs;
1313
1314 if (env->pregs[PR_VR] < 32)
1315 return read_register_crisv10(env, mem_buf, n);
1316
1317 srs = env->pregs[PR_SRS];
1318 if (n < 16) {
1319 GET_REG32(env->regs[n]);
1320 }
1321
1322 if (n >= 21 && n < 32) {
1323 GET_REG32(env->pregs[n - 16]);
1324 }
1325 if (n >= 33 && n < 49) {
1326 GET_REG32(env->sregs[srs][n - 33]);
1327 }
1328 switch (n) {
1329 case 16: GET_REG8(env->pregs[0]);
1330 case 17: GET_REG8(env->pregs[1]);
1331 case 18: GET_REG32(env->pregs[2]);
1332 case 19: GET_REG8(srs);
1333 case 20: GET_REG16(env->pregs[4]);
1334 case 32: GET_REG32(env->pc);
1335 }
1336
1337 return 0;
1338 }
1339
1340 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1341 {
1342 uint32_t tmp;
1343
1344 if (n > 49)
1345 return 0;
1346
1347 tmp = ldl_p(mem_buf);
1348
1349 if (n < 16) {
1350 env->regs[n] = tmp;
1351 }
1352
1353 if (n >= 21 && n < 32) {
1354 env->pregs[n - 16] = tmp;
1355 }
1356
1357 /* FIXME: Should support function regs be writable? */
1358 switch (n) {
1359 case 16: return 1;
1360 case 17: return 1;
1361 case 18: env->pregs[PR_PID] = tmp; break;
1362 case 19: return 1;
1363 case 20: return 2;
1364 case 32: env->pc = tmp; break;
1365 }
1366
1367 return 4;
1368 }
1369 #elif defined (TARGET_ALPHA)
1370
1371 #define NUM_CORE_REGS 67
1372
1373 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1374 {
1375 uint64_t val;
1376 CPU_DoubleU d;
1377
1378 switch (n) {
1379 case 0 ... 30:
1380 val = env->ir[n];
1381 break;
1382 case 32 ... 62:
1383 d.d = env->fir[n - 32];
1384 val = d.ll;
1385 break;
1386 case 63:
1387 val = cpu_alpha_load_fpcr(env);
1388 break;
1389 case 64:
1390 val = env->pc;
1391 break;
1392 case 66:
1393 val = env->unique;
1394 break;
1395 case 31:
1396 case 65:
1397 /* 31 really is the zero register; 65 is unassigned in the
1398 gdb protocol, but is still required to occupy 8 bytes. */
1399 val = 0;
1400 break;
1401 default:
1402 return 0;
1403 }
1404 GET_REGL(val);
1405 }
1406
1407 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1408 {
1409 target_ulong tmp = ldtul_p(mem_buf);
1410 CPU_DoubleU d;
1411
1412 switch (n) {
1413 case 0 ... 30:
1414 env->ir[n] = tmp;
1415 break;
1416 case 32 ... 62:
1417 d.ll = tmp;
1418 env->fir[n - 32] = d.d;
1419 break;
1420 case 63:
1421 cpu_alpha_store_fpcr(env, tmp);
1422 break;
1423 case 64:
1424 env->pc = tmp;
1425 break;
1426 case 66:
1427 env->unique = tmp;
1428 break;
1429 case 31:
1430 case 65:
1431 /* 31 really is the zero register; 65 is unassigned in the
1432 gdb protocol, but is still required to occupy 8 bytes. */
1433 break;
1434 default:
1435 return 0;
1436 }
1437 return 8;
1438 }
1439 #elif defined (TARGET_S390X)
1440
1441 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1442
1443 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1444 {
1445 switch (n) {
1446 case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1447 case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1448 case S390_R0_REGNUM ... S390_R15_REGNUM:
1449 GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1450 case S390_A0_REGNUM ... S390_A15_REGNUM:
1451 GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1452 case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1453 case S390_F0_REGNUM ... S390_F15_REGNUM:
1454 /* XXX */
1455 break;
1456 case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1457 case S390_CC_REGNUM:
1458 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
1459 env->cc_vr);
1460 GET_REG32(env->cc_op);
1461 break;
1462 }
1463
1464 return 0;
1465 }
1466
1467 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1468 {
1469 target_ulong tmpl;
1470 uint32_t tmp32;
1471 int r = 8;
1472 tmpl = ldtul_p(mem_buf);
1473 tmp32 = ldl_p(mem_buf);
1474
1475 switch (n) {
1476 case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1477 case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1478 case S390_R0_REGNUM ... S390_R15_REGNUM:
1479 env->regs[n-S390_R0_REGNUM] = tmpl; break;
1480 case S390_A0_REGNUM ... S390_A15_REGNUM:
1481 env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1482 case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1483 case S390_F0_REGNUM ... S390_F15_REGNUM:
1484 /* XXX */
1485 break;
1486 case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1487 case S390_CC_REGNUM: env->cc_op = tmp32; r=4; break;
1488 }
1489
1490 return r;
1491 }
1492 #elif defined (TARGET_LM32)
1493
1494 #include "hw/lm32_pic.h"
1495 #define NUM_CORE_REGS (32 + 7)
1496
1497 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1498 {
1499 if (n < 32) {
1500 GET_REG32(env->regs[n]);
1501 } else {
1502 switch (n) {
1503 case 32:
1504 GET_REG32(env->pc);
1505 break;
1506 /* FIXME: put in right exception ID */
1507 case 33:
1508 GET_REG32(0);
1509 break;
1510 case 34:
1511 GET_REG32(env->eba);
1512 break;
1513 case 35:
1514 GET_REG32(env->deba);
1515 break;
1516 case 36:
1517 GET_REG32(env->ie);
1518 break;
1519 case 37:
1520 GET_REG32(lm32_pic_get_im(env->pic_state));
1521 break;
1522 case 38:
1523 GET_REG32(lm32_pic_get_ip(env->pic_state));
1524 break;
1525 }
1526 }
1527 return 0;
1528 }
1529
1530 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1531 {
1532 uint32_t tmp;
1533
1534 if (n > NUM_CORE_REGS) {
1535 return 0;
1536 }
1537
1538 tmp = ldl_p(mem_buf);
1539
1540 if (n < 32) {
1541 env->regs[n] = tmp;
1542 } else {
1543 switch (n) {
1544 case 32:
1545 env->pc = tmp;
1546 break;
1547 case 34:
1548 env->eba = tmp;
1549 break;
1550 case 35:
1551 env->deba = tmp;
1552 break;
1553 case 36:
1554 env->ie = tmp;
1555 break;
1556 case 37:
1557 lm32_pic_set_im(env->pic_state, tmp);
1558 break;
1559 case 38:
1560 lm32_pic_set_ip(env->pic_state, tmp);
1561 break;
1562 }
1563 }
1564 return 4;
1565 }
1566 #elif defined(TARGET_XTENSA)
1567
1568 /* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
1569 * Use num_regs to see all registers. gdb modification is required for that:
1570 * reset bit 0 in the 'flags' field of the registers definitions in the
1571 * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
1572 */
1573 #define NUM_CORE_REGS (env->config->gdb_regmap.num_regs)
1574 #define num_g_regs NUM_CORE_REGS
1575
1576 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1577 {
1578 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1579
1580 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1581 return 0;
1582 }
1583
1584 switch (reg->type) {
1585 case 9: /*pc*/
1586 GET_REG32(env->pc);
1587 break;
1588
1589 case 1: /*ar*/
1590 xtensa_sync_phys_from_window(env);
1591 GET_REG32(env->phys_regs[(reg->targno & 0xff) % env->config->nareg]);
1592 break;
1593
1594 case 2: /*SR*/
1595 GET_REG32(env->sregs[reg->targno & 0xff]);
1596 break;
1597
1598 case 3: /*UR*/
1599 GET_REG32(env->uregs[reg->targno & 0xff]);
1600 break;
1601
1602 case 8: /*a*/
1603 GET_REG32(env->regs[reg->targno & 0x0f]);
1604 break;
1605
1606 default:
1607 qemu_log("%s from reg %d of unsupported type %d\n",
1608 __func__, n, reg->type);
1609 return 0;
1610 }
1611 }
1612
1613 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1614 {
1615 uint32_t tmp;
1616 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
1617
1618 if (n < 0 || n >= env->config->gdb_regmap.num_regs) {
1619 return 0;
1620 }
1621
1622 tmp = ldl_p(mem_buf);
1623
1624 switch (reg->type) {
1625 case 9: /*pc*/
1626 env->pc = tmp;
1627 break;
1628
1629 case 1: /*ar*/
1630 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
1631 xtensa_sync_window_from_phys(env);
1632 break;
1633
1634 case 2: /*SR*/
1635 env->sregs[reg->targno & 0xff] = tmp;
1636 break;
1637
1638 case 3: /*UR*/
1639 env->uregs[reg->targno & 0xff] = tmp;
1640 break;
1641
1642 case 8: /*a*/
1643 env->regs[reg->targno & 0x0f] = tmp;
1644 break;
1645
1646 default:
1647 qemu_log("%s to reg %d of unsupported type %d\n",
1648 __func__, n, reg->type);
1649 return 0;
1650 }
1651
1652 return 4;
1653 }
1654 #else
1655
1656 #define NUM_CORE_REGS 0
1657
1658 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1659 {
1660 return 0;
1661 }
1662
1663 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1664 {
1665 return 0;
1666 }
1667
1668 #endif
1669
1670 #if !defined(TARGET_XTENSA)
1671 static int num_g_regs = NUM_CORE_REGS;
1672 #endif
1673
1674 #ifdef GDB_CORE_XML
1675 /* Encode data using the encoding for 'x' packets. */
1676 static int memtox(char *buf, const char *mem, int len)
1677 {
1678 char *p = buf;
1679 char c;
1680
1681 while (len--) {
1682 c = *(mem++);
1683 switch (c) {
1684 case '#': case '$': case '*': case '}':
1685 *(p++) = '}';
1686 *(p++) = c ^ 0x20;
1687 break;
1688 default:
1689 *(p++) = c;
1690 break;
1691 }
1692 }
1693 return p - buf;
1694 }
1695
1696 static const char *get_feature_xml(const char *p, const char **newp)
1697 {
1698 size_t len;
1699 int i;
1700 const char *name;
1701 static char target_xml[1024];
1702
1703 len = 0;
1704 while (p[len] && p[len] != ':')
1705 len++;
1706 *newp = p + len;
1707
1708 name = NULL;
1709 if (strncmp(p, "target.xml", len) == 0) {
1710 /* Generate the XML description for this CPU. */
1711 if (!target_xml[0]) {
1712 GDBRegisterState *r;
1713
1714 snprintf(target_xml, sizeof(target_xml),
1715 "<?xml version=\"1.0\"?>"
1716 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1717 "<target>"
1718 "<xi:include href=\"%s\"/>",
1719 GDB_CORE_XML);
1720
1721 for (r = first_cpu->gdb_regs; r; r = r->next) {
1722 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1723 pstrcat(target_xml, sizeof(target_xml), r->xml);
1724 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1725 }
1726 pstrcat(target_xml, sizeof(target_xml), "</target>");
1727 }
1728 return target_xml;
1729 }
1730 for (i = 0; ; i++) {
1731 name = xml_builtin[i][0];
1732 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1733 break;
1734 }
1735 return name ? xml_builtin[i][1] : NULL;
1736 }
1737 #endif
1738
1739 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1740 {
1741 GDBRegisterState *r;
1742
1743 if (reg < NUM_CORE_REGS)
1744 return cpu_gdb_read_register(env, mem_buf, reg);
1745
1746 for (r = env->gdb_regs; r; r = r->next) {
1747 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1748 return r->get_reg(env, mem_buf, reg - r->base_reg);
1749 }
1750 }
1751 return 0;
1752 }
1753
1754 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1755 {
1756 GDBRegisterState *r;
1757
1758 if (reg < NUM_CORE_REGS)
1759 return cpu_gdb_write_register(env, mem_buf, reg);
1760
1761 for (r = env->gdb_regs; r; r = r->next) {
1762 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1763 return r->set_reg(env, mem_buf, reg - r->base_reg);
1764 }
1765 }
1766 return 0;
1767 }
1768
1769 #if !defined(TARGET_XTENSA)
1770 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1771 specifies the first register number and these registers are included in
1772 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1773 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1774 */
1775
1776 void gdb_register_coprocessor(CPUState * env,
1777 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1778 int num_regs, const char *xml, int g_pos)
1779 {
1780 GDBRegisterState *s;
1781 GDBRegisterState **p;
1782 static int last_reg = NUM_CORE_REGS;
1783
1784 s = (GDBRegisterState *)g_malloc0(sizeof(GDBRegisterState));
1785 s->base_reg = last_reg;
1786 s->num_regs = num_regs;
1787 s->get_reg = get_reg;
1788 s->set_reg = set_reg;
1789 s->xml = xml;
1790 p = &env->gdb_regs;
1791 while (*p) {
1792 /* Check for duplicates. */
1793 if (strcmp((*p)->xml, xml) == 0)
1794 return;
1795 p = &(*p)->next;
1796 }
1797 /* Add to end of list. */
1798 last_reg += num_regs;
1799 *p = s;
1800 if (g_pos) {
1801 if (g_pos != s->base_reg) {
1802 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1803 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1804 } else {
1805 num_g_regs = last_reg;
1806 }
1807 }
1808 }
1809 #endif
1810
1811 #ifndef CONFIG_USER_ONLY
1812 static const int xlat_gdb_type[] = {
1813 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1814 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1815 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1816 };
1817 #endif
1818
1819 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1820 {
1821 CPUState *env;
1822 int err = 0;
1823
1824 if (kvm_enabled())
1825 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1826
1827 switch (type) {
1828 case GDB_BREAKPOINT_SW:
1829 case GDB_BREAKPOINT_HW:
1830 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1831 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1832 if (err)
1833 break;
1834 }
1835 return err;
1836 #ifndef CONFIG_USER_ONLY
1837 case GDB_WATCHPOINT_WRITE:
1838 case GDB_WATCHPOINT_READ:
1839 case GDB_WATCHPOINT_ACCESS:
1840 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1841 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1842 NULL);
1843 if (err)
1844 break;
1845 }
1846 return err;
1847 #endif
1848 default:
1849 return -ENOSYS;
1850 }
1851 }
1852
1853 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1854 {
1855 CPUState *env;
1856 int err = 0;
1857
1858 if (kvm_enabled())
1859 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1860
1861 switch (type) {
1862 case GDB_BREAKPOINT_SW:
1863 case GDB_BREAKPOINT_HW:
1864 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1865 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1866 if (err)
1867 break;
1868 }
1869 return err;
1870 #ifndef CONFIG_USER_ONLY
1871 case GDB_WATCHPOINT_WRITE:
1872 case GDB_WATCHPOINT_READ:
1873 case GDB_WATCHPOINT_ACCESS:
1874 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1875 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1876 if (err)
1877 break;
1878 }
1879 return err;
1880 #endif
1881 default:
1882 return -ENOSYS;
1883 }
1884 }
1885
1886 static void gdb_breakpoint_remove_all(void)
1887 {
1888 CPUState *env;
1889
1890 if (kvm_enabled()) {
1891 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1892 return;
1893 }
1894
1895 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1896 cpu_breakpoint_remove_all(env, BP_GDB);
1897 #ifndef CONFIG_USER_ONLY
1898 cpu_watchpoint_remove_all(env, BP_GDB);
1899 #endif
1900 }
1901 }
1902
1903 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1904 {
1905 #if defined(TARGET_I386)
1906 cpu_synchronize_state(s->c_cpu);
1907 s->c_cpu->eip = pc;
1908 #elif defined (TARGET_PPC)
1909 s->c_cpu->nip = pc;
1910 #elif defined (TARGET_SPARC)
1911 s->c_cpu->pc = pc;
1912 s->c_cpu->npc = pc + 4;
1913 #elif defined (TARGET_ARM)
1914 s->c_cpu->regs[15] = pc;
1915 #elif defined (TARGET_SH4)
1916 s->c_cpu->pc = pc;
1917 #elif defined (TARGET_MIPS)
1918 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1919 if (pc & 1) {
1920 s->c_cpu->hflags |= MIPS_HFLAG_M16;
1921 } else {
1922 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1923 }
1924 #elif defined (TARGET_MICROBLAZE)
1925 s->c_cpu->sregs[SR_PC] = pc;
1926 #elif defined (TARGET_CRIS)
1927 s->c_cpu->pc = pc;
1928 #elif defined (TARGET_ALPHA)
1929 s->c_cpu->pc = pc;
1930 #elif defined (TARGET_S390X)
1931 cpu_synchronize_state(s->c_cpu);
1932 s->c_cpu->psw.addr = pc;
1933 #elif defined (TARGET_LM32)
1934 s->c_cpu->pc = pc;
1935 #elif defined(TARGET_XTENSA)
1936 s->c_cpu->pc = pc;
1937 #endif
1938 }
1939
1940 static inline int gdb_id(CPUState *env)
1941 {
1942 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1943 return env->host_tid;
1944 #else
1945 return env->cpu_index + 1;
1946 #endif
1947 }
1948
1949 static CPUState *find_cpu(uint32_t thread_id)
1950 {
1951 CPUState *env;
1952
1953 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1954 if (gdb_id(env) == thread_id) {
1955 return env;
1956 }
1957 }
1958
1959 return NULL;
1960 }
1961
1962 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1963 {
1964 CPUState *env;
1965 const char *p;
1966 uint32_t thread;
1967 int ch, reg_size, type, res;
1968 char buf[MAX_PACKET_LENGTH];
1969 uint8_t mem_buf[MAX_PACKET_LENGTH];
1970 uint8_t *registers;
1971 target_ulong addr, len;
1972
1973 #ifdef DEBUG_GDB
1974 printf("command='%s'\n", line_buf);
1975 #endif
1976 p = line_buf;
1977 ch = *p++;
1978 switch(ch) {
1979 case '?':
1980 /* TODO: Make this return the correct value for user-mode. */
1981 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1982 gdb_id(s->c_cpu));
1983 put_packet(s, buf);
1984 /* Remove all the breakpoints when this query is issued,
1985 * because gdb is doing and initial connect and the state
1986 * should be cleaned up.
1987 */
1988 gdb_breakpoint_remove_all();
1989 break;
1990 case 'c':
1991 if (*p != '\0') {
1992 addr = strtoull(p, (char **)&p, 16);
1993 gdb_set_cpu_pc(s, addr);
1994 }
1995 s->signal = 0;
1996 gdb_continue(s);
1997 return RS_IDLE;
1998 case 'C':
1999 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
2000 if (s->signal == -1)
2001 s->signal = 0;
2002 gdb_continue(s);
2003 return RS_IDLE;
2004 case 'v':
2005 if (strncmp(p, "Cont", 4) == 0) {
2006 int res_signal, res_thread;
2007
2008 p += 4;
2009 if (*p == '?') {
2010 put_packet(s, "vCont;c;C;s;S");
2011 break;
2012 }
2013 res = 0;
2014 res_signal = 0;
2015 res_thread = 0;
2016 while (*p) {
2017 int action, signal;
2018
2019 if (*p++ != ';') {
2020 res = 0;
2021 break;
2022 }
2023 action = *p++;
2024 signal = 0;
2025 if (action == 'C' || action == 'S') {
2026 signal = strtoul(p, (char **)&p, 16);
2027 } else if (action != 'c' && action != 's') {
2028 res = 0;
2029 break;
2030 }
2031 thread = 0;
2032 if (*p == ':') {
2033 thread = strtoull(p+1, (char **)&p, 16);
2034 }
2035 action = tolower(action);
2036 if (res == 0 || (res == 'c' && action == 's')) {
2037 res = action;
2038 res_signal = signal;
2039 res_thread = thread;
2040 }
2041 }
2042 if (res) {
2043 if (res_thread != -1 && res_thread != 0) {
2044 env = find_cpu(res_thread);
2045 if (env == NULL) {
2046 put_packet(s, "E22");
2047 break;
2048 }
2049 s->c_cpu = env;
2050 }
2051 if (res == 's') {
2052 cpu_single_step(s->c_cpu, sstep_flags);
2053 }
2054 s->signal = res_signal;
2055 gdb_continue(s);
2056 return RS_IDLE;
2057 }
2058 break;
2059 } else {
2060 goto unknown_command;
2061 }
2062 case 'k':
2063 /* Kill the target */
2064 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
2065 exit(0);
2066 case 'D':
2067 /* Detach packet */
2068 gdb_breakpoint_remove_all();
2069 gdb_syscall_mode = GDB_SYS_DISABLED;
2070 gdb_continue(s);
2071 put_packet(s, "OK");
2072 break;
2073 case 's':
2074 if (*p != '\0') {
2075 addr = strtoull(p, (char **)&p, 16);
2076 gdb_set_cpu_pc(s, addr);
2077 }
2078 cpu_single_step(s->c_cpu, sstep_flags);
2079 gdb_continue(s);
2080 return RS_IDLE;
2081 case 'F':
2082 {
2083 target_ulong ret;
2084 target_ulong err;
2085
2086 ret = strtoull(p, (char **)&p, 16);
2087 if (*p == ',') {
2088 p++;
2089 err = strtoull(p, (char **)&p, 16);
2090 } else {
2091 err = 0;
2092 }
2093 if (*p == ',')
2094 p++;
2095 type = *p;
2096 if (gdb_current_syscall_cb)
2097 gdb_current_syscall_cb(s->c_cpu, ret, err);
2098 if (type == 'C') {
2099 put_packet(s, "T02");
2100 } else {
2101 gdb_continue(s);
2102 }
2103 }
2104 break;
2105 case 'g':
2106 cpu_synchronize_state(s->g_cpu);
2107 env = s->g_cpu;
2108 len = 0;
2109 for (addr = 0; addr < num_g_regs; addr++) {
2110 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
2111 len += reg_size;
2112 }
2113 memtohex(buf, mem_buf, len);
2114 put_packet(s, buf);
2115 break;
2116 case 'G':
2117 cpu_synchronize_state(s->g_cpu);
2118 env = s->g_cpu;
2119 registers = mem_buf;
2120 len = strlen(p) / 2;
2121 hextomem((uint8_t *)registers, p, len);
2122 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2123 reg_size = gdb_write_register(s->g_cpu, registers, addr);
2124 len -= reg_size;
2125 registers += reg_size;
2126 }
2127 put_packet(s, "OK");
2128 break;
2129 case 'm':
2130 addr = strtoull(p, (char **)&p, 16);
2131 if (*p == ',')
2132 p++;
2133 len = strtoull(p, NULL, 16);
2134 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2135 put_packet (s, "E14");
2136 } else {
2137 memtohex(buf, mem_buf, len);
2138 put_packet(s, buf);
2139 }
2140 break;
2141 case 'M':
2142 addr = strtoull(p, (char **)&p, 16);
2143 if (*p == ',')
2144 p++;
2145 len = strtoull(p, (char **)&p, 16);
2146 if (*p == ':')
2147 p++;
2148 hextomem(mem_buf, p, len);
2149 if (target_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) {
2150 put_packet(s, "E14");
2151 } else {
2152 put_packet(s, "OK");
2153 }
2154 break;
2155 case 'p':
2156 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2157 This works, but can be very slow. Anything new enough to
2158 understand XML also knows how to use this properly. */
2159 if (!gdb_has_xml)
2160 goto unknown_command;
2161 addr = strtoull(p, (char **)&p, 16);
2162 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2163 if (reg_size) {
2164 memtohex(buf, mem_buf, reg_size);
2165 put_packet(s, buf);
2166 } else {
2167 put_packet(s, "E14");
2168 }
2169 break;
2170 case 'P':
2171 if (!gdb_has_xml)
2172 goto unknown_command;
2173 addr = strtoull(p, (char **)&p, 16);
2174 if (*p == '=')
2175 p++;
2176 reg_size = strlen(p) / 2;
2177 hextomem(mem_buf, p, reg_size);
2178 gdb_write_register(s->g_cpu, mem_buf, addr);
2179 put_packet(s, "OK");
2180 break;
2181 case 'Z':
2182 case 'z':
2183 type = strtoul(p, (char **)&p, 16);
2184 if (*p == ',')
2185 p++;
2186 addr = strtoull(p, (char **)&p, 16);
2187 if (*p == ',')
2188 p++;
2189 len = strtoull(p, (char **)&p, 16);
2190 if (ch == 'Z')
2191 res = gdb_breakpoint_insert(addr, len, type);
2192 else
2193 res = gdb_breakpoint_remove(addr, len, type);
2194 if (res >= 0)
2195 put_packet(s, "OK");
2196 else if (res == -ENOSYS)
2197 put_packet(s, "");
2198 else
2199 put_packet(s, "E22");
2200 break;
2201 case 'H':
2202 type = *p++;
2203 thread = strtoull(p, (char **)&p, 16);
2204 if (thread == -1 || thread == 0) {
2205 put_packet(s, "OK");
2206 break;
2207 }
2208 env = find_cpu(thread);
2209 if (env == NULL) {
2210 put_packet(s, "E22");
2211 break;
2212 }
2213 switch (type) {
2214 case 'c':
2215 s->c_cpu = env;
2216 put_packet(s, "OK");
2217 break;
2218 case 'g':
2219 s->g_cpu = env;
2220 put_packet(s, "OK");
2221 break;
2222 default:
2223 put_packet(s, "E22");
2224 break;
2225 }
2226 break;
2227 case 'T':
2228 thread = strtoull(p, (char **)&p, 16);
2229 env = find_cpu(thread);
2230
2231 if (env != NULL) {
2232 put_packet(s, "OK");
2233 } else {
2234 put_packet(s, "E22");
2235 }
2236 break;
2237 case 'q':
2238 case 'Q':
2239 /* parse any 'q' packets here */
2240 if (!strcmp(p,"qemu.sstepbits")) {
2241 /* Query Breakpoint bit definitions */
2242 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2243 SSTEP_ENABLE,
2244 SSTEP_NOIRQ,
2245 SSTEP_NOTIMER);
2246 put_packet(s, buf);
2247 break;
2248 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2249 /* Display or change the sstep_flags */
2250 p += 10;
2251 if (*p != '=') {
2252 /* Display current setting */
2253 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2254 put_packet(s, buf);
2255 break;
2256 }
2257 p++;
2258 type = strtoul(p, (char **)&p, 16);
2259 sstep_flags = type;
2260 put_packet(s, "OK");
2261 break;
2262 } else if (strcmp(p,"C") == 0) {
2263 /* "Current thread" remains vague in the spec, so always return
2264 * the first CPU (gdb returns the first thread). */
2265 put_packet(s, "QC1");
2266 break;
2267 } else if (strcmp(p,"fThreadInfo") == 0) {
2268 s->query_cpu = first_cpu;
2269 goto report_cpuinfo;
2270 } else if (strcmp(p,"sThreadInfo") == 0) {
2271 report_cpuinfo:
2272 if (s->query_cpu) {
2273 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2274 put_packet(s, buf);
2275 s->query_cpu = s->query_cpu->next_cpu;
2276 } else
2277 put_packet(s, "l");
2278 break;
2279 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2280 thread = strtoull(p+16, (char **)&p, 16);
2281 env = find_cpu(thread);
2282 if (env != NULL) {
2283 cpu_synchronize_state(env);
2284 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2285 "CPU#%d [%s]", env->cpu_index,
2286 env->halted ? "halted " : "running");
2287 memtohex(buf, mem_buf, len);
2288 put_packet(s, buf);
2289 }
2290 break;
2291 }
2292 #ifdef CONFIG_USER_ONLY
2293 else if (strncmp(p, "Offsets", 7) == 0) {
2294 TaskState *ts = s->c_cpu->opaque;
2295
2296 snprintf(buf, sizeof(buf),
2297 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2298 ";Bss=" TARGET_ABI_FMT_lx,
2299 ts->info->code_offset,
2300 ts->info->data_offset,
2301 ts->info->data_offset);
2302 put_packet(s, buf);
2303 break;
2304 }
2305 #else /* !CONFIG_USER_ONLY */
2306 else if (strncmp(p, "Rcmd,", 5) == 0) {
2307 int len = strlen(p + 5);
2308
2309 if ((len % 2) != 0) {
2310 put_packet(s, "E01");
2311 break;
2312 }
2313 hextomem(mem_buf, p + 5, len);
2314 len = len / 2;
2315 mem_buf[len++] = 0;
2316 qemu_chr_be_write(s->mon_chr, mem_buf, len);
2317 put_packet(s, "OK");
2318 break;
2319 }
2320 #endif /* !CONFIG_USER_ONLY */
2321 if (strncmp(p, "Supported", 9) == 0) {
2322 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2323 #ifdef GDB_CORE_XML
2324 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2325 #endif
2326 put_packet(s, buf);
2327 break;
2328 }
2329 #ifdef GDB_CORE_XML
2330 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2331 const char *xml;
2332 target_ulong total_len;
2333
2334 gdb_has_xml = 1;
2335 p += 19;
2336 xml = get_feature_xml(p, &p);
2337 if (!xml) {
2338 snprintf(buf, sizeof(buf), "E00");
2339 put_packet(s, buf);
2340 break;
2341 }
2342
2343 if (*p == ':')
2344 p++;
2345 addr = strtoul(p, (char **)&p, 16);
2346 if (*p == ',')
2347 p++;
2348 len = strtoul(p, (char **)&p, 16);
2349
2350 total_len = strlen(xml);
2351 if (addr > total_len) {
2352 snprintf(buf, sizeof(buf), "E00");
2353 put_packet(s, buf);
2354 break;
2355 }
2356 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2357 len = (MAX_PACKET_LENGTH - 5) / 2;
2358 if (len < total_len - addr) {
2359 buf[0] = 'm';
2360 len = memtox(buf + 1, xml + addr, len);
2361 } else {
2362 buf[0] = 'l';
2363 len = memtox(buf + 1, xml + addr, total_len - addr);
2364 }
2365 put_packet_binary(s, buf, len + 1);
2366 break;
2367 }
2368 #endif
2369 /* Unrecognised 'q' command. */
2370 goto unknown_command;
2371
2372 default:
2373 unknown_command:
2374 /* put empty packet */
2375 buf[0] = '\0';
2376 put_packet(s, buf);
2377 break;
2378 }
2379 return RS_IDLE;
2380 }
2381
2382 void gdb_set_stop_cpu(CPUState *env)
2383 {
2384 gdbserver_state->c_cpu = env;
2385 gdbserver_state->g_cpu = env;
2386 }
2387
2388 #ifndef CONFIG_USER_ONLY
2389 static void gdb_vm_state_change(void *opaque, int running, RunState state)
2390 {
2391 GDBState *s = gdbserver_state;
2392 CPUState *env = s->c_cpu;
2393 char buf[256];
2394 const char *type;
2395 int ret;
2396
2397 if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
2398 return;
2399 }
2400 switch (state) {
2401 case RUN_STATE_DEBUG:
2402 if (env->watchpoint_hit) {
2403 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2404 case BP_MEM_READ:
2405 type = "r";
2406 break;
2407 case BP_MEM_ACCESS:
2408 type = "a";
2409 break;
2410 default:
2411 type = "";
2412 break;
2413 }
2414 snprintf(buf, sizeof(buf),
2415 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2416 GDB_SIGNAL_TRAP, gdb_id(env), type,
2417 env->watchpoint_hit->vaddr);
2418 env->watchpoint_hit = NULL;
2419 goto send_packet;
2420 }
2421 tb_flush(env);
2422 ret = GDB_SIGNAL_TRAP;
2423 break;
2424 case RUN_STATE_PAUSED:
2425 ret = GDB_SIGNAL_INT;
2426 break;
2427 case RUN_STATE_SHUTDOWN:
2428 ret = GDB_SIGNAL_QUIT;
2429 break;
2430 case RUN_STATE_IO_ERROR:
2431 ret = GDB_SIGNAL_IO;
2432 break;
2433 case RUN_STATE_WATCHDOG:
2434 ret = GDB_SIGNAL_ALRM;
2435 break;
2436 case RUN_STATE_INTERNAL_ERROR:
2437 ret = GDB_SIGNAL_ABRT;
2438 break;
2439 case RUN_STATE_SAVE_VM:
2440 case RUN_STATE_RESTORE_VM:
2441 return;
2442 case RUN_STATE_FINISH_MIGRATE:
2443 ret = GDB_SIGNAL_XCPU;
2444 break;
2445 default:
2446 ret = GDB_SIGNAL_UNKNOWN;
2447 break;
2448 }
2449 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2450
2451 send_packet:
2452 put_packet(s, buf);
2453
2454 /* disable single step if it was enabled */
2455 cpu_single_step(env, 0);
2456 }
2457 #endif
2458
2459 /* Send a gdb syscall request.
2460 This accepts limited printf-style format specifiers, specifically:
2461 %x - target_ulong argument printed in hex.
2462 %lx - 64-bit argument printed in hex.
2463 %s - string pointer (target_ulong) and length (int) pair. */
2464 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2465 {
2466 va_list va;
2467 char buf[256];
2468 char *p;
2469 target_ulong addr;
2470 uint64_t i64;
2471 GDBState *s;
2472
2473 s = gdbserver_state;
2474 if (!s)
2475 return;
2476 gdb_current_syscall_cb = cb;
2477 s->state = RS_SYSCALL;
2478 #ifndef CONFIG_USER_ONLY
2479 vm_stop(RUN_STATE_DEBUG);
2480 #endif
2481 s->state = RS_IDLE;
2482 va_start(va, fmt);
2483 p = buf;
2484 *(p++) = 'F';
2485 while (*fmt) {
2486 if (*fmt == '%') {
2487 fmt++;
2488 switch (*fmt++) {
2489 case 'x':
2490 addr = va_arg(va, target_ulong);
2491 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2492 break;
2493 case 'l':
2494 if (*(fmt++) != 'x')
2495 goto bad_format;
2496 i64 = va_arg(va, uint64_t);
2497 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2498 break;
2499 case 's':
2500 addr = va_arg(va, target_ulong);
2501 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2502 addr, va_arg(va, int));
2503 break;
2504 default:
2505 bad_format:
2506 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2507 fmt - 1);
2508 break;
2509 }
2510 } else {
2511 *(p++) = *(fmt++);
2512 }
2513 }
2514 *p = 0;
2515 va_end(va);
2516 put_packet(s, buf);
2517 #ifdef CONFIG_USER_ONLY
2518 gdb_handlesig(s->c_cpu, 0);
2519 #else
2520 cpu_exit(s->c_cpu);
2521 #endif
2522 }
2523
2524 static void gdb_read_byte(GDBState *s, int ch)
2525 {
2526 int i, csum;
2527 uint8_t reply;
2528
2529 #ifndef CONFIG_USER_ONLY
2530 if (s->last_packet_len) {
2531 /* Waiting for a response to the last packet. If we see the start
2532 of a new command then abandon the previous response. */
2533 if (ch == '-') {
2534 #ifdef DEBUG_GDB
2535 printf("Got NACK, retransmitting\n");
2536 #endif
2537 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2538 }
2539 #ifdef DEBUG_GDB
2540 else if (ch == '+')
2541 printf("Got ACK\n");
2542 else
2543 printf("Got '%c' when expecting ACK/NACK\n", ch);
2544 #endif
2545 if (ch == '+' || ch == '$')
2546 s->last_packet_len = 0;
2547 if (ch != '$')
2548 return;
2549 }
2550 if (runstate_is_running()) {
2551 /* when the CPU is running, we cannot do anything except stop
2552 it when receiving a char */
2553 vm_stop(RUN_STATE_PAUSED);
2554 } else
2555 #endif
2556 {
2557 switch(s->state) {
2558 case RS_IDLE:
2559 if (ch == '$') {
2560 s->line_buf_index = 0;
2561 s->state = RS_GETLINE;
2562 }
2563 break;
2564 case RS_GETLINE:
2565 if (ch == '#') {
2566 s->state = RS_CHKSUM1;
2567 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2568 s->state = RS_IDLE;
2569 } else {
2570 s->line_buf[s->line_buf_index++] = ch;
2571 }
2572 break;
2573 case RS_CHKSUM1:
2574 s->line_buf[s->line_buf_index] = '\0';
2575 s->line_csum = fromhex(ch) << 4;
2576 s->state = RS_CHKSUM2;
2577 break;
2578 case RS_CHKSUM2:
2579 s->line_csum |= fromhex(ch);
2580 csum = 0;
2581 for(i = 0; i < s->line_buf_index; i++) {
2582 csum += s->line_buf[i];
2583 }
2584 if (s->line_csum != (csum & 0xff)) {
2585 reply = '-';
2586 put_buffer(s, &reply, 1);
2587 s->state = RS_IDLE;
2588 } else {
2589 reply = '+';
2590 put_buffer(s, &reply, 1);
2591 s->state = gdb_handle_packet(s, s->line_buf);
2592 }
2593 break;
2594 default:
2595 abort();
2596 }
2597 }
2598 }
2599
2600 /* Tell the remote gdb that the process has exited. */
2601 void gdb_exit(CPUState *env, int code)
2602 {
2603 GDBState *s;
2604 char buf[4];
2605
2606 s = gdbserver_state;
2607 if (!s) {
2608 return;
2609 }
2610 #ifdef CONFIG_USER_ONLY
2611 if (gdbserver_fd < 0 || s->fd < 0) {
2612 return;
2613 }
2614 #endif
2615
2616 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2617 put_packet(s, buf);
2618
2619 #ifndef CONFIG_USER_ONLY
2620 if (s->chr) {
2621 qemu_chr_delete(s->chr);
2622 }
2623 #endif
2624 }
2625
2626 #ifdef CONFIG_USER_ONLY
2627 int
2628 gdb_queuesig (void)
2629 {
2630 GDBState *s;
2631
2632 s = gdbserver_state;
2633
2634 if (gdbserver_fd < 0 || s->fd < 0)
2635 return 0;
2636 else
2637 return 1;
2638 }
2639
2640 int
2641 gdb_handlesig (CPUState *env, int sig)
2642 {
2643 GDBState *s;
2644 char buf[256];
2645 int n;
2646
2647 s = gdbserver_state;
2648 if (gdbserver_fd < 0 || s->fd < 0)
2649 return sig;
2650
2651 /* disable single step if it was enabled */
2652 cpu_single_step(env, 0);
2653 tb_flush(env);
2654
2655 if (sig != 0)
2656 {
2657 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2658 put_packet(s, buf);
2659 }
2660 /* put_packet() might have detected that the peer terminated the
2661 connection. */
2662 if (s->fd < 0)
2663 return sig;
2664
2665 sig = 0;
2666 s->state = RS_IDLE;
2667 s->running_state = 0;
2668 while (s->running_state == 0) {
2669 n = read (s->fd, buf, 256);
2670 if (n > 0)
2671 {
2672 int i;
2673
2674 for (i = 0; i < n; i++)
2675 gdb_read_byte (s, buf[i]);
2676 }
2677 else if (n == 0 || errno != EAGAIN)
2678 {
2679 /* XXX: Connection closed. Should probably wait for annother
2680 connection before continuing. */
2681 return sig;
2682 }
2683 }
2684 sig = s->signal;
2685 s->signal = 0;
2686 return sig;
2687 }
2688
2689 /* Tell the remote gdb that the process has exited due to SIG. */
2690 void gdb_signalled(CPUState *env, int sig)
2691 {
2692 GDBState *s;
2693 char buf[4];
2694
2695 s = gdbserver_state;
2696 if (gdbserver_fd < 0 || s->fd < 0)
2697 return;
2698
2699 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2700 put_packet(s, buf);
2701 }
2702
2703 static void gdb_accept(void)
2704 {
2705 GDBState *s;
2706 struct sockaddr_in sockaddr;
2707 socklen_t len;
2708 int val, fd;
2709
2710 for(;;) {
2711 len = sizeof(sockaddr);
2712 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2713 if (fd < 0 && errno != EINTR) {
2714 perror("accept");
2715 return;
2716 } else if (fd >= 0) {
2717 #ifndef _WIN32
2718 fcntl(fd, F_SETFD, FD_CLOEXEC);
2719 #endif
2720 break;
2721 }
2722 }
2723
2724 /* set short latency */
2725 val = 1;
2726 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2727
2728 s = g_malloc0(sizeof(GDBState));
2729 s->c_cpu = first_cpu;
2730 s->g_cpu = first_cpu;
2731 s->fd = fd;
2732 gdb_has_xml = 0;
2733
2734 gdbserver_state = s;
2735
2736 fcntl(fd, F_SETFL, O_NONBLOCK);
2737 }
2738
2739 static int gdbserver_open(int port)
2740 {
2741 struct sockaddr_in sockaddr;
2742 int fd, val, ret;
2743
2744 fd = socket(PF_INET, SOCK_STREAM, 0);
2745 if (fd < 0) {
2746 perror("socket");
2747 return -1;
2748 }
2749 #ifndef _WIN32
2750 fcntl(fd, F_SETFD, FD_CLOEXEC);
2751 #endif
2752
2753 /* allow fast reuse */
2754 val = 1;
2755 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2756
2757 sockaddr.sin_family = AF_INET;
2758 sockaddr.sin_port = htons(port);
2759 sockaddr.sin_addr.s_addr = 0;
2760 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2761 if (ret < 0) {
2762 perror("bind");
2763 return -1;
2764 }
2765 ret = listen(fd, 0);
2766 if (ret < 0) {
2767 perror("listen");
2768 return -1;
2769 }
2770 return fd;
2771 }
2772
2773 int gdbserver_start(int port)
2774 {
2775 gdbserver_fd = gdbserver_open(port);
2776 if (gdbserver_fd < 0)
2777 return -1;
2778 /* accept connections */
2779 gdb_accept();
2780 return 0;
2781 }
2782
2783 /* Disable gdb stub for child processes. */
2784 void gdbserver_fork(CPUState *env)
2785 {
2786 GDBState *s = gdbserver_state;
2787 if (gdbserver_fd < 0 || s->fd < 0)
2788 return;
2789 close(s->fd);
2790 s->fd = -1;
2791 cpu_breakpoint_remove_all(env, BP_GDB);
2792 cpu_watchpoint_remove_all(env, BP_GDB);
2793 }
2794 #else
2795 static int gdb_chr_can_receive(void *opaque)
2796 {
2797 /* We can handle an arbitrarily large amount of data.
2798 Pick the maximum packet size, which is as good as anything. */
2799 return MAX_PACKET_LENGTH;
2800 }
2801
2802 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2803 {
2804 int i;
2805
2806 for (i = 0; i < size; i++) {
2807 gdb_read_byte(gdbserver_state, buf[i]);
2808 }
2809 }
2810
2811 static void gdb_chr_event(void *opaque, int event)
2812 {
2813 switch (event) {
2814 case CHR_EVENT_OPENED:
2815 vm_stop(RUN_STATE_PAUSED);
2816 gdb_has_xml = 0;
2817 break;
2818 default:
2819 break;
2820 }
2821 }
2822
2823 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2824 {
2825 char buf[MAX_PACKET_LENGTH];
2826
2827 buf[0] = 'O';
2828 if (len > (MAX_PACKET_LENGTH/2) - 1)
2829 len = (MAX_PACKET_LENGTH/2) - 1;
2830 memtohex(buf + 1, (uint8_t *)msg, len);
2831 put_packet(s, buf);
2832 }
2833
2834 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2835 {
2836 const char *p = (const char *)buf;
2837 int max_sz;
2838
2839 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2840 for (;;) {
2841 if (len <= max_sz) {
2842 gdb_monitor_output(gdbserver_state, p, len);
2843 break;
2844 }
2845 gdb_monitor_output(gdbserver_state, p, max_sz);
2846 p += max_sz;
2847 len -= max_sz;
2848 }
2849 return len;
2850 }
2851
2852 #ifndef _WIN32
2853 static void gdb_sigterm_handler(int signal)
2854 {
2855 if (runstate_is_running()) {
2856 vm_stop(RUN_STATE_PAUSED);
2857 }
2858 }
2859 #endif
2860
2861 int gdbserver_start(const char *device)
2862 {
2863 GDBState *s;
2864 char gdbstub_device_name[128];
2865 CharDriverState *chr = NULL;
2866 CharDriverState *mon_chr;
2867
2868 if (!device)
2869 return -1;
2870 if (strcmp(device, "none") != 0) {
2871 if (strstart(device, "tcp:", NULL)) {
2872 /* enforce required TCP attributes */
2873 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2874 "%s,nowait,nodelay,server", device);
2875 device = gdbstub_device_name;
2876 }
2877 #ifndef _WIN32
2878 else if (strcmp(device, "stdio") == 0) {
2879 struct sigaction act;
2880
2881 memset(&act, 0, sizeof(act));
2882 act.sa_handler = gdb_sigterm_handler;
2883 sigaction(SIGINT, &act, NULL);
2884 }
2885 #endif
2886 chr = qemu_chr_new("gdb", device, NULL);
2887 if (!chr)
2888 return -1;
2889
2890 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2891 gdb_chr_event, NULL);
2892 }
2893
2894 s = gdbserver_state;
2895 if (!s) {
2896 s = g_malloc0(sizeof(GDBState));
2897 gdbserver_state = s;
2898
2899 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2900
2901 /* Initialize a monitor terminal for gdb */
2902 mon_chr = g_malloc0(sizeof(*mon_chr));
2903 mon_chr->chr_write = gdb_monitor_write;
2904 monitor_init(mon_chr, 0);
2905 } else {
2906 if (s->chr)
2907 qemu_chr_delete(s->chr);
2908 mon_chr = s->mon_chr;
2909 memset(s, 0, sizeof(GDBState));
2910 }
2911 s->c_cpu = first_cpu;
2912 s->g_cpu = first_cpu;
2913 s->chr = chr;
2914 s->state = chr ? RS_IDLE : RS_INACTIVE;
2915 s->mon_chr = mon_chr;
2916
2917 return 0;
2918 }
2919 #endif
QEmu