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ppc: Don't set access_type on all load/stores on hash64
[qemu.git] / target-ppc / translate.c
blob59864356b1def4ea478a8bc6c52166ed0ae4d407
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 bool need_access_type;
199 int mem_idx;
200 int access_type;
201 /* Translation flags */
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 bool sf_mode;
205 bool has_cfar;
206 #endif
207 bool fpu_enabled;
208 bool altivec_enabled;
209 bool vsx_enabled;
210 bool spe_enabled;
211 bool tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
255 {
256 if (ctx->need_access_type && ctx->access_type != access_type) {
257 tcg_gen_movi_i32(cpu_access_type, access_type);
258 ctx->access_type = access_type;
259 }
260 }
261
262 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
263 {
264 if (NARROW_MODE(ctx)) {
265 nip = (uint32_t)nip;
266 }
267 tcg_gen_movi_tl(cpu_nip, nip);
268 }
269
270 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
271 {
272 TCGv_i32 t0, t1;
273
274 /* These are all synchronous exceptions, we set the PC back to
275 * the faulting instruction
276 */
277 if (ctx->exception == POWERPC_EXCP_NONE) {
278 gen_update_nip(ctx, ctx->nip - 4);
279 }
280 t0 = tcg_const_i32(excp);
281 t1 = tcg_const_i32(error);
282 gen_helper_raise_exception_err(cpu_env, t0, t1);
283 tcg_temp_free_i32(t0);
284 tcg_temp_free_i32(t1);
285 ctx->exception = (excp);
286 }
287
288 static void gen_exception(DisasContext *ctx, uint32_t excp)
289 {
290 TCGv_i32 t0;
291
292 /* These are all synchronous exceptions, we set the PC back to
293 * the faulting instruction
294 */
295 if (ctx->exception == POWERPC_EXCP_NONE) {
296 gen_update_nip(ctx, ctx->nip - 4);
297 }
298 t0 = tcg_const_i32(excp);
299 gen_helper_raise_exception(cpu_env, t0);
300 tcg_temp_free_i32(t0);
301 ctx->exception = (excp);
302 }
303
304 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
305 target_ulong nip)
306 {
307 TCGv_i32 t0;
308
309 gen_update_nip(ctx, nip);
310 t0 = tcg_const_i32(excp);
311 gen_helper_raise_exception(cpu_env, t0);
312 tcg_temp_free_i32(t0);
313 ctx->exception = (excp);
314 }
315
316 static void gen_debug_exception(DisasContext *ctx)
317 {
318 TCGv_i32 t0;
319
320 /* These are all synchronous exceptions, we set the PC back to
321 * the faulting instruction
322 */
323 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
324 (ctx->exception != POWERPC_EXCP_SYNC)) {
325 gen_update_nip(ctx, ctx->nip - 4);
326 }
327 t0 = tcg_const_i32(EXCP_DEBUG);
328 gen_helper_raise_exception(cpu_env, t0);
329 tcg_temp_free_i32(t0);
330 }
331
332 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
333 {
334 /* Will be converted to program check if needed */
335 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
336 }
337
338 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
339 {
340 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
341 }
342
343 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
344 {
345 /* Will be converted to program check if needed */
346 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
347 }
348
349 /* Stop translation */
350 static inline void gen_stop_exception(DisasContext *ctx)
351 {
352 gen_update_nip(ctx, ctx->nip);
353 ctx->exception = POWERPC_EXCP_STOP;
354 }
355
356 #ifndef CONFIG_USER_ONLY
357 /* No need to update nip here, as execution flow will change */
358 static inline void gen_sync_exception(DisasContext *ctx)
359 {
360 ctx->exception = POWERPC_EXCP_SYNC;
361 }
362 #endif
363
364 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
365 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
366
367 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
368 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
369
370 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
371 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
372
373 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
374 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
375
376 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
377 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
378
379 typedef struct opcode_t {
380 unsigned char opc1, opc2, opc3, opc4;
381 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
382 unsigned char pad[4];
383 #endif
384 opc_handler_t handler;
385 const char *oname;
386 } opcode_t;
387
388 /* Helpers for priv. check */
389 #define GEN_PRIV \
390 do { \
391 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
392 } while (0)
393
394 #if defined(CONFIG_USER_ONLY)
395 #define CHK_HV GEN_PRIV
396 #define CHK_SV GEN_PRIV
397 #define CHK_HVRM GEN_PRIV
398 #else
399 #define CHK_HV \
400 do { \
401 if (unlikely(ctx->pr || !ctx->hv)) { \
402 GEN_PRIV; \
403 } \
404 } while (0)
405 #define CHK_SV \
406 do { \
407 if (unlikely(ctx->pr)) { \
408 GEN_PRIV; \
409 } \
410 } while (0)
411 #define CHK_HVRM \
412 do { \
413 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
414 GEN_PRIV; \
415 } \
416 } while (0)
417 #endif
418
419 #define CHK_NONE
420
421
422 /*****************************************************************************/
423 /*** Instruction decoding ***/
424 #define EXTRACT_HELPER(name, shift, nb) \
425 static inline uint32_t name(uint32_t opcode) \
426 { \
427 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
428 }
429
430 #define EXTRACT_SHELPER(name, shift, nb) \
431 static inline int32_t name(uint32_t opcode) \
432 { \
433 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
434 }
435
436 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
437 static inline uint32_t name(uint32_t opcode) \
438 { \
439 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
440 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
441 }
442
443 #define EXTRACT_HELPER_DXFORM(name, \
444 d0_bits, shift_op_d0, shift_d0, \
445 d1_bits, shift_op_d1, shift_d1, \
446 d2_bits, shift_op_d2, shift_d2) \
447 static inline int16_t name(uint32_t opcode) \
448 { \
449 return \
450 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
451 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
452 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
453 }
454
455
456 /* Opcode part 1 */
457 EXTRACT_HELPER(opc1, 26, 6);
458 /* Opcode part 2 */
459 EXTRACT_HELPER(opc2, 1, 5);
460 /* Opcode part 3 */
461 EXTRACT_HELPER(opc3, 6, 5);
462 /* Opcode part 4 */
463 EXTRACT_HELPER(opc4, 16, 5);
464 /* Update Cr0 flags */
465 EXTRACT_HELPER(Rc, 0, 1);
466 /* Update Cr6 flags (Altivec) */
467 EXTRACT_HELPER(Rc21, 10, 1);
468 /* Destination */
469 EXTRACT_HELPER(rD, 21, 5);
470 /* Source */
471 EXTRACT_HELPER(rS, 21, 5);
472 /* First operand */
473 EXTRACT_HELPER(rA, 16, 5);
474 /* Second operand */
475 EXTRACT_HELPER(rB, 11, 5);
476 /* Third operand */
477 EXTRACT_HELPER(rC, 6, 5);
478 /*** Get CRn ***/
479 EXTRACT_HELPER(crfD, 23, 3);
480 EXTRACT_HELPER(crfS, 18, 3);
481 EXTRACT_HELPER(crbD, 21, 5);
482 EXTRACT_HELPER(crbA, 16, 5);
483 EXTRACT_HELPER(crbB, 11, 5);
484 /* SPR / TBL */
485 EXTRACT_HELPER(_SPR, 11, 10);
486 static inline uint32_t SPR(uint32_t opcode)
487 {
488 uint32_t sprn = _SPR(opcode);
489
490 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
491 }
492 /*** Get constants ***/
493 /* 16 bits signed immediate value */
494 EXTRACT_SHELPER(SIMM, 0, 16);
495 /* 16 bits unsigned immediate value */
496 EXTRACT_HELPER(UIMM, 0, 16);
497 /* 5 bits signed immediate value */
498 EXTRACT_HELPER(SIMM5, 16, 5);
499 /* 5 bits signed immediate value */
500 EXTRACT_HELPER(UIMM5, 16, 5);
501 /* Bit count */
502 EXTRACT_HELPER(NB, 11, 5);
503 /* Shift count */
504 EXTRACT_HELPER(SH, 11, 5);
505 /* Vector shift count */
506 EXTRACT_HELPER(VSH, 6, 4);
507 /* Mask start */
508 EXTRACT_HELPER(MB, 6, 5);
509 /* Mask end */
510 EXTRACT_HELPER(ME, 1, 5);
511 /* Trap operand */
512 EXTRACT_HELPER(TO, 21, 5);
513
514 EXTRACT_HELPER(CRM, 12, 8);
515
516 #ifndef CONFIG_USER_ONLY
517 EXTRACT_HELPER(SR, 16, 4);
518 #endif
519
520 /* mtfsf/mtfsfi */
521 EXTRACT_HELPER(FPBF, 23, 3);
522 EXTRACT_HELPER(FPIMM, 12, 4);
523 EXTRACT_HELPER(FPL, 25, 1);
524 EXTRACT_HELPER(FPFLM, 17, 8);
525 EXTRACT_HELPER(FPW, 16, 1);
526
527 /* addpcis */
528 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
529
530 /*** Jump target decoding ***/
531 /* Immediate address */
532 static inline target_ulong LI(uint32_t opcode)
533 {
534 return (opcode >> 0) & 0x03FFFFFC;
535 }
536
537 static inline uint32_t BD(uint32_t opcode)
538 {
539 return (opcode >> 0) & 0xFFFC;
540 }
541
542 EXTRACT_HELPER(BO, 21, 5);
543 EXTRACT_HELPER(BI, 16, 5);
544 /* Absolute/relative address */
545 EXTRACT_HELPER(AA, 1, 1);
546 /* Link */
547 EXTRACT_HELPER(LK, 0, 1);
548
549 /* DFP Z22-form */
550 EXTRACT_HELPER(DCM, 10, 6)
551
552 /* DFP Z23-form */
553 EXTRACT_HELPER(RMC, 9, 2)
554
555 /* Create a mask between <start> and <end> bits */
556 static inline target_ulong MASK(uint32_t start, uint32_t end)
557 {
558 target_ulong ret;
559
560 #if defined(TARGET_PPC64)
561 if (likely(start == 0)) {
562 ret = UINT64_MAX << (63 - end);
563 } else if (likely(end == 63)) {
564 ret = UINT64_MAX >> start;
565 }
566 #else
567 if (likely(start == 0)) {
568 ret = UINT32_MAX << (31 - end);
569 } else if (likely(end == 31)) {
570 ret = UINT32_MAX >> start;
571 }
572 #endif
573 else {
574 ret = (((target_ulong)(-1ULL)) >> (start)) ^
575 (((target_ulong)(-1ULL) >> (end)) >> 1);
576 if (unlikely(start > end))
577 return ~ret;
578 }
579
580 return ret;
581 }
582
583 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
585 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
586 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
587 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
588 EXTRACT_HELPER(DM, 8, 2);
589 EXTRACT_HELPER(UIM, 16, 2);
590 EXTRACT_HELPER(SHW, 8, 2);
591 EXTRACT_HELPER(SP, 19, 2);
592 /*****************************************************************************/
593 /* PowerPC instructions table */
594
595 #if defined(DO_PPC_STATISTICS)
596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .opc4 = 0xff, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 .oname = stringify(name), \
608 }, \
609 .oname = stringify(name), \
610 }
611 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
612 { \
613 .opc1 = op1, \
614 .opc2 = op2, \
615 .opc3 = op3, \
616 .opc4 = 0xff, \
617 .handler = { \
618 .inval1 = invl1, \
619 .inval2 = invl2, \
620 .type = _typ, \
621 .type2 = _typ2, \
622 .handler = &gen_##name, \
623 .oname = stringify(name), \
624 }, \
625 .oname = stringify(name), \
626 }
627 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
628 { \
629 .opc1 = op1, \
630 .opc2 = op2, \
631 .opc3 = op3, \
632 .opc4 = 0xff, \
633 .handler = { \
634 .inval1 = invl, \
635 .type = _typ, \
636 .type2 = _typ2, \
637 .handler = &gen_##name, \
638 .oname = onam, \
639 }, \
640 .oname = onam, \
641 }
642 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
643 { \
644 .opc1 = op1, \
645 .opc2 = op2, \
646 .opc3 = op3, \
647 .opc4 = op4, \
648 .handler = { \
649 .inval1 = invl, \
650 .type = _typ, \
651 .type2 = _typ2, \
652 .handler = &gen_##name, \
653 .oname = stringify(name), \
654 }, \
655 .oname = stringify(name), \
656 }
657 #else
658 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
659 { \
660 .opc1 = op1, \
661 .opc2 = op2, \
662 .opc3 = op3, \
663 .opc4 = 0xff, \
664 .handler = { \
665 .inval1 = invl, \
666 .type = _typ, \
667 .type2 = _typ2, \
668 .handler = &gen_##name, \
669 }, \
670 .oname = stringify(name), \
671 }
672 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
673 { \
674 .opc1 = op1, \
675 .opc2 = op2, \
676 .opc3 = op3, \
677 .opc4 = 0xff, \
678 .handler = { \
679 .inval1 = invl1, \
680 .inval2 = invl2, \
681 .type = _typ, \
682 .type2 = _typ2, \
683 .handler = &gen_##name, \
684 }, \
685 .oname = stringify(name), \
686 }
687 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
688 { \
689 .opc1 = op1, \
690 .opc2 = op2, \
691 .opc3 = op3, \
692 .opc4 = 0xff, \
693 .handler = { \
694 .inval1 = invl, \
695 .type = _typ, \
696 .type2 = _typ2, \
697 .handler = &gen_##name, \
698 }, \
699 .oname = onam, \
700 }
701 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
702 { \
703 .opc1 = op1, \
704 .opc2 = op2, \
705 .opc3 = op3, \
706 .opc4 = op4, \
707 .handler = { \
708 .inval1 = invl, \
709 .type = _typ, \
710 .type2 = _typ2, \
711 .handler = &gen_##name, \
712 }, \
713 .oname = stringify(name), \
714 }
715 #endif
716
717 /* SPR load/store helpers */
718 static inline void gen_load_spr(TCGv t, int reg)
719 {
720 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
721 }
722
723 static inline void gen_store_spr(int reg, TCGv t)
724 {
725 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
726 }
727
728 /* Invalid instruction */
729 static void gen_invalid(DisasContext *ctx)
730 {
731 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
732 }
733
734 static opc_handler_t invalid_handler = {
735 .inval1 = 0xFFFFFFFF,
736 .inval2 = 0xFFFFFFFF,
737 .type = PPC_NONE,
738 .type2 = PPC_NONE,
739 .handler = gen_invalid,
740 };
741
742 /*** Integer comparison ***/
743
744 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
745 {
746 TCGv t0 = tcg_temp_new();
747 TCGv_i32 t1 = tcg_temp_new_i32();
748
749 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
750
751 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
752 tcg_gen_trunc_tl_i32(t1, t0);
753 tcg_gen_shli_i32(t1, t1, CRF_LT);
754 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
755
756 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
757 tcg_gen_trunc_tl_i32(t1, t0);
758 tcg_gen_shli_i32(t1, t1, CRF_GT);
759 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
760
761 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
762 tcg_gen_trunc_tl_i32(t1, t0);
763 tcg_gen_shli_i32(t1, t1, CRF_EQ);
764 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
765
766 tcg_temp_free(t0);
767 tcg_temp_free_i32(t1);
768 }
769
770 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
771 {
772 TCGv t0 = tcg_const_tl(arg1);
773 gen_op_cmp(arg0, t0, s, crf);
774 tcg_temp_free(t0);
775 }
776
777 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
778 {
779 TCGv t0, t1;
780 t0 = tcg_temp_new();
781 t1 = tcg_temp_new();
782 if (s) {
783 tcg_gen_ext32s_tl(t0, arg0);
784 tcg_gen_ext32s_tl(t1, arg1);
785 } else {
786 tcg_gen_ext32u_tl(t0, arg0);
787 tcg_gen_ext32u_tl(t1, arg1);
788 }
789 gen_op_cmp(t0, t1, s, crf);
790 tcg_temp_free(t1);
791 tcg_temp_free(t0);
792 }
793
794 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
795 {
796 TCGv t0 = tcg_const_tl(arg1);
797 gen_op_cmp32(arg0, t0, s, crf);
798 tcg_temp_free(t0);
799 }
800
801 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
802 {
803 if (NARROW_MODE(ctx)) {
804 gen_op_cmpi32(reg, 0, 1, 0);
805 } else {
806 gen_op_cmpi(reg, 0, 1, 0);
807 }
808 }
809
810 /* cmp */
811 static void gen_cmp(DisasContext *ctx)
812 {
813 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
814 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
815 1, crfD(ctx->opcode));
816 } else {
817 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
818 1, crfD(ctx->opcode));
819 }
820 }
821
822 /* cmpi */
823 static void gen_cmpi(DisasContext *ctx)
824 {
825 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
826 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
827 1, crfD(ctx->opcode));
828 } else {
829 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
830 1, crfD(ctx->opcode));
831 }
832 }
833
834 /* cmpl */
835 static void gen_cmpl(DisasContext *ctx)
836 {
837 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
838 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
839 0, crfD(ctx->opcode));
840 } else {
841 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
842 0, crfD(ctx->opcode));
843 }
844 }
845
846 /* cmpli */
847 static void gen_cmpli(DisasContext *ctx)
848 {
849 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
850 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
851 0, crfD(ctx->opcode));
852 } else {
853 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
854 0, crfD(ctx->opcode));
855 }
856 }
857
858 /* cmprb - range comparison: isupper, isaplha, islower*/
859 static void gen_cmprb(DisasContext *ctx)
860 {
861 TCGv_i32 src1 = tcg_temp_new_i32();
862 TCGv_i32 src2 = tcg_temp_new_i32();
863 TCGv_i32 src2lo = tcg_temp_new_i32();
864 TCGv_i32 src2hi = tcg_temp_new_i32();
865 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
866
867 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
868 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
869
870 tcg_gen_andi_i32(src1, src1, 0xFF);
871 tcg_gen_ext8u_i32(src2lo, src2);
872 tcg_gen_shri_i32(src2, src2, 8);
873 tcg_gen_ext8u_i32(src2hi, src2);
874
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
876 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
877 tcg_gen_and_i32(crf, src2lo, src2hi);
878
879 if (ctx->opcode & 0x00200000) {
880 tcg_gen_shri_i32(src2, src2, 8);
881 tcg_gen_ext8u_i32(src2lo, src2);
882 tcg_gen_shri_i32(src2, src2, 8);
883 tcg_gen_ext8u_i32(src2hi, src2);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
885 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
886 tcg_gen_and_i32(src2lo, src2lo, src2hi);
887 tcg_gen_or_i32(crf, crf, src2lo);
888 }
889 tcg_gen_shli_i32(crf, crf, CRF_GT);
890 tcg_temp_free_i32(src1);
891 tcg_temp_free_i32(src2);
892 tcg_temp_free_i32(src2lo);
893 tcg_temp_free_i32(src2hi);
894 }
895
896 #if defined(TARGET_PPC64)
897 /* cmpeqb */
898 static void gen_cmpeqb(DisasContext *ctx)
899 {
900 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
901 cpu_gpr[rB(ctx->opcode)]);
902 }
903 #endif
904
905 /* isel (PowerPC 2.03 specification) */
906 static void gen_isel(DisasContext *ctx)
907 {
908 uint32_t bi = rC(ctx->opcode);
909 uint32_t mask = 0x08 >> (bi & 0x03);
910 TCGv t0 = tcg_temp_new();
911 TCGv zr;
912
913 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
914 tcg_gen_andi_tl(t0, t0, mask);
915
916 zr = tcg_const_tl(0);
917 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
918 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
919 cpu_gpr[rB(ctx->opcode)]);
920 tcg_temp_free(zr);
921 tcg_temp_free(t0);
922 }
923
924 /* cmpb: PowerPC 2.05 specification */
925 static void gen_cmpb(DisasContext *ctx)
926 {
927 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
928 cpu_gpr[rB(ctx->opcode)]);
929 }
930
931 /*** Integer arithmetic ***/
932
933 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
934 TCGv arg1, TCGv arg2, int sub)
935 {
936 TCGv t0 = tcg_temp_new();
937
938 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
939 tcg_gen_xor_tl(t0, arg1, arg2);
940 if (sub) {
941 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
942 } else {
943 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
944 }
945 tcg_temp_free(t0);
946 if (NARROW_MODE(ctx)) {
947 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
948 }
949 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
950 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
951 }
952
953 /* Common add function */
954 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
955 TCGv arg2, bool add_ca, bool compute_ca,
956 bool compute_ov, bool compute_rc0)
957 {
958 TCGv t0 = ret;
959
960 if (compute_ca || compute_ov) {
961 t0 = tcg_temp_new();
962 }
963
964 if (compute_ca) {
965 if (NARROW_MODE(ctx)) {
966 /* Caution: a non-obvious corner case of the spec is that we
967 must produce the *entire* 64-bit addition, but produce the
968 carry into bit 32. */
969 TCGv t1 = tcg_temp_new();
970 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
971 tcg_gen_add_tl(t0, arg1, arg2);
972 if (add_ca) {
973 tcg_gen_add_tl(t0, t0, cpu_ca);
974 }
975 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
976 tcg_temp_free(t1);
977 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
978 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
979 } else {
980 TCGv zero = tcg_const_tl(0);
981 if (add_ca) {
982 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
983 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
984 } else {
985 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
986 }
987 tcg_temp_free(zero);
988 }
989 } else {
990 tcg_gen_add_tl(t0, arg1, arg2);
991 if (add_ca) {
992 tcg_gen_add_tl(t0, t0, cpu_ca);
993 }
994 }
995
996 if (compute_ov) {
997 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
998 }
999 if (unlikely(compute_rc0)) {
1000 gen_set_Rc0(ctx, t0);
1001 }
1002
1003 if (!TCGV_EQUAL(t0, ret)) {
1004 tcg_gen_mov_tl(ret, t0);
1005 tcg_temp_free(t0);
1006 }
1007 }
1008 /* Add functions with two operands */
1009 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1010 static void glue(gen_, name)(DisasContext *ctx) \
1011 { \
1012 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1013 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1014 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1015 }
1016 /* Add functions with one operand and one immediate */
1017 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1018 add_ca, compute_ca, compute_ov) \
1019 static void glue(gen_, name)(DisasContext *ctx) \
1020 { \
1021 TCGv t0 = tcg_const_tl(const_val); \
1022 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1023 cpu_gpr[rA(ctx->opcode)], t0, \
1024 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1025 tcg_temp_free(t0); \
1026 }
1027
1028 /* add add. addo addo. */
1029 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1030 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1031 /* addc addc. addco addco. */
1032 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1033 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1034 /* adde adde. addeo addeo. */
1035 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1036 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1037 /* addme addme. addmeo addmeo. */
1038 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1039 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1040 /* addze addze. addzeo addzeo.*/
1041 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1042 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1043 /* addi */
1044 static void gen_addi(DisasContext *ctx)
1045 {
1046 target_long simm = SIMM(ctx->opcode);
1047
1048 if (rA(ctx->opcode) == 0) {
1049 /* li case */
1050 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1051 } else {
1052 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1053 cpu_gpr[rA(ctx->opcode)], simm);
1054 }
1055 }
1056 /* addic addic.*/
1057 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1058 {
1059 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1060 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1061 c, 0, 1, 0, compute_rc0);
1062 tcg_temp_free(c);
1063 }
1064
1065 static void gen_addic(DisasContext *ctx)
1066 {
1067 gen_op_addic(ctx, 0);
1068 }
1069
1070 static void gen_addic_(DisasContext *ctx)
1071 {
1072 gen_op_addic(ctx, 1);
1073 }
1074
1075 /* addis */
1076 static void gen_addis(DisasContext *ctx)
1077 {
1078 target_long simm = SIMM(ctx->opcode);
1079
1080 if (rA(ctx->opcode) == 0) {
1081 /* lis case */
1082 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1083 } else {
1084 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1085 cpu_gpr[rA(ctx->opcode)], simm << 16);
1086 }
1087 }
1088
1089 /* addpcis */
1090 static void gen_addpcis(DisasContext *ctx)
1091 {
1092 target_long d = DX(ctx->opcode);
1093
1094 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1095 }
1096
1097 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1098 TCGv arg2, int sign, int compute_ov)
1099 {
1100 TCGLabel *l1 = gen_new_label();
1101 TCGLabel *l2 = gen_new_label();
1102 TCGv_i32 t0 = tcg_temp_local_new_i32();
1103 TCGv_i32 t1 = tcg_temp_local_new_i32();
1104
1105 tcg_gen_trunc_tl_i32(t0, arg1);
1106 tcg_gen_trunc_tl_i32(t1, arg2);
1107 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1108 if (sign) {
1109 TCGLabel *l3 = gen_new_label();
1110 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1111 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1112 gen_set_label(l3);
1113 tcg_gen_div_i32(t0, t0, t1);
1114 } else {
1115 tcg_gen_divu_i32(t0, t0, t1);
1116 }
1117 if (compute_ov) {
1118 tcg_gen_movi_tl(cpu_ov, 0);
1119 }
1120 tcg_gen_br(l2);
1121 gen_set_label(l1);
1122 if (sign) {
1123 tcg_gen_sari_i32(t0, t0, 31);
1124 } else {
1125 tcg_gen_movi_i32(t0, 0);
1126 }
1127 if (compute_ov) {
1128 tcg_gen_movi_tl(cpu_ov, 1);
1129 tcg_gen_movi_tl(cpu_so, 1);
1130 }
1131 gen_set_label(l2);
1132 tcg_gen_extu_i32_tl(ret, t0);
1133 tcg_temp_free_i32(t0);
1134 tcg_temp_free_i32(t1);
1135 if (unlikely(Rc(ctx->opcode) != 0))
1136 gen_set_Rc0(ctx, ret);
1137 }
1138 /* Div functions */
1139 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1140 static void glue(gen_, name)(DisasContext *ctx) \
1141 { \
1142 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1143 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1144 sign, compute_ov); \
1145 }
1146 /* divwu divwu. divwuo divwuo. */
1147 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1148 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1149 /* divw divw. divwo divwo. */
1150 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1151 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1152
1153 /* div[wd]eu[o][.] */
1154 #define GEN_DIVE(name, hlpr, compute_ov) \
1155 static void gen_##name(DisasContext *ctx) \
1156 { \
1157 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1158 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1159 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1160 tcg_temp_free_i32(t0); \
1161 if (unlikely(Rc(ctx->opcode) != 0)) { \
1162 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1163 } \
1164 }
1165
1166 GEN_DIVE(divweu, divweu, 0);
1167 GEN_DIVE(divweuo, divweu, 1);
1168 GEN_DIVE(divwe, divwe, 0);
1169 GEN_DIVE(divweo, divwe, 1);
1170
1171 #if defined(TARGET_PPC64)
1172 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1173 TCGv arg2, int sign, int compute_ov)
1174 {
1175 TCGLabel *l1 = gen_new_label();
1176 TCGLabel *l2 = gen_new_label();
1177
1178 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1179 if (sign) {
1180 TCGLabel *l3 = gen_new_label();
1181 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1182 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1183 gen_set_label(l3);
1184 tcg_gen_div_i64(ret, arg1, arg2);
1185 } else {
1186 tcg_gen_divu_i64(ret, arg1, arg2);
1187 }
1188 if (compute_ov) {
1189 tcg_gen_movi_tl(cpu_ov, 0);
1190 }
1191 tcg_gen_br(l2);
1192 gen_set_label(l1);
1193 if (sign) {
1194 tcg_gen_sari_i64(ret, arg1, 63);
1195 } else {
1196 tcg_gen_movi_i64(ret, 0);
1197 }
1198 if (compute_ov) {
1199 tcg_gen_movi_tl(cpu_ov, 1);
1200 tcg_gen_movi_tl(cpu_so, 1);
1201 }
1202 gen_set_label(l2);
1203 if (unlikely(Rc(ctx->opcode) != 0))
1204 gen_set_Rc0(ctx, ret);
1205 }
1206 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1207 static void glue(gen_, name)(DisasContext *ctx) \
1208 { \
1209 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1210 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1211 sign, compute_ov); \
1212 }
1213 /* divwu divwu. divwuo divwuo. */
1214 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1215 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1216 /* divw divw. divwo divwo. */
1217 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1218 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1219
1220 GEN_DIVE(divdeu, divdeu, 0);
1221 GEN_DIVE(divdeuo, divdeu, 1);
1222 GEN_DIVE(divde, divde, 0);
1223 GEN_DIVE(divdeo, divde, 1);
1224 #endif
1225
1226 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1227 TCGv arg2, int sign)
1228 {
1229 TCGv_i32 t0 = tcg_temp_new_i32();
1230 TCGv_i32 t1 = tcg_temp_new_i32();
1231
1232 tcg_gen_trunc_tl_i32(t0, arg1);
1233 tcg_gen_trunc_tl_i32(t1, arg2);
1234 if (sign) {
1235 TCGv_i32 t2 = tcg_temp_new_i32();
1236 TCGv_i32 t3 = tcg_temp_new_i32();
1237 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1238 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1239 tcg_gen_and_i32(t2, t2, t3);
1240 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1241 tcg_gen_or_i32(t2, t2, t3);
1242 tcg_gen_movi_i32(t3, 0);
1243 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1244 tcg_gen_rem_i32(t3, t0, t1);
1245 tcg_gen_ext_i32_tl(ret, t3);
1246 tcg_temp_free_i32(t2);
1247 tcg_temp_free_i32(t3);
1248 } else {
1249 TCGv_i32 t2 = tcg_const_i32(1);
1250 TCGv_i32 t3 = tcg_const_i32(0);
1251 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1252 tcg_gen_remu_i32(t3, t0, t1);
1253 tcg_gen_extu_i32_tl(ret, t3);
1254 tcg_temp_free_i32(t2);
1255 tcg_temp_free_i32(t3);
1256 }
1257 tcg_temp_free_i32(t0);
1258 tcg_temp_free_i32(t1);
1259 }
1260
1261 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1262 static void glue(gen_, name)(DisasContext *ctx) \
1263 { \
1264 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1265 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1266 sign); \
1267 }
1268
1269 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1270 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1271
1272 #if defined(TARGET_PPC64)
1273 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1274 TCGv arg2, int sign)
1275 {
1276 TCGv_i64 t0 = tcg_temp_new_i64();
1277 TCGv_i64 t1 = tcg_temp_new_i64();
1278
1279 tcg_gen_mov_i64(t0, arg1);
1280 tcg_gen_mov_i64(t1, arg2);
1281 if (sign) {
1282 TCGv_i64 t2 = tcg_temp_new_i64();
1283 TCGv_i64 t3 = tcg_temp_new_i64();
1284 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1285 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1286 tcg_gen_and_i64(t2, t2, t3);
1287 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1288 tcg_gen_or_i64(t2, t2, t3);
1289 tcg_gen_movi_i64(t3, 0);
1290 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1291 tcg_gen_rem_i64(ret, t0, t1);
1292 tcg_temp_free_i64(t2);
1293 tcg_temp_free_i64(t3);
1294 } else {
1295 TCGv_i64 t2 = tcg_const_i64(1);
1296 TCGv_i64 t3 = tcg_const_i64(0);
1297 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1298 tcg_gen_remu_i64(ret, t0, t1);
1299 tcg_temp_free_i64(t2);
1300 tcg_temp_free_i64(t3);
1301 }
1302 tcg_temp_free_i64(t0);
1303 tcg_temp_free_i64(t1);
1304 }
1305
1306 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1310 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1311 sign); \
1312 }
1313
1314 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1315 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1316 #endif
1317
1318 /* mulhw mulhw. */
1319 static void gen_mulhw(DisasContext *ctx)
1320 {
1321 TCGv_i32 t0 = tcg_temp_new_i32();
1322 TCGv_i32 t1 = tcg_temp_new_i32();
1323
1324 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1325 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1326 tcg_gen_muls2_i32(t0, t1, t0, t1);
1327 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1328 tcg_temp_free_i32(t0);
1329 tcg_temp_free_i32(t1);
1330 if (unlikely(Rc(ctx->opcode) != 0))
1331 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1332 }
1333
1334 /* mulhwu mulhwu. */
1335 static void gen_mulhwu(DisasContext *ctx)
1336 {
1337 TCGv_i32 t0 = tcg_temp_new_i32();
1338 TCGv_i32 t1 = tcg_temp_new_i32();
1339
1340 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1341 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1342 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1343 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1344 tcg_temp_free_i32(t0);
1345 tcg_temp_free_i32(t1);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1348 }
1349
1350 /* mullw mullw. */
1351 static void gen_mullw(DisasContext *ctx)
1352 {
1353 #if defined(TARGET_PPC64)
1354 TCGv_i64 t0, t1;
1355 t0 = tcg_temp_new_i64();
1356 t1 = tcg_temp_new_i64();
1357 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1358 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1359 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1360 tcg_temp_free(t0);
1361 tcg_temp_free(t1);
1362 #else
1363 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1364 cpu_gpr[rB(ctx->opcode)]);
1365 #endif
1366 if (unlikely(Rc(ctx->opcode) != 0))
1367 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1368 }
1369
1370 /* mullwo mullwo. */
1371 static void gen_mullwo(DisasContext *ctx)
1372 {
1373 TCGv_i32 t0 = tcg_temp_new_i32();
1374 TCGv_i32 t1 = tcg_temp_new_i32();
1375
1376 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1377 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1378 tcg_gen_muls2_i32(t0, t1, t0, t1);
1379 #if defined(TARGET_PPC64)
1380 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1381 #else
1382 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1383 #endif
1384
1385 tcg_gen_sari_i32(t0, t0, 31);
1386 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1387 tcg_gen_extu_i32_tl(cpu_ov, t0);
1388 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1389
1390 tcg_temp_free_i32(t0);
1391 tcg_temp_free_i32(t1);
1392 if (unlikely(Rc(ctx->opcode) != 0))
1393 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1394 }
1395
1396 /* mulli */
1397 static void gen_mulli(DisasContext *ctx)
1398 {
1399 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1400 SIMM(ctx->opcode));
1401 }
1402
1403 #if defined(TARGET_PPC64)
1404 /* mulhd mulhd. */
1405 static void gen_mulhd(DisasContext *ctx)
1406 {
1407 TCGv lo = tcg_temp_new();
1408 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1410 tcg_temp_free(lo);
1411 if (unlikely(Rc(ctx->opcode) != 0)) {
1412 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1413 }
1414 }
1415
1416 /* mulhdu mulhdu. */
1417 static void gen_mulhdu(DisasContext *ctx)
1418 {
1419 TCGv lo = tcg_temp_new();
1420 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1421 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1422 tcg_temp_free(lo);
1423 if (unlikely(Rc(ctx->opcode) != 0)) {
1424 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1425 }
1426 }
1427
1428 /* mulld mulld. */
1429 static void gen_mulld(DisasContext *ctx)
1430 {
1431 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1432 cpu_gpr[rB(ctx->opcode)]);
1433 if (unlikely(Rc(ctx->opcode) != 0))
1434 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1435 }
1436
1437 /* mulldo mulldo. */
1438 static void gen_mulldo(DisasContext *ctx)
1439 {
1440 TCGv_i64 t0 = tcg_temp_new_i64();
1441 TCGv_i64 t1 = tcg_temp_new_i64();
1442
1443 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1444 cpu_gpr[rB(ctx->opcode)]);
1445 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1446
1447 tcg_gen_sari_i64(t0, t0, 63);
1448 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1449 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1450
1451 tcg_temp_free_i64(t0);
1452 tcg_temp_free_i64(t1);
1453
1454 if (unlikely(Rc(ctx->opcode) != 0)) {
1455 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1456 }
1457 }
1458 #endif
1459
1460 /* Common subf function */
1461 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1462 TCGv arg2, bool add_ca, bool compute_ca,
1463 bool compute_ov, bool compute_rc0)
1464 {
1465 TCGv t0 = ret;
1466
1467 if (compute_ca || compute_ov) {
1468 t0 = tcg_temp_new();
1469 }
1470
1471 if (compute_ca) {
1472 /* dest = ~arg1 + arg2 [+ ca]. */
1473 if (NARROW_MODE(ctx)) {
1474 /* Caution: a non-obvious corner case of the spec is that we
1475 must produce the *entire* 64-bit addition, but produce the
1476 carry into bit 32. */
1477 TCGv inv1 = tcg_temp_new();
1478 TCGv t1 = tcg_temp_new();
1479 tcg_gen_not_tl(inv1, arg1);
1480 if (add_ca) {
1481 tcg_gen_add_tl(t0, arg2, cpu_ca);
1482 } else {
1483 tcg_gen_addi_tl(t0, arg2, 1);
1484 }
1485 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1486 tcg_gen_add_tl(t0, t0, inv1);
1487 tcg_temp_free(inv1);
1488 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1489 tcg_temp_free(t1);
1490 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1491 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1492 } else if (add_ca) {
1493 TCGv zero, inv1 = tcg_temp_new();
1494 tcg_gen_not_tl(inv1, arg1);
1495 zero = tcg_const_tl(0);
1496 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1497 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1498 tcg_temp_free(zero);
1499 tcg_temp_free(inv1);
1500 } else {
1501 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1502 tcg_gen_sub_tl(t0, arg2, arg1);
1503 }
1504 } else if (add_ca) {
1505 /* Since we're ignoring carry-out, we can simplify the
1506 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1507 tcg_gen_sub_tl(t0, arg2, arg1);
1508 tcg_gen_add_tl(t0, t0, cpu_ca);
1509 tcg_gen_subi_tl(t0, t0, 1);
1510 } else {
1511 tcg_gen_sub_tl(t0, arg2, arg1);
1512 }
1513
1514 if (compute_ov) {
1515 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1516 }
1517 if (unlikely(compute_rc0)) {
1518 gen_set_Rc0(ctx, t0);
1519 }
1520
1521 if (!TCGV_EQUAL(t0, ret)) {
1522 tcg_gen_mov_tl(ret, t0);
1523 tcg_temp_free(t0);
1524 }
1525 }
1526 /* Sub functions with Two operands functions */
1527 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1528 static void glue(gen_, name)(DisasContext *ctx) \
1529 { \
1530 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1531 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1532 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1533 }
1534 /* Sub functions with one operand and one immediate */
1535 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1536 add_ca, compute_ca, compute_ov) \
1537 static void glue(gen_, name)(DisasContext *ctx) \
1538 { \
1539 TCGv t0 = tcg_const_tl(const_val); \
1540 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1541 cpu_gpr[rA(ctx->opcode)], t0, \
1542 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1543 tcg_temp_free(t0); \
1544 }
1545 /* subf subf. subfo subfo. */
1546 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1547 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1548 /* subfc subfc. subfco subfco. */
1549 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1550 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1551 /* subfe subfe. subfeo subfo. */
1552 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1553 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1554 /* subfme subfme. subfmeo subfmeo. */
1555 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1556 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1557 /* subfze subfze. subfzeo subfzeo.*/
1558 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1559 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1560
1561 /* subfic */
1562 static void gen_subfic(DisasContext *ctx)
1563 {
1564 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1565 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1566 c, 0, 1, 0, 0);
1567 tcg_temp_free(c);
1568 }
1569
1570 /* neg neg. nego nego. */
1571 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1572 {
1573 TCGv zero = tcg_const_tl(0);
1574 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1575 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1576 tcg_temp_free(zero);
1577 }
1578
1579 static void gen_neg(DisasContext *ctx)
1580 {
1581 gen_op_arith_neg(ctx, 0);
1582 }
1583
1584 static void gen_nego(DisasContext *ctx)
1585 {
1586 gen_op_arith_neg(ctx, 1);
1587 }
1588
1589 /*** Integer logical ***/
1590 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1591 static void glue(gen_, name)(DisasContext *ctx) \
1592 { \
1593 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1594 cpu_gpr[rB(ctx->opcode)]); \
1595 if (unlikely(Rc(ctx->opcode) != 0)) \
1596 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1597 }
1598
1599 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1600 static void glue(gen_, name)(DisasContext *ctx) \
1601 { \
1602 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1603 if (unlikely(Rc(ctx->opcode) != 0)) \
1604 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1605 }
1606
1607 /* and & and. */
1608 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1609 /* andc & andc. */
1610 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1611
1612 /* andi. */
1613 static void gen_andi_(DisasContext *ctx)
1614 {
1615 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1616 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1617 }
1618
1619 /* andis. */
1620 static void gen_andis_(DisasContext *ctx)
1621 {
1622 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625
1626 /* cntlzw */
1627 static void gen_cntlzw(DisasContext *ctx)
1628 {
1629 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1630 if (unlikely(Rc(ctx->opcode) != 0))
1631 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1632 }
1633
1634 /* cnttzw */
1635 static void gen_cnttzw(DisasContext *ctx)
1636 {
1637 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1638 if (unlikely(Rc(ctx->opcode) != 0)) {
1639 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1640 }
1641 }
1642
1643 /* eqv & eqv. */
1644 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1645 /* extsb & extsb. */
1646 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1647 /* extsh & extsh. */
1648 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1649 /* nand & nand. */
1650 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1651 /* nor & nor. */
1652 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1653
1654 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1655 static void gen_pause(DisasContext *ctx)
1656 {
1657 TCGv_i32 t0 = tcg_const_i32(0);
1658 tcg_gen_st_i32(t0, cpu_env,
1659 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1660 tcg_temp_free_i32(t0);
1661
1662 /* Stop translation, this gives other CPUs a chance to run */
1663 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1664 }
1665 #endif /* defined(TARGET_PPC64) */
1666
1667 /* or & or. */
1668 static void gen_or(DisasContext *ctx)
1669 {
1670 int rs, ra, rb;
1671
1672 rs = rS(ctx->opcode);
1673 ra = rA(ctx->opcode);
1674 rb = rB(ctx->opcode);
1675 /* Optimisation for mr. ri case */
1676 if (rs != ra || rs != rb) {
1677 if (rs != rb)
1678 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1679 else
1680 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1681 if (unlikely(Rc(ctx->opcode) != 0))
1682 gen_set_Rc0(ctx, cpu_gpr[ra]);
1683 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1684 gen_set_Rc0(ctx, cpu_gpr[rs]);
1685 #if defined(TARGET_PPC64)
1686 } else if (rs != 0) { /* 0 is nop */
1687 int prio = 0;
1688
1689 switch (rs) {
1690 case 1:
1691 /* Set process priority to low */
1692 prio = 2;
1693 break;
1694 case 6:
1695 /* Set process priority to medium-low */
1696 prio = 3;
1697 break;
1698 case 2:
1699 /* Set process priority to normal */
1700 prio = 4;
1701 break;
1702 #if !defined(CONFIG_USER_ONLY)
1703 case 31:
1704 if (!ctx->pr) {
1705 /* Set process priority to very low */
1706 prio = 1;
1707 }
1708 break;
1709 case 5:
1710 if (!ctx->pr) {
1711 /* Set process priority to medium-hight */
1712 prio = 5;
1713 }
1714 break;
1715 case 3:
1716 if (!ctx->pr) {
1717 /* Set process priority to high */
1718 prio = 6;
1719 }
1720 break;
1721 case 7:
1722 if (ctx->hv && !ctx->pr) {
1723 /* Set process priority to very high */
1724 prio = 7;
1725 }
1726 break;
1727 #endif
1728 default:
1729 break;
1730 }
1731 if (prio) {
1732 TCGv t0 = tcg_temp_new();
1733 gen_load_spr(t0, SPR_PPR);
1734 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1735 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1736 gen_store_spr(SPR_PPR, t0);
1737 tcg_temp_free(t0);
1738 }
1739 #if !defined(CONFIG_USER_ONLY)
1740 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1741 * CPU and the kernel hangs. This applies to all encodings other
1742 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1743 * and all currently undefined.
1744 */
1745 gen_pause(ctx);
1746 #endif
1747 #endif
1748 }
1749 }
1750 /* orc & orc. */
1751 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1752
1753 /* xor & xor. */
1754 static void gen_xor(DisasContext *ctx)
1755 {
1756 /* Optimisation for "set to zero" case */
1757 if (rS(ctx->opcode) != rB(ctx->opcode))
1758 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1759 else
1760 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1761 if (unlikely(Rc(ctx->opcode) != 0))
1762 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1763 }
1764
1765 /* ori */
1766 static void gen_ori(DisasContext *ctx)
1767 {
1768 target_ulong uimm = UIMM(ctx->opcode);
1769
1770 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1771 return;
1772 }
1773 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1774 }
1775
1776 /* oris */
1777 static void gen_oris(DisasContext *ctx)
1778 {
1779 target_ulong uimm = UIMM(ctx->opcode);
1780
1781 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1782 /* NOP */
1783 return;
1784 }
1785 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1786 }
1787
1788 /* xori */
1789 static void gen_xori(DisasContext *ctx)
1790 {
1791 target_ulong uimm = UIMM(ctx->opcode);
1792
1793 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1794 /* NOP */
1795 return;
1796 }
1797 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1798 }
1799
1800 /* xoris */
1801 static void gen_xoris(DisasContext *ctx)
1802 {
1803 target_ulong uimm = UIMM(ctx->opcode);
1804
1805 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1806 /* NOP */
1807 return;
1808 }
1809 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1810 }
1811
1812 /* popcntb : PowerPC 2.03 specification */
1813 static void gen_popcntb(DisasContext *ctx)
1814 {
1815 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1816 }
1817
1818 static void gen_popcntw(DisasContext *ctx)
1819 {
1820 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1821 }
1822
1823 #if defined(TARGET_PPC64)
1824 /* popcntd: PowerPC 2.06 specification */
1825 static void gen_popcntd(DisasContext *ctx)
1826 {
1827 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 }
1829 #endif
1830
1831 /* prtyw: PowerPC 2.05 specification */
1832 static void gen_prtyw(DisasContext *ctx)
1833 {
1834 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1835 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1836 TCGv t0 = tcg_temp_new();
1837 tcg_gen_shri_tl(t0, rs, 16);
1838 tcg_gen_xor_tl(ra, rs, t0);
1839 tcg_gen_shri_tl(t0, ra, 8);
1840 tcg_gen_xor_tl(ra, ra, t0);
1841 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1842 tcg_temp_free(t0);
1843 }
1844
1845 #if defined(TARGET_PPC64)
1846 /* prtyd: PowerPC 2.05 specification */
1847 static void gen_prtyd(DisasContext *ctx)
1848 {
1849 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1850 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1851 TCGv t0 = tcg_temp_new();
1852 tcg_gen_shri_tl(t0, rs, 32);
1853 tcg_gen_xor_tl(ra, rs, t0);
1854 tcg_gen_shri_tl(t0, ra, 16);
1855 tcg_gen_xor_tl(ra, ra, t0);
1856 tcg_gen_shri_tl(t0, ra, 8);
1857 tcg_gen_xor_tl(ra, ra, t0);
1858 tcg_gen_andi_tl(ra, ra, 1);
1859 tcg_temp_free(t0);
1860 }
1861 #endif
1862
1863 #if defined(TARGET_PPC64)
1864 /* bpermd */
1865 static void gen_bpermd(DisasContext *ctx)
1866 {
1867 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1868 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1869 }
1870 #endif
1871
1872 #if defined(TARGET_PPC64)
1873 /* extsw & extsw. */
1874 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1875
1876 /* cntlzd */
1877 static void gen_cntlzd(DisasContext *ctx)
1878 {
1879 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* cnttzd */
1885 static void gen_cnttzd(DisasContext *ctx)
1886 {
1887 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1888 if (unlikely(Rc(ctx->opcode) != 0)) {
1889 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1890 }
1891 }
1892 #endif
1893
1894 /*** Integer rotate ***/
1895
1896 /* rlwimi & rlwimi. */
1897 static void gen_rlwimi(DisasContext *ctx)
1898 {
1899 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1900 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1901 uint32_t sh = SH(ctx->opcode);
1902 uint32_t mb = MB(ctx->opcode);
1903 uint32_t me = ME(ctx->opcode);
1904
1905 if (sh == (31-me) && mb <= me) {
1906 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1907 } else {
1908 target_ulong mask;
1909 TCGv t1;
1910
1911 #if defined(TARGET_PPC64)
1912 mb += 32;
1913 me += 32;
1914 #endif
1915 mask = MASK(mb, me);
1916
1917 t1 = tcg_temp_new();
1918 if (mask <= 0xffffffffu) {
1919 TCGv_i32 t0 = tcg_temp_new_i32();
1920 tcg_gen_trunc_tl_i32(t0, t_rs);
1921 tcg_gen_rotli_i32(t0, t0, sh);
1922 tcg_gen_extu_i32_tl(t1, t0);
1923 tcg_temp_free_i32(t0);
1924 } else {
1925 #if defined(TARGET_PPC64)
1926 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1927 tcg_gen_rotli_i64(t1, t1, sh);
1928 #else
1929 g_assert_not_reached();
1930 #endif
1931 }
1932
1933 tcg_gen_andi_tl(t1, t1, mask);
1934 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1935 tcg_gen_or_tl(t_ra, t_ra, t1);
1936 tcg_temp_free(t1);
1937 }
1938 if (unlikely(Rc(ctx->opcode) != 0)) {
1939 gen_set_Rc0(ctx, t_ra);
1940 }
1941 }
1942
1943 /* rlwinm & rlwinm. */
1944 static void gen_rlwinm(DisasContext *ctx)
1945 {
1946 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1947 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1948 uint32_t sh = SH(ctx->opcode);
1949 uint32_t mb = MB(ctx->opcode);
1950 uint32_t me = ME(ctx->opcode);
1951
1952 if (mb == 0 && me == (31 - sh)) {
1953 tcg_gen_shli_tl(t_ra, t_rs, sh);
1954 tcg_gen_ext32u_tl(t_ra, t_ra);
1955 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1956 tcg_gen_ext32u_tl(t_ra, t_rs);
1957 tcg_gen_shri_tl(t_ra, t_ra, mb);
1958 } else {
1959 target_ulong mask;
1960 #if defined(TARGET_PPC64)
1961 mb += 32;
1962 me += 32;
1963 #endif
1964 mask = MASK(mb, me);
1965
1966 if (mask <= 0xffffffffu) {
1967 TCGv_i32 t0 = tcg_temp_new_i32();
1968 tcg_gen_trunc_tl_i32(t0, t_rs);
1969 tcg_gen_rotli_i32(t0, t0, sh);
1970 tcg_gen_andi_i32(t0, t0, mask);
1971 tcg_gen_extu_i32_tl(t_ra, t0);
1972 tcg_temp_free_i32(t0);
1973 } else {
1974 #if defined(TARGET_PPC64)
1975 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1976 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1977 tcg_gen_andi_i64(t_ra, t_ra, mask);
1978 #else
1979 g_assert_not_reached();
1980 #endif
1981 }
1982 }
1983 if (unlikely(Rc(ctx->opcode) != 0)) {
1984 gen_set_Rc0(ctx, t_ra);
1985 }
1986 }
1987
1988 /* rlwnm & rlwnm. */
1989 static void gen_rlwnm(DisasContext *ctx)
1990 {
1991 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1992 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1993 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1994 uint32_t mb = MB(ctx->opcode);
1995 uint32_t me = ME(ctx->opcode);
1996 target_ulong mask;
1997
1998 #if defined(TARGET_PPC64)
1999 mb += 32;
2000 me += 32;
2001 #endif
2002 mask = MASK(mb, me);
2003
2004 if (mask <= 0xffffffffu) {
2005 TCGv_i32 t0 = tcg_temp_new_i32();
2006 TCGv_i32 t1 = tcg_temp_new_i32();
2007 tcg_gen_trunc_tl_i32(t0, t_rb);
2008 tcg_gen_trunc_tl_i32(t1, t_rs);
2009 tcg_gen_andi_i32(t0, t0, 0x1f);
2010 tcg_gen_rotl_i32(t1, t1, t0);
2011 tcg_gen_extu_i32_tl(t_ra, t1);
2012 tcg_temp_free_i32(t0);
2013 tcg_temp_free_i32(t1);
2014 } else {
2015 #if defined(TARGET_PPC64)
2016 TCGv_i64 t0 = tcg_temp_new_i64();
2017 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2018 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2019 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2020 tcg_temp_free_i64(t0);
2021 #else
2022 g_assert_not_reached();
2023 #endif
2024 }
2025
2026 tcg_gen_andi_tl(t_ra, t_ra, mask);
2027
2028 if (unlikely(Rc(ctx->opcode) != 0)) {
2029 gen_set_Rc0(ctx, t_ra);
2030 }
2031 }
2032
2033 #if defined(TARGET_PPC64)
2034 #define GEN_PPC64_R2(name, opc1, opc2) \
2035 static void glue(gen_, name##0)(DisasContext *ctx) \
2036 { \
2037 gen_##name(ctx, 0); \
2038 } \
2039 \
2040 static void glue(gen_, name##1)(DisasContext *ctx) \
2041 { \
2042 gen_##name(ctx, 1); \
2043 }
2044 #define GEN_PPC64_R4(name, opc1, opc2) \
2045 static void glue(gen_, name##0)(DisasContext *ctx) \
2046 { \
2047 gen_##name(ctx, 0, 0); \
2048 } \
2049 \
2050 static void glue(gen_, name##1)(DisasContext *ctx) \
2051 { \
2052 gen_##name(ctx, 0, 1); \
2053 } \
2054 \
2055 static void glue(gen_, name##2)(DisasContext *ctx) \
2056 { \
2057 gen_##name(ctx, 1, 0); \
2058 } \
2059 \
2060 static void glue(gen_, name##3)(DisasContext *ctx) \
2061 { \
2062 gen_##name(ctx, 1, 1); \
2063 }
2064
2065 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2066 {
2067 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2068 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2069
2070 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2071 tcg_gen_shli_tl(t_ra, t_rs, sh);
2072 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2073 tcg_gen_shri_tl(t_ra, t_rs, mb);
2074 } else {
2075 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2076 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2077 }
2078 if (unlikely(Rc(ctx->opcode) != 0)) {
2079 gen_set_Rc0(ctx, t_ra);
2080 }
2081 }
2082
2083 /* rldicl - rldicl. */
2084 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2085 {
2086 uint32_t sh, mb;
2087
2088 sh = SH(ctx->opcode) | (shn << 5);
2089 mb = MB(ctx->opcode) | (mbn << 5);
2090 gen_rldinm(ctx, mb, 63, sh);
2091 }
2092 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2093
2094 /* rldicr - rldicr. */
2095 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2096 {
2097 uint32_t sh, me;
2098
2099 sh = SH(ctx->opcode) | (shn << 5);
2100 me = MB(ctx->opcode) | (men << 5);
2101 gen_rldinm(ctx, 0, me, sh);
2102 }
2103 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2104
2105 /* rldic - rldic. */
2106 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2107 {
2108 uint32_t sh, mb;
2109
2110 sh = SH(ctx->opcode) | (shn << 5);
2111 mb = MB(ctx->opcode) | (mbn << 5);
2112 gen_rldinm(ctx, mb, 63 - sh, sh);
2113 }
2114 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2115
2116 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2117 {
2118 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2119 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2120 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2121 TCGv t0;
2122
2123 t0 = tcg_temp_new();
2124 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2125 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2126 tcg_temp_free(t0);
2127
2128 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2129 if (unlikely(Rc(ctx->opcode) != 0)) {
2130 gen_set_Rc0(ctx, t_ra);
2131 }
2132 }
2133
2134 /* rldcl - rldcl. */
2135 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2136 {
2137 uint32_t mb;
2138
2139 mb = MB(ctx->opcode) | (mbn << 5);
2140 gen_rldnm(ctx, mb, 63);
2141 }
2142 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2143
2144 /* rldcr - rldcr. */
2145 static inline void gen_rldcr(DisasContext *ctx, int men)
2146 {
2147 uint32_t me;
2148
2149 me = MB(ctx->opcode) | (men << 5);
2150 gen_rldnm(ctx, 0, me);
2151 }
2152 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2153
2154 /* rldimi - rldimi. */
2155 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2156 {
2157 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2158 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2159 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2160 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2161 uint32_t me = 63 - sh;
2162
2163 if (mb <= me) {
2164 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2165 } else {
2166 target_ulong mask = MASK(mb, me);
2167 TCGv t1 = tcg_temp_new();
2168
2169 tcg_gen_rotli_tl(t1, t_rs, sh);
2170 tcg_gen_andi_tl(t1, t1, mask);
2171 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2172 tcg_gen_or_tl(t_ra, t_ra, t1);
2173 tcg_temp_free(t1);
2174 }
2175 if (unlikely(Rc(ctx->opcode) != 0)) {
2176 gen_set_Rc0(ctx, t_ra);
2177 }
2178 }
2179 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2180 #endif
2181
2182 /*** Integer shift ***/
2183
2184 /* slw & slw. */
2185 static void gen_slw(DisasContext *ctx)
2186 {
2187 TCGv t0, t1;
2188
2189 t0 = tcg_temp_new();
2190 /* AND rS with a mask that is 0 when rB >= 0x20 */
2191 #if defined(TARGET_PPC64)
2192 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2193 tcg_gen_sari_tl(t0, t0, 0x3f);
2194 #else
2195 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2196 tcg_gen_sari_tl(t0, t0, 0x1f);
2197 #endif
2198 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2199 t1 = tcg_temp_new();
2200 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2201 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2202 tcg_temp_free(t1);
2203 tcg_temp_free(t0);
2204 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2205 if (unlikely(Rc(ctx->opcode) != 0))
2206 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2207 }
2208
2209 /* sraw & sraw. */
2210 static void gen_sraw(DisasContext *ctx)
2211 {
2212 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2213 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2214 if (unlikely(Rc(ctx->opcode) != 0))
2215 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2216 }
2217
2218 /* srawi & srawi. */
2219 static void gen_srawi(DisasContext *ctx)
2220 {
2221 int sh = SH(ctx->opcode);
2222 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2223 TCGv src = cpu_gpr[rS(ctx->opcode)];
2224 if (sh == 0) {
2225 tcg_gen_ext32s_tl(dst, src);
2226 tcg_gen_movi_tl(cpu_ca, 0);
2227 } else {
2228 TCGv t0;
2229 tcg_gen_ext32s_tl(dst, src);
2230 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2231 t0 = tcg_temp_new();
2232 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2233 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2234 tcg_temp_free(t0);
2235 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2236 tcg_gen_sari_tl(dst, dst, sh);
2237 }
2238 if (unlikely(Rc(ctx->opcode) != 0)) {
2239 gen_set_Rc0(ctx, dst);
2240 }
2241 }
2242
2243 /* srw & srw. */
2244 static void gen_srw(DisasContext *ctx)
2245 {
2246 TCGv t0, t1;
2247
2248 t0 = tcg_temp_new();
2249 /* AND rS with a mask that is 0 when rB >= 0x20 */
2250 #if defined(TARGET_PPC64)
2251 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2252 tcg_gen_sari_tl(t0, t0, 0x3f);
2253 #else
2254 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2255 tcg_gen_sari_tl(t0, t0, 0x1f);
2256 #endif
2257 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2258 tcg_gen_ext32u_tl(t0, t0);
2259 t1 = tcg_temp_new();
2260 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2261 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2262 tcg_temp_free(t1);
2263 tcg_temp_free(t0);
2264 if (unlikely(Rc(ctx->opcode) != 0))
2265 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2266 }
2267
2268 #if defined(TARGET_PPC64)
2269 /* sld & sld. */
2270 static void gen_sld(DisasContext *ctx)
2271 {
2272 TCGv t0, t1;
2273
2274 t0 = tcg_temp_new();
2275 /* AND rS with a mask that is 0 when rB >= 0x40 */
2276 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2277 tcg_gen_sari_tl(t0, t0, 0x3f);
2278 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2279 t1 = tcg_temp_new();
2280 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2281 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2282 tcg_temp_free(t1);
2283 tcg_temp_free(t0);
2284 if (unlikely(Rc(ctx->opcode) != 0))
2285 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2286 }
2287
2288 /* srad & srad. */
2289 static void gen_srad(DisasContext *ctx)
2290 {
2291 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2292 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2293 if (unlikely(Rc(ctx->opcode) != 0))
2294 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2295 }
2296 /* sradi & sradi. */
2297 static inline void gen_sradi(DisasContext *ctx, int n)
2298 {
2299 int sh = SH(ctx->opcode) + (n << 5);
2300 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2301 TCGv src = cpu_gpr[rS(ctx->opcode)];
2302 if (sh == 0) {
2303 tcg_gen_mov_tl(dst, src);
2304 tcg_gen_movi_tl(cpu_ca, 0);
2305 } else {
2306 TCGv t0;
2307 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2308 t0 = tcg_temp_new();
2309 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2310 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2311 tcg_temp_free(t0);
2312 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2313 tcg_gen_sari_tl(dst, src, sh);
2314 }
2315 if (unlikely(Rc(ctx->opcode) != 0)) {
2316 gen_set_Rc0(ctx, dst);
2317 }
2318 }
2319
2320 static void gen_sradi0(DisasContext *ctx)
2321 {
2322 gen_sradi(ctx, 0);
2323 }
2324
2325 static void gen_sradi1(DisasContext *ctx)
2326 {
2327 gen_sradi(ctx, 1);
2328 }
2329
2330 /* srd & srd. */
2331 static void gen_srd(DisasContext *ctx)
2332 {
2333 TCGv t0, t1;
2334
2335 t0 = tcg_temp_new();
2336 /* AND rS with a mask that is 0 when rB >= 0x40 */
2337 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2338 tcg_gen_sari_tl(t0, t0, 0x3f);
2339 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2340 t1 = tcg_temp_new();
2341 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2342 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2343 tcg_temp_free(t1);
2344 tcg_temp_free(t0);
2345 if (unlikely(Rc(ctx->opcode) != 0))
2346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2347 }
2348 #endif
2349
2350 /*** Addressing modes ***/
2351 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2352 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2353 target_long maskl)
2354 {
2355 target_long simm = SIMM(ctx->opcode);
2356
2357 simm &= ~maskl;
2358 if (rA(ctx->opcode) == 0) {
2359 if (NARROW_MODE(ctx)) {
2360 simm = (uint32_t)simm;
2361 }
2362 tcg_gen_movi_tl(EA, simm);
2363 } else if (likely(simm != 0)) {
2364 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2365 if (NARROW_MODE(ctx)) {
2366 tcg_gen_ext32u_tl(EA, EA);
2367 }
2368 } else {
2369 if (NARROW_MODE(ctx)) {
2370 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2371 } else {
2372 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2373 }
2374 }
2375 }
2376
2377 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2378 {
2379 if (rA(ctx->opcode) == 0) {
2380 if (NARROW_MODE(ctx)) {
2381 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2382 } else {
2383 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2384 }
2385 } else {
2386 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2387 if (NARROW_MODE(ctx)) {
2388 tcg_gen_ext32u_tl(EA, EA);
2389 }
2390 }
2391 }
2392
2393 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2394 {
2395 if (rA(ctx->opcode) == 0) {
2396 tcg_gen_movi_tl(EA, 0);
2397 } else if (NARROW_MODE(ctx)) {
2398 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2399 } else {
2400 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2401 }
2402 }
2403
2404 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2405 target_long val)
2406 {
2407 tcg_gen_addi_tl(ret, arg1, val);
2408 if (NARROW_MODE(ctx)) {
2409 tcg_gen_ext32u_tl(ret, ret);
2410 }
2411 }
2412
2413 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2414 {
2415 TCGLabel *l1 = gen_new_label();
2416 TCGv t0 = tcg_temp_new();
2417 TCGv_i32 t1, t2;
2418 tcg_gen_andi_tl(t0, EA, mask);
2419 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2420 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2421 t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
2422 gen_update_nip(ctx, ctx->nip - 4);
2423 gen_helper_raise_exception_err(cpu_env, t1, t2);
2424 tcg_temp_free_i32(t1);
2425 tcg_temp_free_i32(t2);
2426 gen_set_label(l1);
2427 tcg_temp_free(t0);
2428 }
2429
2430 /*** Integer load ***/
2431 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2432 {
2433 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2434 }
2435
2436 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2437 {
2438 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2439 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2440 }
2441
2442 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2445 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2446 }
2447
2448 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449 {
2450 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2451 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2452 }
2453
2454 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2455 {
2456 TCGv tmp = tcg_temp_new();
2457 gen_qemu_ld32u(ctx, tmp, addr);
2458 tcg_gen_extu_tl_i64(val, tmp);
2459 tcg_temp_free(tmp);
2460 }
2461
2462 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2463 {
2464 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2465 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2466 }
2467
2468 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2469 {
2470 TCGv tmp = tcg_temp_new();
2471 gen_qemu_ld32s(ctx, tmp, addr);
2472 tcg_gen_ext_tl_i64(val, tmp);
2473 tcg_temp_free(tmp);
2474 }
2475
2476 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2477 {
2478 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2479 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2480 }
2481
2482 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2483 {
2484 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2485 }
2486
2487 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2488 {
2489 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2490 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2491 }
2492
2493 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2494 {
2495 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2496 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2497 }
2498
2499 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2500 {
2501 TCGv tmp = tcg_temp_new();
2502 tcg_gen_trunc_i64_tl(tmp, val);
2503 gen_qemu_st32(ctx, tmp, addr);
2504 tcg_temp_free(tmp);
2505 }
2506
2507 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2508 {
2509 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2510 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2511 }
2512
2513 #define GEN_LD(name, ldop, opc, type) \
2514 static void glue(gen_, name)(DisasContext *ctx) \
2515 { \
2516 TCGv EA; \
2517 gen_set_access_type(ctx, ACCESS_INT); \
2518 EA = tcg_temp_new(); \
2519 gen_addr_imm_index(ctx, EA, 0); \
2520 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2521 tcg_temp_free(EA); \
2522 }
2523
2524 #define GEN_LDU(name, ldop, opc, type) \
2525 static void glue(gen_, name##u)(DisasContext *ctx) \
2526 { \
2527 TCGv EA; \
2528 if (unlikely(rA(ctx->opcode) == 0 || \
2529 rA(ctx->opcode) == rD(ctx->opcode))) { \
2530 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2531 return; \
2532 } \
2533 gen_set_access_type(ctx, ACCESS_INT); \
2534 EA = tcg_temp_new(); \
2535 if (type == PPC_64B) \
2536 gen_addr_imm_index(ctx, EA, 0x03); \
2537 else \
2538 gen_addr_imm_index(ctx, EA, 0); \
2539 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2541 tcg_temp_free(EA); \
2542 }
2543
2544 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2545 static void glue(gen_, name##ux)(DisasContext *ctx) \
2546 { \
2547 TCGv EA; \
2548 if (unlikely(rA(ctx->opcode) == 0 || \
2549 rA(ctx->opcode) == rD(ctx->opcode))) { \
2550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2551 return; \
2552 } \
2553 gen_set_access_type(ctx, ACCESS_INT); \
2554 EA = tcg_temp_new(); \
2555 gen_addr_reg_index(ctx, EA); \
2556 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2557 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2558 tcg_temp_free(EA); \
2559 }
2560
2561 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2562 static void glue(gen_, name##x)(DisasContext *ctx) \
2563 { \
2564 TCGv EA; \
2565 chk; \
2566 gen_set_access_type(ctx, ACCESS_INT); \
2567 EA = tcg_temp_new(); \
2568 gen_addr_reg_index(ctx, EA); \
2569 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2570 tcg_temp_free(EA); \
2571 }
2572
2573 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2574 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2575
2576 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2577 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2578
2579 #define GEN_LDS(name, ldop, op, type) \
2580 GEN_LD(name, ldop, op | 0x20, type); \
2581 GEN_LDU(name, ldop, op | 0x21, type); \
2582 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2583 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2584
2585 /* lbz lbzu lbzux lbzx */
2586 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2587 /* lha lhau lhaux lhax */
2588 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2589 /* lhz lhzu lhzux lhzx */
2590 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2591 /* lwz lwzu lwzux lwzx */
2592 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2593 #if defined(TARGET_PPC64)
2594 /* lwaux */
2595 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2596 /* lwax */
2597 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2598 /* ldux */
2599 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2600 /* ldx */
2601 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2602
2603 /* CI load/store variants */
2604 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2605 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2606 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2607 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2608
2609 static void gen_ld(DisasContext *ctx)
2610 {
2611 TCGv EA;
2612 if (Rc(ctx->opcode)) {
2613 if (unlikely(rA(ctx->opcode) == 0 ||
2614 rA(ctx->opcode) == rD(ctx->opcode))) {
2615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2616 return;
2617 }
2618 }
2619 gen_set_access_type(ctx, ACCESS_INT);
2620 EA = tcg_temp_new();
2621 gen_addr_imm_index(ctx, EA, 0x03);
2622 if (ctx->opcode & 0x02) {
2623 /* lwa (lwau is undefined) */
2624 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2625 } else {
2626 /* ld - ldu */
2627 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2628 }
2629 if (Rc(ctx->opcode))
2630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2631 tcg_temp_free(EA);
2632 }
2633
2634 /* lq */
2635 static void gen_lq(DisasContext *ctx)
2636 {
2637 int ra, rd;
2638 TCGv EA;
2639
2640 /* lq is a legal user mode instruction starting in ISA 2.07 */
2641 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2642 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2643
2644 if (!legal_in_user_mode && ctx->pr) {
2645 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2646 return;
2647 }
2648
2649 if (!le_is_supported && ctx->le_mode) {
2650 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2651 return;
2652 }
2653
2654 ra = rA(ctx->opcode);
2655 rd = rD(ctx->opcode);
2656 if (unlikely((rd & 1) || rd == ra)) {
2657 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2658 return;
2659 }
2660
2661 gen_set_access_type(ctx, ACCESS_INT);
2662 EA = tcg_temp_new();
2663 gen_addr_imm_index(ctx, EA, 0x0F);
2664
2665 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2666 64-bit byteswap already. */
2667 if (unlikely(ctx->le_mode)) {
2668 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2669 gen_addr_add(ctx, EA, EA, 8);
2670 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2671 } else {
2672 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2673 gen_addr_add(ctx, EA, EA, 8);
2674 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2675 }
2676 tcg_temp_free(EA);
2677 }
2678 #endif
2679
2680 /*** Integer store ***/
2681 #define GEN_ST(name, stop, opc, type) \
2682 static void glue(gen_, name)(DisasContext *ctx) \
2683 { \
2684 TCGv EA; \
2685 gen_set_access_type(ctx, ACCESS_INT); \
2686 EA = tcg_temp_new(); \
2687 gen_addr_imm_index(ctx, EA, 0); \
2688 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2689 tcg_temp_free(EA); \
2690 }
2691
2692 #define GEN_STU(name, stop, opc, type) \
2693 static void glue(gen_, stop##u)(DisasContext *ctx) \
2694 { \
2695 TCGv EA; \
2696 if (unlikely(rA(ctx->opcode) == 0)) { \
2697 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2698 return; \
2699 } \
2700 gen_set_access_type(ctx, ACCESS_INT); \
2701 EA = tcg_temp_new(); \
2702 if (type == PPC_64B) \
2703 gen_addr_imm_index(ctx, EA, 0x03); \
2704 else \
2705 gen_addr_imm_index(ctx, EA, 0); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2709 }
2710
2711 #define GEN_STUX(name, stop, opc2, opc3, type) \
2712 static void glue(gen_, name##ux)(DisasContext *ctx) \
2713 { \
2714 TCGv EA; \
2715 if (unlikely(rA(ctx->opcode) == 0)) { \
2716 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2717 return; \
2718 } \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 gen_addr_reg_index(ctx, EA); \
2722 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2723 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2724 tcg_temp_free(EA); \
2725 }
2726
2727 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2728 static void glue(gen_, name##x)(DisasContext *ctx) \
2729 { \
2730 TCGv EA; \
2731 chk; \
2732 gen_set_access_type(ctx, ACCESS_INT); \
2733 EA = tcg_temp_new(); \
2734 gen_addr_reg_index(ctx, EA); \
2735 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2736 tcg_temp_free(EA); \
2737 }
2738 #define GEN_STX(name, stop, opc2, opc3, type) \
2739 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2740
2741 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2742 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2743
2744 #define GEN_STS(name, stop, op, type) \
2745 GEN_ST(name, stop, op | 0x20, type); \
2746 GEN_STU(name, stop, op | 0x21, type); \
2747 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2748 GEN_STX(name, stop, 0x17, op | 0x00, type)
2749
2750 /* stb stbu stbux stbx */
2751 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2752 /* sth sthu sthux sthx */
2753 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2754 /* stw stwu stwux stwx */
2755 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2756 #if defined(TARGET_PPC64)
2757 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2758 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2759 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2760 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2761 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2762 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2763
2764 static void gen_std(DisasContext *ctx)
2765 {
2766 int rs;
2767 TCGv EA;
2768
2769 rs = rS(ctx->opcode);
2770 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2771 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2772 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2773
2774 if (!(ctx->insns_flags & PPC_64BX)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2776 }
2777
2778 if (!legal_in_user_mode && ctx->pr) {
2779 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2780 return;
2781 }
2782
2783 if (!le_is_supported && ctx->le_mode) {
2784 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2785 return;
2786 }
2787
2788 if (unlikely(rs & 1)) {
2789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2790 return;
2791 }
2792 gen_set_access_type(ctx, ACCESS_INT);
2793 EA = tcg_temp_new();
2794 gen_addr_imm_index(ctx, EA, 0x03);
2795
2796 /* We only need to swap high and low halves. gen_qemu_st64 does
2797 necessary 64-bit byteswap already. */
2798 if (unlikely(ctx->le_mode)) {
2799 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2800 gen_addr_add(ctx, EA, EA, 8);
2801 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2802 } else {
2803 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2804 gen_addr_add(ctx, EA, EA, 8);
2805 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2806 }
2807 tcg_temp_free(EA);
2808 } else {
2809 /* std / stdu*/
2810 if (Rc(ctx->opcode)) {
2811 if (unlikely(rA(ctx->opcode) == 0)) {
2812 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2813 return;
2814 }
2815 }
2816 gen_set_access_type(ctx, ACCESS_INT);
2817 EA = tcg_temp_new();
2818 gen_addr_imm_index(ctx, EA, 0x03);
2819 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2820 if (Rc(ctx->opcode))
2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2822 tcg_temp_free(EA);
2823 }
2824 }
2825 #endif
2826 /*** Integer load and store with byte reverse ***/
2827
2828 /* lhbrx */
2829 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2830 {
2831 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2832 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2833 }
2834 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2835
2836 /* lwbrx */
2837 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838 {
2839 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2840 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2841 }
2842 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2843
2844 #if defined(TARGET_PPC64)
2845 /* ldbrx */
2846 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2849 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2850 }
2851 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2852 #endif /* TARGET_PPC64 */
2853
2854 /* sthbrx */
2855 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2856 {
2857 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2858 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2859 }
2860 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2861
2862 /* stwbrx */
2863 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2864 {
2865 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2866 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2867 }
2868 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2869
2870 #if defined(TARGET_PPC64)
2871 /* stdbrx */
2872 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2873 {
2874 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2875 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2876 }
2877 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2878 #endif /* TARGET_PPC64 */
2879
2880 /*** Integer load and store multiple ***/
2881
2882 /* lmw */
2883 static void gen_lmw(DisasContext *ctx)
2884 {
2885 TCGv t0;
2886 TCGv_i32 t1;
2887 gen_set_access_type(ctx, ACCESS_INT);
2888 t0 = tcg_temp_new();
2889 t1 = tcg_const_i32(rD(ctx->opcode));
2890 gen_addr_imm_index(ctx, t0, 0);
2891 gen_helper_lmw(cpu_env, t0, t1);
2892 tcg_temp_free(t0);
2893 tcg_temp_free_i32(t1);
2894 }
2895
2896 /* stmw */
2897 static void gen_stmw(DisasContext *ctx)
2898 {
2899 TCGv t0;
2900 TCGv_i32 t1;
2901 gen_set_access_type(ctx, ACCESS_INT);
2902 t0 = tcg_temp_new();
2903 t1 = tcg_const_i32(rS(ctx->opcode));
2904 gen_addr_imm_index(ctx, t0, 0);
2905 gen_helper_stmw(cpu_env, t0, t1);
2906 tcg_temp_free(t0);
2907 tcg_temp_free_i32(t1);
2908 }
2909
2910 /*** Integer load and store strings ***/
2911
2912 /* lswi */
2913 /* PowerPC32 specification says we must generate an exception if
2914 * rA is in the range of registers to be loaded.
2915 * In an other hand, IBM says this is valid, but rA won't be loaded.
2916 * For now, I'll follow the spec...
2917 */
2918 static void gen_lswi(DisasContext *ctx)
2919 {
2920 TCGv t0;
2921 TCGv_i32 t1, t2;
2922 int nb = NB(ctx->opcode);
2923 int start = rD(ctx->opcode);
2924 int ra = rA(ctx->opcode);
2925 int nr;
2926
2927 if (nb == 0)
2928 nb = 32;
2929 nr = (nb + 3) / 4;
2930 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2932 return;
2933 }
2934 gen_set_access_type(ctx, ACCESS_INT);
2935 t0 = tcg_temp_new();
2936 gen_addr_register(ctx, t0);
2937 t1 = tcg_const_i32(nb);
2938 t2 = tcg_const_i32(start);
2939 gen_helper_lsw(cpu_env, t0, t1, t2);
2940 tcg_temp_free(t0);
2941 tcg_temp_free_i32(t1);
2942 tcg_temp_free_i32(t2);
2943 }
2944
2945 /* lswx */
2946 static void gen_lswx(DisasContext *ctx)
2947 {
2948 TCGv t0;
2949 TCGv_i32 t1, t2, t3;
2950 gen_set_access_type(ctx, ACCESS_INT);
2951 t0 = tcg_temp_new();
2952 gen_addr_reg_index(ctx, t0);
2953 t1 = tcg_const_i32(rD(ctx->opcode));
2954 t2 = tcg_const_i32(rA(ctx->opcode));
2955 t3 = tcg_const_i32(rB(ctx->opcode));
2956 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2957 tcg_temp_free(t0);
2958 tcg_temp_free_i32(t1);
2959 tcg_temp_free_i32(t2);
2960 tcg_temp_free_i32(t3);
2961 }
2962
2963 /* stswi */
2964 static void gen_stswi(DisasContext *ctx)
2965 {
2966 TCGv t0;
2967 TCGv_i32 t1, t2;
2968 int nb = NB(ctx->opcode);
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 t0 = tcg_temp_new();
2971 gen_addr_register(ctx, t0);
2972 if (nb == 0)
2973 nb = 32;
2974 t1 = tcg_const_i32(nb);
2975 t2 = tcg_const_i32(rS(ctx->opcode));
2976 gen_helper_stsw(cpu_env, t0, t1, t2);
2977 tcg_temp_free(t0);
2978 tcg_temp_free_i32(t1);
2979 tcg_temp_free_i32(t2);
2980 }
2981
2982 /* stswx */
2983 static void gen_stswx(DisasContext *ctx)
2984 {
2985 TCGv t0;
2986 TCGv_i32 t1, t2;
2987 gen_set_access_type(ctx, ACCESS_INT);
2988 t0 = tcg_temp_new();
2989 gen_addr_reg_index(ctx, t0);
2990 t1 = tcg_temp_new_i32();
2991 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2992 tcg_gen_andi_i32(t1, t1, 0x7F);
2993 t2 = tcg_const_i32(rS(ctx->opcode));
2994 gen_helper_stsw(cpu_env, t0, t1, t2);
2995 tcg_temp_free(t0);
2996 tcg_temp_free_i32(t1);
2997 tcg_temp_free_i32(t2);
2998 }
2999
3000 /*** Memory synchronisation ***/
3001 /* eieio */
3002 static void gen_eieio(DisasContext *ctx)
3003 {
3004 }
3005
3006 #if !defined(CONFIG_USER_ONLY)
3007 static inline void gen_check_tlb_flush(DisasContext *ctx)
3008 {
3009 TCGv_i32 t;
3010 TCGLabel *l;
3011
3012 if (!ctx->lazy_tlb_flush) {
3013 return;
3014 }
3015 l = gen_new_label();
3016 t = tcg_temp_new_i32();
3017 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3018 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3019 gen_helper_check_tlb_flush(cpu_env);
3020 gen_set_label(l);
3021 tcg_temp_free_i32(t);
3022 }
3023 #else
3024 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3025 #endif
3026
3027 /* isync */
3028 static void gen_isync(DisasContext *ctx)
3029 {
3030 /*
3031 * We need to check for a pending TLB flush. This can only happen in
3032 * kernel mode however so check MSR_PR
3033 */
3034 if (!ctx->pr) {
3035 gen_check_tlb_flush(ctx);
3036 }
3037 gen_stop_exception(ctx);
3038 }
3039
3040 #define LARX(name, len, loadop) \
3041 static void gen_##name(DisasContext *ctx) \
3042 { \
3043 TCGv t0; \
3044 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3045 gen_set_access_type(ctx, ACCESS_RES); \
3046 t0 = tcg_temp_local_new(); \
3047 gen_addr_reg_index(ctx, t0); \
3048 if ((len) > 1) { \
3049 gen_check_align(ctx, t0, (len)-1); \
3050 } \
3051 gen_qemu_##loadop(ctx, gpr, t0); \
3052 tcg_gen_mov_tl(cpu_reserve, t0); \
3053 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3054 tcg_temp_free(t0); \
3055 }
3056
3057 /* lwarx */
3058 LARX(lbarx, 1, ld8u);
3059 LARX(lharx, 2, ld16u);
3060 LARX(lwarx, 4, ld32u);
3061
3062
3063 #if defined(CONFIG_USER_ONLY)
3064 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3065 int reg, int size)
3066 {
3067 TCGv t0 = tcg_temp_new();
3068
3069 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3070 tcg_gen_movi_tl(t0, (size << 5) | reg);
3071 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3072 tcg_temp_free(t0);
3073 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3074 }
3075 #else
3076 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3077 int reg, int size)
3078 {
3079 TCGLabel *l1;
3080
3081 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3082 l1 = gen_new_label();
3083 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3084 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3085 #if defined(TARGET_PPC64)
3086 if (size == 8) {
3087 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3088 } else
3089 #endif
3090 if (size == 4) {
3091 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3092 } else if (size == 2) {
3093 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3094 #if defined(TARGET_PPC64)
3095 } else if (size == 16) {
3096 TCGv gpr1, gpr2 , EA8;
3097 if (unlikely(ctx->le_mode)) {
3098 gpr1 = cpu_gpr[reg+1];
3099 gpr2 = cpu_gpr[reg];
3100 } else {
3101 gpr1 = cpu_gpr[reg];
3102 gpr2 = cpu_gpr[reg+1];
3103 }
3104 gen_qemu_st64(ctx, gpr1, EA);
3105 EA8 = tcg_temp_local_new();
3106 gen_addr_add(ctx, EA8, EA, 8);
3107 gen_qemu_st64(ctx, gpr2, EA8);
3108 tcg_temp_free(EA8);
3109 #endif
3110 } else {
3111 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3112 }
3113 gen_set_label(l1);
3114 tcg_gen_movi_tl(cpu_reserve, -1);
3115 }
3116 #endif
3117
3118 #define STCX(name, len) \
3119 static void gen_##name(DisasContext *ctx) \
3120 { \
3121 TCGv t0; \
3122 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3123 gen_inval_exception(ctx, \
3124 POWERPC_EXCP_INVAL_INVAL); \
3125 return; \
3126 } \
3127 gen_set_access_type(ctx, ACCESS_RES); \
3128 t0 = tcg_temp_local_new(); \
3129 gen_addr_reg_index(ctx, t0); \
3130 if (len > 1) { \
3131 gen_check_align(ctx, t0, (len)-1); \
3132 } \
3133 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3134 tcg_temp_free(t0); \
3135 }
3136
3137 STCX(stbcx_, 1);
3138 STCX(sthcx_, 2);
3139 STCX(stwcx_, 4);
3140
3141 #if defined(TARGET_PPC64)
3142 /* ldarx */
3143 LARX(ldarx, 8, ld64);
3144
3145 /* lqarx */
3146 static void gen_lqarx(DisasContext *ctx)
3147 {
3148 TCGv EA;
3149 int rd = rD(ctx->opcode);
3150 TCGv gpr1, gpr2;
3151
3152 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3153 (rd == rB(ctx->opcode)))) {
3154 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3155 return;
3156 }
3157
3158 gen_set_access_type(ctx, ACCESS_RES);
3159 EA = tcg_temp_local_new();
3160 gen_addr_reg_index(ctx, EA);
3161 gen_check_align(ctx, EA, 15);
3162 if (unlikely(ctx->le_mode)) {
3163 gpr1 = cpu_gpr[rd+1];
3164 gpr2 = cpu_gpr[rd];
3165 } else {
3166 gpr1 = cpu_gpr[rd];
3167 gpr2 = cpu_gpr[rd+1];
3168 }
3169 gen_qemu_ld64(ctx, gpr1, EA);
3170 tcg_gen_mov_tl(cpu_reserve, EA);
3171
3172 gen_addr_add(ctx, EA, EA, 8);
3173 gen_qemu_ld64(ctx, gpr2, EA);
3174
3175 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3176 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3177
3178 tcg_temp_free(EA);
3179 }
3180
3181 /* stdcx. */
3182 STCX(stdcx_, 8);
3183 STCX(stqcx_, 16);
3184 #endif /* defined(TARGET_PPC64) */
3185
3186 /* sync */
3187 static void gen_sync(DisasContext *ctx)
3188 {
3189 uint32_t l = (ctx->opcode >> 21) & 3;
3190
3191 /*
3192 * We may need to check for a pending TLB flush.
3193 *
3194 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3195 *
3196 * Additionally, this can only happen in kernel mode however so
3197 * check MSR_PR as well.
3198 */
3199 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3200 gen_check_tlb_flush(ctx);
3201 }
3202 }
3203
3204 /* wait */
3205 static void gen_wait(DisasContext *ctx)
3206 {
3207 TCGv_i32 t0 = tcg_const_i32(1);
3208 tcg_gen_st_i32(t0, cpu_env,
3209 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3210 tcg_temp_free_i32(t0);
3211 /* Stop translation, as the CPU is supposed to sleep from now */
3212 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3213 }
3214
3215 #if defined(TARGET_PPC64)
3216 static void gen_doze(DisasContext *ctx)
3217 {
3218 #if defined(CONFIG_USER_ONLY)
3219 GEN_PRIV;
3220 #else
3221 TCGv_i32 t;
3222
3223 CHK_HV;
3224 t = tcg_const_i32(PPC_PM_DOZE);
3225 gen_helper_pminsn(cpu_env, t);
3226 tcg_temp_free_i32(t);
3227 gen_stop_exception(ctx);
3228 #endif /* defined(CONFIG_USER_ONLY) */
3229 }
3230
3231 static void gen_nap(DisasContext *ctx)
3232 {
3233 #if defined(CONFIG_USER_ONLY)
3234 GEN_PRIV;
3235 #else
3236 TCGv_i32 t;
3237
3238 CHK_HV;
3239 t = tcg_const_i32(PPC_PM_NAP);
3240 gen_helper_pminsn(cpu_env, t);
3241 tcg_temp_free_i32(t);
3242 gen_stop_exception(ctx);
3243 #endif /* defined(CONFIG_USER_ONLY) */
3244 }
3245
3246 static void gen_sleep(DisasContext *ctx)
3247 {
3248 #if defined(CONFIG_USER_ONLY)
3249 GEN_PRIV;
3250 #else
3251 TCGv_i32 t;
3252
3253 CHK_HV;
3254 t = tcg_const_i32(PPC_PM_SLEEP);
3255 gen_helper_pminsn(cpu_env, t);
3256 tcg_temp_free_i32(t);
3257 gen_stop_exception(ctx);
3258 #endif /* defined(CONFIG_USER_ONLY) */
3259 }
3260
3261 static void gen_rvwinkle(DisasContext *ctx)
3262 {
3263 #if defined(CONFIG_USER_ONLY)
3264 GEN_PRIV;
3265 #else
3266 TCGv_i32 t;
3267
3268 CHK_HV;
3269 t = tcg_const_i32(PPC_PM_RVWINKLE);
3270 gen_helper_pminsn(cpu_env, t);
3271 tcg_temp_free_i32(t);
3272 gen_stop_exception(ctx);
3273 #endif /* defined(CONFIG_USER_ONLY) */
3274 }
3275 #endif /* #if defined(TARGET_PPC64) */
3276
3277 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3278 {
3279 #if defined(TARGET_PPC64)
3280 if (ctx->has_cfar)
3281 tcg_gen_movi_tl(cpu_cfar, nip);
3282 #endif
3283 }
3284
3285 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3286 {
3287 if (unlikely(ctx->singlestep_enabled)) {
3288 return false;
3289 }
3290
3291 #ifndef CONFIG_USER_ONLY
3292 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3293 #else
3294 return true;
3295 #endif
3296 }
3297
3298 /*** Branch ***/
3299 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3300 {
3301 if (NARROW_MODE(ctx)) {
3302 dest = (uint32_t) dest;
3303 }
3304 if (use_goto_tb(ctx, dest)) {
3305 tcg_gen_goto_tb(n);
3306 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3307 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3308 } else {
3309 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3310 if (unlikely(ctx->singlestep_enabled)) {
3311 if ((ctx->singlestep_enabled &
3312 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3313 (ctx->exception == POWERPC_EXCP_BRANCH ||
3314 ctx->exception == POWERPC_EXCP_TRACE)) {
3315 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3316 }
3317 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3318 gen_debug_exception(ctx);
3319 }
3320 }
3321 tcg_gen_exit_tb(0);
3322 }
3323 }
3324
3325 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3326 {
3327 if (NARROW_MODE(ctx)) {
3328 nip = (uint32_t)nip;
3329 }
3330 tcg_gen_movi_tl(cpu_lr, nip);
3331 }
3332
3333 /* b ba bl bla */
3334 static void gen_b(DisasContext *ctx)
3335 {
3336 target_ulong li, target;
3337
3338 ctx->exception = POWERPC_EXCP_BRANCH;
3339 /* sign extend LI */
3340 li = LI(ctx->opcode);
3341 li = (li ^ 0x02000000) - 0x02000000;
3342 if (likely(AA(ctx->opcode) == 0)) {
3343 target = ctx->nip + li - 4;
3344 } else {
3345 target = li;
3346 }
3347 if (LK(ctx->opcode)) {
3348 gen_setlr(ctx, ctx->nip);
3349 }
3350 gen_update_cfar(ctx, ctx->nip - 4);
3351 gen_goto_tb(ctx, 0, target);
3352 }
3353
3354 #define BCOND_IM 0
3355 #define BCOND_LR 1
3356 #define BCOND_CTR 2
3357 #define BCOND_TAR 3
3358
3359 static inline void gen_bcond(DisasContext *ctx, int type)
3360 {
3361 uint32_t bo = BO(ctx->opcode);
3362 TCGLabel *l1;
3363 TCGv target;
3364
3365 ctx->exception = POWERPC_EXCP_BRANCH;
3366 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3367 target = tcg_temp_local_new();
3368 if (type == BCOND_CTR)
3369 tcg_gen_mov_tl(target, cpu_ctr);
3370 else if (type == BCOND_TAR)
3371 gen_load_spr(target, SPR_TAR);
3372 else
3373 tcg_gen_mov_tl(target, cpu_lr);
3374 } else {
3375 TCGV_UNUSED(target);
3376 }
3377 if (LK(ctx->opcode))
3378 gen_setlr(ctx, ctx->nip);
3379 l1 = gen_new_label();
3380 if ((bo & 0x4) == 0) {
3381 /* Decrement and test CTR */
3382 TCGv temp = tcg_temp_new();
3383 if (unlikely(type == BCOND_CTR)) {
3384 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3385 return;
3386 }
3387 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3388 if (NARROW_MODE(ctx)) {
3389 tcg_gen_ext32u_tl(temp, cpu_ctr);
3390 } else {
3391 tcg_gen_mov_tl(temp, cpu_ctr);
3392 }
3393 if (bo & 0x2) {
3394 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3395 } else {
3396 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3397 }
3398 tcg_temp_free(temp);
3399 }
3400 if ((bo & 0x10) == 0) {
3401 /* Test CR */
3402 uint32_t bi = BI(ctx->opcode);
3403 uint32_t mask = 0x08 >> (bi & 0x03);
3404 TCGv_i32 temp = tcg_temp_new_i32();
3405
3406 if (bo & 0x8) {
3407 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3408 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3409 } else {
3410 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3411 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3412 }
3413 tcg_temp_free_i32(temp);
3414 }
3415 gen_update_cfar(ctx, ctx->nip - 4);
3416 if (type == BCOND_IM) {
3417 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3418 if (likely(AA(ctx->opcode) == 0)) {
3419 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3420 } else {
3421 gen_goto_tb(ctx, 0, li);
3422 }
3423 gen_set_label(l1);
3424 gen_goto_tb(ctx, 1, ctx->nip);
3425 } else {
3426 if (NARROW_MODE(ctx)) {
3427 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3428 } else {
3429 tcg_gen_andi_tl(cpu_nip, target, ~3);
3430 }
3431 tcg_gen_exit_tb(0);
3432 gen_set_label(l1);
3433 gen_update_nip(ctx, ctx->nip);
3434 tcg_gen_exit_tb(0);
3435 }
3436 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3437 tcg_temp_free(target);
3438 }
3439 }
3440
3441 static void gen_bc(DisasContext *ctx)
3442 {
3443 gen_bcond(ctx, BCOND_IM);
3444 }
3445
3446 static void gen_bcctr(DisasContext *ctx)
3447 {
3448 gen_bcond(ctx, BCOND_CTR);
3449 }
3450
3451 static void gen_bclr(DisasContext *ctx)
3452 {
3453 gen_bcond(ctx, BCOND_LR);
3454 }
3455
3456 static void gen_bctar(DisasContext *ctx)
3457 {
3458 gen_bcond(ctx, BCOND_TAR);
3459 }
3460
3461 /*** Condition register logical ***/
3462 #define GEN_CRLOGIC(name, tcg_op, opc) \
3463 static void glue(gen_, name)(DisasContext *ctx) \
3464 { \
3465 uint8_t bitmask; \
3466 int sh; \
3467 TCGv_i32 t0, t1; \
3468 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3469 t0 = tcg_temp_new_i32(); \
3470 if (sh > 0) \
3471 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3472 else if (sh < 0) \
3473 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3474 else \
3475 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3476 t1 = tcg_temp_new_i32(); \
3477 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3478 if (sh > 0) \
3479 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3480 else if (sh < 0) \
3481 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3482 else \
3483 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3484 tcg_op(t0, t0, t1); \
3485 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3486 tcg_gen_andi_i32(t0, t0, bitmask); \
3487 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3488 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3489 tcg_temp_free_i32(t0); \
3490 tcg_temp_free_i32(t1); \
3491 }
3492
3493 /* crand */
3494 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3495 /* crandc */
3496 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3497 /* creqv */
3498 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3499 /* crnand */
3500 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3501 /* crnor */
3502 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3503 /* cror */
3504 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3505 /* crorc */
3506 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3507 /* crxor */
3508 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3509
3510 /* mcrf */
3511 static void gen_mcrf(DisasContext *ctx)
3512 {
3513 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3514 }
3515
3516 /*** System linkage ***/
3517
3518 /* rfi (supervisor only) */
3519 static void gen_rfi(DisasContext *ctx)
3520 {
3521 #if defined(CONFIG_USER_ONLY)
3522 GEN_PRIV;
3523 #else
3524 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3525 * processors compliant with arch 2.x, we should remove it there,
3526 * but we need to fix OpenBIOS not to use it on 970 first
3527 */
3528 /* Restore CPU state */
3529 CHK_SV;
3530 gen_update_cfar(ctx, ctx->nip - 4);
3531 gen_helper_rfi(cpu_env);
3532 gen_sync_exception(ctx);
3533 #endif
3534 }
3535
3536 #if defined(TARGET_PPC64)
3537 static void gen_rfid(DisasContext *ctx)
3538 {
3539 #if defined(CONFIG_USER_ONLY)
3540 GEN_PRIV;
3541 #else
3542 /* Restore CPU state */
3543 CHK_SV;
3544 gen_update_cfar(ctx, ctx->nip - 4);
3545 gen_helper_rfid(cpu_env);
3546 gen_sync_exception(ctx);
3547 #endif
3548 }
3549
3550 static void gen_hrfid(DisasContext *ctx)
3551 {
3552 #if defined(CONFIG_USER_ONLY)
3553 GEN_PRIV;
3554 #else
3555 /* Restore CPU state */
3556 CHK_HV;
3557 gen_helper_hrfid(cpu_env);
3558 gen_sync_exception(ctx);
3559 #endif
3560 }
3561 #endif
3562
3563 /* sc */
3564 #if defined(CONFIG_USER_ONLY)
3565 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3566 #else
3567 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3568 #endif
3569 static void gen_sc(DisasContext *ctx)
3570 {
3571 uint32_t lev;
3572
3573 lev = (ctx->opcode >> 5) & 0x7F;
3574 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3575 }
3576
3577 /*** Trap ***/
3578
3579 /* Check for unconditional traps (always or never) */
3580 static bool check_unconditional_trap(DisasContext *ctx)
3581 {
3582 /* Trap never */
3583 if (TO(ctx->opcode) == 0) {
3584 return true;
3585 }
3586 /* Trap always */
3587 if (TO(ctx->opcode) == 31) {
3588 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
3589 return true;
3590 }
3591 return false;
3592 }
3593
3594 /* tw */
3595 static void gen_tw(DisasContext *ctx)
3596 {
3597 TCGv_i32 t0;
3598
3599 if (check_unconditional_trap(ctx)) {
3600 return;
3601 }
3602 t0 = tcg_const_i32(TO(ctx->opcode));
3603 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3604 t0);
3605 tcg_temp_free_i32(t0);
3606 }
3607
3608 /* twi */
3609 static void gen_twi(DisasContext *ctx)
3610 {
3611 TCGv t0;
3612 TCGv_i32 t1;
3613
3614 if (check_unconditional_trap(ctx)) {
3615 return;
3616 }
3617 t0 = tcg_const_tl(SIMM(ctx->opcode));
3618 t1 = tcg_const_i32(TO(ctx->opcode));
3619 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3620 tcg_temp_free(t0);
3621 tcg_temp_free_i32(t1);
3622 }
3623
3624 #if defined(TARGET_PPC64)
3625 /* td */
3626 static void gen_td(DisasContext *ctx)
3627 {
3628 TCGv_i32 t0;
3629
3630 if (check_unconditional_trap(ctx)) {
3631 return;
3632 }
3633 t0 = tcg_const_i32(TO(ctx->opcode));
3634 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3635 t0);
3636 tcg_temp_free_i32(t0);
3637 }
3638
3639 /* tdi */
3640 static void gen_tdi(DisasContext *ctx)
3641 {
3642 TCGv t0;
3643 TCGv_i32 t1;
3644
3645 if (check_unconditional_trap(ctx)) {
3646 return;
3647 }
3648 t0 = tcg_const_tl(SIMM(ctx->opcode));
3649 t1 = tcg_const_i32(TO(ctx->opcode));
3650 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3651 tcg_temp_free(t0);
3652 tcg_temp_free_i32(t1);
3653 }
3654 #endif
3655
3656 /*** Processor control ***/
3657
3658 static void gen_read_xer(TCGv dst)
3659 {
3660 TCGv t0 = tcg_temp_new();
3661 TCGv t1 = tcg_temp_new();
3662 TCGv t2 = tcg_temp_new();
3663 tcg_gen_mov_tl(dst, cpu_xer);
3664 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3665 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3666 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3667 tcg_gen_or_tl(t0, t0, t1);
3668 tcg_gen_or_tl(dst, dst, t2);
3669 tcg_gen_or_tl(dst, dst, t0);
3670 tcg_temp_free(t0);
3671 tcg_temp_free(t1);
3672 tcg_temp_free(t2);
3673 }
3674
3675 static void gen_write_xer(TCGv src)
3676 {
3677 tcg_gen_andi_tl(cpu_xer, src,
3678 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3679 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3680 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3681 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3682 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3683 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3684 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3685 }
3686
3687 /* mcrxr */
3688 static void gen_mcrxr(DisasContext *ctx)
3689 {
3690 TCGv_i32 t0 = tcg_temp_new_i32();
3691 TCGv_i32 t1 = tcg_temp_new_i32();
3692 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3693
3694 tcg_gen_trunc_tl_i32(t0, cpu_so);
3695 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3696 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3697 tcg_gen_shli_i32(t0, t0, 3);
3698 tcg_gen_shli_i32(t1, t1, 2);
3699 tcg_gen_shli_i32(dst, dst, 1);
3700 tcg_gen_or_i32(dst, dst, t0);
3701 tcg_gen_or_i32(dst, dst, t1);
3702 tcg_temp_free_i32(t0);
3703 tcg_temp_free_i32(t1);
3704
3705 tcg_gen_movi_tl(cpu_so, 0);
3706 tcg_gen_movi_tl(cpu_ov, 0);
3707 tcg_gen_movi_tl(cpu_ca, 0);
3708 }
3709
3710 /* mfcr mfocrf */
3711 static void gen_mfcr(DisasContext *ctx)
3712 {
3713 uint32_t crm, crn;
3714
3715 if (likely(ctx->opcode & 0x00100000)) {
3716 crm = CRM(ctx->opcode);
3717 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3718 crn = ctz32 (crm);
3719 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3720 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3721 cpu_gpr[rD(ctx->opcode)], crn * 4);
3722 }
3723 } else {
3724 TCGv_i32 t0 = tcg_temp_new_i32();
3725 tcg_gen_mov_i32(t0, cpu_crf[0]);
3726 tcg_gen_shli_i32(t0, t0, 4);
3727 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3728 tcg_gen_shli_i32(t0, t0, 4);
3729 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3730 tcg_gen_shli_i32(t0, t0, 4);
3731 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3732 tcg_gen_shli_i32(t0, t0, 4);
3733 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3734 tcg_gen_shli_i32(t0, t0, 4);
3735 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3736 tcg_gen_shli_i32(t0, t0, 4);
3737 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3738 tcg_gen_shli_i32(t0, t0, 4);
3739 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3740 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3741 tcg_temp_free_i32(t0);
3742 }
3743 }
3744
3745 /* mfmsr */
3746 static void gen_mfmsr(DisasContext *ctx)
3747 {
3748 CHK_SV;
3749 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3750 }
3751
3752 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3753 {
3754 #if 0
3755 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3756 printf("ERROR: try to access SPR %d !\n", sprn);
3757 #endif
3758 }
3759 #define SPR_NOACCESS (&spr_noaccess)
3760
3761 /* mfspr */
3762 static inline void gen_op_mfspr(DisasContext *ctx)
3763 {
3764 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3765 uint32_t sprn = SPR(ctx->opcode);
3766
3767 #if defined(CONFIG_USER_ONLY)
3768 read_cb = ctx->spr_cb[sprn].uea_read;
3769 #else
3770 if (ctx->pr) {
3771 read_cb = ctx->spr_cb[sprn].uea_read;
3772 } else if (ctx->hv) {
3773 read_cb = ctx->spr_cb[sprn].hea_read;
3774 } else {
3775 read_cb = ctx->spr_cb[sprn].oea_read;
3776 }
3777 #endif
3778 if (likely(read_cb != NULL)) {
3779 if (likely(read_cb != SPR_NOACCESS)) {
3780 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3781 } else {
3782 /* Privilege exception */
3783 /* This is a hack to avoid warnings when running Linux:
3784 * this OS breaks the PowerPC virtualisation model,
3785 * allowing userland application to read the PVR
3786 */
3787 if (sprn != SPR_PVR) {
3788 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3789 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3790 if (qemu_log_separate()) {
3791 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3792 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3793 }
3794 }
3795 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3796 }
3797 } else {
3798 /* ISA 2.07 defines these as no-ops */
3799 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3800 (sprn >= 808 && sprn <= 811)) {
3801 /* This is a nop */
3802 return;
3803 }
3804 /* Not defined */
3805 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3806 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3807 if (qemu_log_separate()) {
3808 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3809 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3810 }
3811
3812 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3813 * it can generate a priv, a hv emu or a no-op
3814 */
3815 if (sprn & 0x10) {
3816 if (ctx->pr) {
3817 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3818 }
3819 } else {
3820 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3821 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3822 }
3823 }
3824 }
3825 }
3826
3827 static void gen_mfspr(DisasContext *ctx)
3828 {
3829 gen_op_mfspr(ctx);
3830 }
3831
3832 /* mftb */
3833 static void gen_mftb(DisasContext *ctx)
3834 {
3835 gen_op_mfspr(ctx);
3836 }
3837
3838 /* mtcrf mtocrf*/
3839 static void gen_mtcrf(DisasContext *ctx)
3840 {
3841 uint32_t crm, crn;
3842
3843 crm = CRM(ctx->opcode);
3844 if (likely((ctx->opcode & 0x00100000))) {
3845 if (crm && ((crm & (crm - 1)) == 0)) {
3846 TCGv_i32 temp = tcg_temp_new_i32();
3847 crn = ctz32 (crm);
3848 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3849 tcg_gen_shri_i32(temp, temp, crn * 4);
3850 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3851 tcg_temp_free_i32(temp);
3852 }
3853 } else {
3854 TCGv_i32 temp = tcg_temp_new_i32();
3855 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3856 for (crn = 0 ; crn < 8 ; crn++) {
3857 if (crm & (1 << crn)) {
3858 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3859 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3860 }
3861 }
3862 tcg_temp_free_i32(temp);
3863 }
3864 }
3865
3866 /* mtmsr */
3867 #if defined(TARGET_PPC64)
3868 static void gen_mtmsrd(DisasContext *ctx)
3869 {
3870 CHK_SV;
3871
3872 #if !defined(CONFIG_USER_ONLY)
3873 if (ctx->opcode & 0x00010000) {
3874 /* Special form that does not need any synchronisation */
3875 TCGv t0 = tcg_temp_new();
3876 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3877 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3878 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3879 tcg_temp_free(t0);
3880 } else {
3881 /* XXX: we need to update nip before the store
3882 * if we enter power saving mode, we will exit the loop
3883 * directly from ppc_store_msr
3884 */
3885 gen_update_nip(ctx, ctx->nip);
3886 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3887 /* Must stop the translation as machine state (may have) changed */
3888 /* Note that mtmsr is not always defined as context-synchronizing */
3889 gen_stop_exception(ctx);
3890 }
3891 #endif /* !defined(CONFIG_USER_ONLY) */
3892 }
3893 #endif /* defined(TARGET_PPC64) */
3894
3895 static void gen_mtmsr(DisasContext *ctx)
3896 {
3897 CHK_SV;
3898
3899 #if !defined(CONFIG_USER_ONLY)
3900 if (ctx->opcode & 0x00010000) {
3901 /* Special form that does not need any synchronisation */
3902 TCGv t0 = tcg_temp_new();
3903 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3904 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3905 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3906 tcg_temp_free(t0);
3907 } else {
3908 TCGv msr = tcg_temp_new();
3909
3910 /* XXX: we need to update nip before the store
3911 * if we enter power saving mode, we will exit the loop
3912 * directly from ppc_store_msr
3913 */
3914 gen_update_nip(ctx, ctx->nip);
3915 #if defined(TARGET_PPC64)
3916 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3917 #else
3918 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3919 #endif
3920 gen_helper_store_msr(cpu_env, msr);
3921 tcg_temp_free(msr);
3922 /* Must stop the translation as machine state (may have) changed */
3923 /* Note that mtmsr is not always defined as context-synchronizing */
3924 gen_stop_exception(ctx);
3925 }
3926 #endif
3927 }
3928
3929 /* mtspr */
3930 static void gen_mtspr(DisasContext *ctx)
3931 {
3932 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3933 uint32_t sprn = SPR(ctx->opcode);
3934
3935 #if defined(CONFIG_USER_ONLY)
3936 write_cb = ctx->spr_cb[sprn].uea_write;
3937 #else
3938 if (ctx->pr) {
3939 write_cb = ctx->spr_cb[sprn].uea_write;
3940 } else if (ctx->hv) {
3941 write_cb = ctx->spr_cb[sprn].hea_write;
3942 } else {
3943 write_cb = ctx->spr_cb[sprn].oea_write;
3944 }
3945 #endif
3946 if (likely(write_cb != NULL)) {
3947 if (likely(write_cb != SPR_NOACCESS)) {
3948 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3949 } else {
3950 /* Privilege exception */
3951 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3952 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3953 if (qemu_log_separate()) {
3954 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3955 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3956 }
3957 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3958 }
3959 } else {
3960 /* ISA 2.07 defines these as no-ops */
3961 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3962 (sprn >= 808 && sprn <= 811)) {
3963 /* This is a nop */
3964 return;
3965 }
3966
3967 /* Not defined */
3968 if (qemu_log_separate()) {
3969 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3970 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3971 }
3972 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3973 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3974
3975
3976 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3977 * it can generate a priv, a hv emu or a no-op
3978 */
3979 if (sprn & 0x10) {
3980 if (ctx->pr) {
3981 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3982 }
3983 } else {
3984 if (ctx->pr || sprn == 0) {
3985 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3986 }
3987 }
3988 }
3989 }
3990
3991 #if defined(TARGET_PPC64)
3992 /* setb */
3993 static void gen_setb(DisasContext *ctx)
3994 {
3995 TCGv_i32 t0 = tcg_temp_new_i32();
3996 TCGv_i32 t8 = tcg_temp_new_i32();
3997 TCGv_i32 tm1 = tcg_temp_new_i32();
3998 int crf = crfS(ctx->opcode);
3999
4000 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4001 tcg_gen_movi_i32(t8, 8);
4002 tcg_gen_movi_i32(tm1, -1);
4003 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4004 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4005
4006 tcg_temp_free_i32(t0);
4007 tcg_temp_free_i32(t8);
4008 tcg_temp_free_i32(tm1);
4009 }
4010 #endif
4011
4012 /*** Cache management ***/
4013
4014 /* dcbf */
4015 static void gen_dcbf(DisasContext *ctx)
4016 {
4017 /* XXX: specification says this is treated as a load by the MMU */
4018 TCGv t0;
4019 gen_set_access_type(ctx, ACCESS_CACHE);
4020 t0 = tcg_temp_new();
4021 gen_addr_reg_index(ctx, t0);
4022 gen_qemu_ld8u(ctx, t0, t0);
4023 tcg_temp_free(t0);
4024 }
4025
4026 /* dcbi (Supervisor only) */
4027 static void gen_dcbi(DisasContext *ctx)
4028 {
4029 #if defined(CONFIG_USER_ONLY)
4030 GEN_PRIV;
4031 #else
4032 TCGv EA, val;
4033
4034 CHK_SV;
4035 EA = tcg_temp_new();
4036 gen_set_access_type(ctx, ACCESS_CACHE);
4037 gen_addr_reg_index(ctx, EA);
4038 val = tcg_temp_new();
4039 /* XXX: specification says this should be treated as a store by the MMU */
4040 gen_qemu_ld8u(ctx, val, EA);
4041 gen_qemu_st8(ctx, val, EA);
4042 tcg_temp_free(val);
4043 tcg_temp_free(EA);
4044 #endif /* defined(CONFIG_USER_ONLY) */
4045 }
4046
4047 /* dcdst */
4048 static void gen_dcbst(DisasContext *ctx)
4049 {
4050 /* XXX: specification say this is treated as a load by the MMU */
4051 TCGv t0;
4052 gen_set_access_type(ctx, ACCESS_CACHE);
4053 t0 = tcg_temp_new();
4054 gen_addr_reg_index(ctx, t0);
4055 gen_qemu_ld8u(ctx, t0, t0);
4056 tcg_temp_free(t0);
4057 }
4058
4059 /* dcbt */
4060 static void gen_dcbt(DisasContext *ctx)
4061 {
4062 /* interpreted as no-op */
4063 /* XXX: specification say this is treated as a load by the MMU
4064 * but does not generate any exception
4065 */
4066 }
4067
4068 /* dcbtst */
4069 static void gen_dcbtst(DisasContext *ctx)
4070 {
4071 /* interpreted as no-op */
4072 /* XXX: specification say this is treated as a load by the MMU
4073 * but does not generate any exception
4074 */
4075 }
4076
4077 /* dcbtls */
4078 static void gen_dcbtls(DisasContext *ctx)
4079 {
4080 /* Always fails locking the cache */
4081 TCGv t0 = tcg_temp_new();
4082 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4083 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4084 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4085 tcg_temp_free(t0);
4086 }
4087
4088 /* dcbz */
4089 static void gen_dcbz(DisasContext *ctx)
4090 {
4091 TCGv tcgv_addr;
4092 TCGv_i32 tcgv_op;
4093
4094 gen_set_access_type(ctx, ACCESS_CACHE);
4095 tcgv_addr = tcg_temp_new();
4096 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4097 gen_addr_reg_index(ctx, tcgv_addr);
4098 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4099 tcg_temp_free(tcgv_addr);
4100 tcg_temp_free_i32(tcgv_op);
4101 }
4102
4103 /* dst / dstt */
4104 static void gen_dst(DisasContext *ctx)
4105 {
4106 if (rA(ctx->opcode) == 0) {
4107 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4108 } else {
4109 /* interpreted as no-op */
4110 }
4111 }
4112
4113 /* dstst /dststt */
4114 static void gen_dstst(DisasContext *ctx)
4115 {
4116 if (rA(ctx->opcode) == 0) {
4117 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4118 } else {
4119 /* interpreted as no-op */
4120 }
4121
4122 }
4123
4124 /* dss / dssall */
4125 static void gen_dss(DisasContext *ctx)
4126 {
4127 /* interpreted as no-op */
4128 }
4129
4130 /* icbi */
4131 static void gen_icbi(DisasContext *ctx)
4132 {
4133 TCGv t0;
4134 gen_set_access_type(ctx, ACCESS_CACHE);
4135 t0 = tcg_temp_new();
4136 gen_addr_reg_index(ctx, t0);
4137 gen_helper_icbi(cpu_env, t0);
4138 tcg_temp_free(t0);
4139 }
4140
4141 /* Optional: */
4142 /* dcba */
4143 static void gen_dcba(DisasContext *ctx)
4144 {
4145 /* interpreted as no-op */
4146 /* XXX: specification say this is treated as a store by the MMU
4147 * but does not generate any exception
4148 */
4149 }
4150
4151 /*** Segment register manipulation ***/
4152 /* Supervisor only: */
4153
4154 /* mfsr */
4155 static void gen_mfsr(DisasContext *ctx)
4156 {
4157 #if defined(CONFIG_USER_ONLY)
4158 GEN_PRIV;
4159 #else
4160 TCGv t0;
4161
4162 CHK_SV;
4163 t0 = tcg_const_tl(SR(ctx->opcode));
4164 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4165 tcg_temp_free(t0);
4166 #endif /* defined(CONFIG_USER_ONLY) */
4167 }
4168
4169 /* mfsrin */
4170 static void gen_mfsrin(DisasContext *ctx)
4171 {
4172 #if defined(CONFIG_USER_ONLY)
4173 GEN_PRIV;
4174 #else
4175 TCGv t0;
4176
4177 CHK_SV;
4178 t0 = tcg_temp_new();
4179 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4180 tcg_gen_andi_tl(t0, t0, 0xF);
4181 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4182 tcg_temp_free(t0);
4183 #endif /* defined(CONFIG_USER_ONLY) */
4184 }
4185
4186 /* mtsr */
4187 static void gen_mtsr(DisasContext *ctx)
4188 {
4189 #if defined(CONFIG_USER_ONLY)
4190 GEN_PRIV;
4191 #else
4192 TCGv t0;
4193
4194 CHK_SV;
4195 t0 = tcg_const_tl(SR(ctx->opcode));
4196 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4197 tcg_temp_free(t0);
4198 #endif /* defined(CONFIG_USER_ONLY) */
4199 }
4200
4201 /* mtsrin */
4202 static void gen_mtsrin(DisasContext *ctx)
4203 {
4204 #if defined(CONFIG_USER_ONLY)
4205 GEN_PRIV;
4206 #else
4207 TCGv t0;
4208 CHK_SV;
4209
4210 t0 = tcg_temp_new();
4211 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4212 tcg_gen_andi_tl(t0, t0, 0xF);
4213 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4214 tcg_temp_free(t0);
4215 #endif /* defined(CONFIG_USER_ONLY) */
4216 }
4217
4218 #if defined(TARGET_PPC64)
4219 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4220
4221 /* mfsr */
4222 static void gen_mfsr_64b(DisasContext *ctx)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 GEN_PRIV;
4226 #else
4227 TCGv t0;
4228
4229 CHK_SV;
4230 t0 = tcg_const_tl(SR(ctx->opcode));
4231 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4232 tcg_temp_free(t0);
4233 #endif /* defined(CONFIG_USER_ONLY) */
4234 }
4235
4236 /* mfsrin */
4237 static void gen_mfsrin_64b(DisasContext *ctx)
4238 {
4239 #if defined(CONFIG_USER_ONLY)
4240 GEN_PRIV;
4241 #else
4242 TCGv t0;
4243
4244 CHK_SV;
4245 t0 = tcg_temp_new();
4246 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4247 tcg_gen_andi_tl(t0, t0, 0xF);
4248 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4249 tcg_temp_free(t0);
4250 #endif /* defined(CONFIG_USER_ONLY) */
4251 }
4252
4253 /* mtsr */
4254 static void gen_mtsr_64b(DisasContext *ctx)
4255 {
4256 #if defined(CONFIG_USER_ONLY)
4257 GEN_PRIV;
4258 #else
4259 TCGv t0;
4260
4261 CHK_SV;
4262 t0 = tcg_const_tl(SR(ctx->opcode));
4263 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4264 tcg_temp_free(t0);
4265 #endif /* defined(CONFIG_USER_ONLY) */
4266 }
4267
4268 /* mtsrin */
4269 static void gen_mtsrin_64b(DisasContext *ctx)
4270 {
4271 #if defined(CONFIG_USER_ONLY)
4272 GEN_PRIV;
4273 #else
4274 TCGv t0;
4275
4276 CHK_SV;
4277 t0 = tcg_temp_new();
4278 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4279 tcg_gen_andi_tl(t0, t0, 0xF);
4280 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4281 tcg_temp_free(t0);
4282 #endif /* defined(CONFIG_USER_ONLY) */
4283 }
4284
4285 /* slbmte */
4286 static void gen_slbmte(DisasContext *ctx)
4287 {
4288 #if defined(CONFIG_USER_ONLY)
4289 GEN_PRIV;
4290 #else
4291 CHK_SV;
4292
4293 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4294 cpu_gpr[rS(ctx->opcode)]);
4295 #endif /* defined(CONFIG_USER_ONLY) */
4296 }
4297
4298 static void gen_slbmfee(DisasContext *ctx)
4299 {
4300 #if defined(CONFIG_USER_ONLY)
4301 GEN_PRIV;
4302 #else
4303 CHK_SV;
4304
4305 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4306 cpu_gpr[rB(ctx->opcode)]);
4307 #endif /* defined(CONFIG_USER_ONLY) */
4308 }
4309
4310 static void gen_slbmfev(DisasContext *ctx)
4311 {
4312 #if defined(CONFIG_USER_ONLY)
4313 GEN_PRIV;
4314 #else
4315 CHK_SV;
4316
4317 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4318 cpu_gpr[rB(ctx->opcode)]);
4319 #endif /* defined(CONFIG_USER_ONLY) */
4320 }
4321
4322 static void gen_slbfee_(DisasContext *ctx)
4323 {
4324 #if defined(CONFIG_USER_ONLY)
4325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4326 #else
4327 TCGLabel *l1, *l2;
4328
4329 if (unlikely(ctx->pr)) {
4330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4331 return;
4332 }
4333 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4334 cpu_gpr[rB(ctx->opcode)]);
4335 l1 = gen_new_label();
4336 l2 = gen_new_label();
4337 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4338 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4339 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4340 tcg_gen_br(l2);
4341 gen_set_label(l1);
4342 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4343 gen_set_label(l2);
4344 #endif
4345 }
4346 #endif /* defined(TARGET_PPC64) */
4347
4348 /*** Lookaside buffer management ***/
4349 /* Optional & supervisor only: */
4350
4351 /* tlbia */
4352 static void gen_tlbia(DisasContext *ctx)
4353 {
4354 #if defined(CONFIG_USER_ONLY)
4355 GEN_PRIV;
4356 #else
4357 CHK_HV;
4358
4359 gen_helper_tlbia(cpu_env);
4360 #endif /* defined(CONFIG_USER_ONLY) */
4361 }
4362
4363 /* tlbiel */
4364 static void gen_tlbiel(DisasContext *ctx)
4365 {
4366 #if defined(CONFIG_USER_ONLY)
4367 GEN_PRIV;
4368 #else
4369 CHK_SV;
4370
4371 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4372 #endif /* defined(CONFIG_USER_ONLY) */
4373 }
4374
4375 /* tlbie */
4376 static void gen_tlbie(DisasContext *ctx)
4377 {
4378 #if defined(CONFIG_USER_ONLY)
4379 GEN_PRIV;
4380 #else
4381 CHK_HV;
4382
4383 if (NARROW_MODE(ctx)) {
4384 TCGv t0 = tcg_temp_new();
4385 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4386 gen_helper_tlbie(cpu_env, t0);
4387 tcg_temp_free(t0);
4388 } else {
4389 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4390 }
4391 #endif /* defined(CONFIG_USER_ONLY) */
4392 }
4393
4394 /* tlbsync */
4395 static void gen_tlbsync(DisasContext *ctx)
4396 {
4397 #if defined(CONFIG_USER_ONLY)
4398 GEN_PRIV;
4399 #else
4400 CHK_HV;
4401
4402 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4403 * embedded however needs to deal with tlbsync. We don't try to be
4404 * fancy and swallow the overhead of checking for both.
4405 */
4406 gen_check_tlb_flush(ctx);
4407 #endif /* defined(CONFIG_USER_ONLY) */
4408 }
4409
4410 #if defined(TARGET_PPC64)
4411 /* slbia */
4412 static void gen_slbia(DisasContext *ctx)
4413 {
4414 #if defined(CONFIG_USER_ONLY)
4415 GEN_PRIV;
4416 #else
4417 CHK_SV;
4418
4419 gen_helper_slbia(cpu_env);
4420 #endif /* defined(CONFIG_USER_ONLY) */
4421 }
4422
4423 /* slbie */
4424 static void gen_slbie(DisasContext *ctx)
4425 {
4426 #if defined(CONFIG_USER_ONLY)
4427 GEN_PRIV;
4428 #else
4429 CHK_SV;
4430
4431 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4432 #endif /* defined(CONFIG_USER_ONLY) */
4433 }
4434 #endif /* defined(TARGET_PPC64) */
4435
4436 /*** External control ***/
4437 /* Optional: */
4438
4439 /* eciwx */
4440 static void gen_eciwx(DisasContext *ctx)
4441 {
4442 TCGv t0;
4443 /* Should check EAR[E] ! */
4444 gen_set_access_type(ctx, ACCESS_EXT);
4445 t0 = tcg_temp_new();
4446 gen_addr_reg_index(ctx, t0);
4447 gen_check_align(ctx, t0, 0x03);
4448 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4449 tcg_temp_free(t0);
4450 }
4451
4452 /* ecowx */
4453 static void gen_ecowx(DisasContext *ctx)
4454 {
4455 TCGv t0;
4456 /* Should check EAR[E] ! */
4457 gen_set_access_type(ctx, ACCESS_EXT);
4458 t0 = tcg_temp_new();
4459 gen_addr_reg_index(ctx, t0);
4460 gen_check_align(ctx, t0, 0x03);
4461 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4462 tcg_temp_free(t0);
4463 }
4464
4465 /* PowerPC 601 specific instructions */
4466
4467 /* abs - abs. */
4468 static void gen_abs(DisasContext *ctx)
4469 {
4470 TCGLabel *l1 = gen_new_label();
4471 TCGLabel *l2 = gen_new_label();
4472 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4473 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4474 tcg_gen_br(l2);
4475 gen_set_label(l1);
4476 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4477 gen_set_label(l2);
4478 if (unlikely(Rc(ctx->opcode) != 0))
4479 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4480 }
4481
4482 /* abso - abso. */
4483 static void gen_abso(DisasContext *ctx)
4484 {
4485 TCGLabel *l1 = gen_new_label();
4486 TCGLabel *l2 = gen_new_label();
4487 TCGLabel *l3 = gen_new_label();
4488 /* Start with XER OV disabled, the most likely case */
4489 tcg_gen_movi_tl(cpu_ov, 0);
4490 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4491 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4492 tcg_gen_movi_tl(cpu_ov, 1);
4493 tcg_gen_movi_tl(cpu_so, 1);
4494 tcg_gen_br(l2);
4495 gen_set_label(l1);
4496 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4497 tcg_gen_br(l3);
4498 gen_set_label(l2);
4499 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4500 gen_set_label(l3);
4501 if (unlikely(Rc(ctx->opcode) != 0))
4502 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4503 }
4504
4505 /* clcs */
4506 static void gen_clcs(DisasContext *ctx)
4507 {
4508 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4509 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4510 tcg_temp_free_i32(t0);
4511 /* Rc=1 sets CR0 to an undefined state */
4512 }
4513
4514 /* div - div. */
4515 static void gen_div(DisasContext *ctx)
4516 {
4517 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4518 cpu_gpr[rB(ctx->opcode)]);
4519 if (unlikely(Rc(ctx->opcode) != 0))
4520 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4521 }
4522
4523 /* divo - divo. */
4524 static void gen_divo(DisasContext *ctx)
4525 {
4526 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4527 cpu_gpr[rB(ctx->opcode)]);
4528 if (unlikely(Rc(ctx->opcode) != 0))
4529 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4530 }
4531
4532 /* divs - divs. */
4533 static void gen_divs(DisasContext *ctx)
4534 {
4535 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4536 cpu_gpr[rB(ctx->opcode)]);
4537 if (unlikely(Rc(ctx->opcode) != 0))
4538 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4539 }
4540
4541 /* divso - divso. */
4542 static void gen_divso(DisasContext *ctx)
4543 {
4544 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4545 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4546 if (unlikely(Rc(ctx->opcode) != 0))
4547 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4548 }
4549
4550 /* doz - doz. */
4551 static void gen_doz(DisasContext *ctx)
4552 {
4553 TCGLabel *l1 = gen_new_label();
4554 TCGLabel *l2 = gen_new_label();
4555 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4556 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4557 tcg_gen_br(l2);
4558 gen_set_label(l1);
4559 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4560 gen_set_label(l2);
4561 if (unlikely(Rc(ctx->opcode) != 0))
4562 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4563 }
4564
4565 /* dozo - dozo. */
4566 static void gen_dozo(DisasContext *ctx)
4567 {
4568 TCGLabel *l1 = gen_new_label();
4569 TCGLabel *l2 = gen_new_label();
4570 TCGv t0 = tcg_temp_new();
4571 TCGv t1 = tcg_temp_new();
4572 TCGv t2 = tcg_temp_new();
4573 /* Start with XER OV disabled, the most likely case */
4574 tcg_gen_movi_tl(cpu_ov, 0);
4575 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4576 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4577 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4578 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4579 tcg_gen_andc_tl(t1, t1, t2);
4580 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4581 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4582 tcg_gen_movi_tl(cpu_ov, 1);
4583 tcg_gen_movi_tl(cpu_so, 1);
4584 tcg_gen_br(l2);
4585 gen_set_label(l1);
4586 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4587 gen_set_label(l2);
4588 tcg_temp_free(t0);
4589 tcg_temp_free(t1);
4590 tcg_temp_free(t2);
4591 if (unlikely(Rc(ctx->opcode) != 0))
4592 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4593 }
4594
4595 /* dozi */
4596 static void gen_dozi(DisasContext *ctx)
4597 {
4598 target_long simm = SIMM(ctx->opcode);
4599 TCGLabel *l1 = gen_new_label();
4600 TCGLabel *l2 = gen_new_label();
4601 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4602 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4603 tcg_gen_br(l2);
4604 gen_set_label(l1);
4605 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4606 gen_set_label(l2);
4607 if (unlikely(Rc(ctx->opcode) != 0))
4608 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4609 }
4610
4611 /* lscbx - lscbx. */
4612 static void gen_lscbx(DisasContext *ctx)
4613 {
4614 TCGv t0 = tcg_temp_new();
4615 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4616 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4617 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4618
4619 gen_addr_reg_index(ctx, t0);
4620 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4621 tcg_temp_free_i32(t1);
4622 tcg_temp_free_i32(t2);
4623 tcg_temp_free_i32(t3);
4624 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4625 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4626 if (unlikely(Rc(ctx->opcode) != 0))
4627 gen_set_Rc0(ctx, t0);
4628 tcg_temp_free(t0);
4629 }
4630
4631 /* maskg - maskg. */
4632 static void gen_maskg(DisasContext *ctx)
4633 {
4634 TCGLabel *l1 = gen_new_label();
4635 TCGv t0 = tcg_temp_new();
4636 TCGv t1 = tcg_temp_new();
4637 TCGv t2 = tcg_temp_new();
4638 TCGv t3 = tcg_temp_new();
4639 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4640 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4641 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4642 tcg_gen_addi_tl(t2, t0, 1);
4643 tcg_gen_shr_tl(t2, t3, t2);
4644 tcg_gen_shr_tl(t3, t3, t1);
4645 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4646 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4647 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4648 gen_set_label(l1);
4649 tcg_temp_free(t0);
4650 tcg_temp_free(t1);
4651 tcg_temp_free(t2);
4652 tcg_temp_free(t3);
4653 if (unlikely(Rc(ctx->opcode) != 0))
4654 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4655 }
4656
4657 /* maskir - maskir. */
4658 static void gen_maskir(DisasContext *ctx)
4659 {
4660 TCGv t0 = tcg_temp_new();
4661 TCGv t1 = tcg_temp_new();
4662 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4663 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4664 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4665 tcg_temp_free(t0);
4666 tcg_temp_free(t1);
4667 if (unlikely(Rc(ctx->opcode) != 0))
4668 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4669 }
4670
4671 /* mul - mul. */
4672 static void gen_mul(DisasContext *ctx)
4673 {
4674 TCGv_i64 t0 = tcg_temp_new_i64();
4675 TCGv_i64 t1 = tcg_temp_new_i64();
4676 TCGv t2 = tcg_temp_new();
4677 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4678 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4679 tcg_gen_mul_i64(t0, t0, t1);
4680 tcg_gen_trunc_i64_tl(t2, t0);
4681 gen_store_spr(SPR_MQ, t2);
4682 tcg_gen_shri_i64(t1, t0, 32);
4683 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4684 tcg_temp_free_i64(t0);
4685 tcg_temp_free_i64(t1);
4686 tcg_temp_free(t2);
4687 if (unlikely(Rc(ctx->opcode) != 0))
4688 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4689 }
4690
4691 /* mulo - mulo. */
4692 static void gen_mulo(DisasContext *ctx)
4693 {
4694 TCGLabel *l1 = gen_new_label();
4695 TCGv_i64 t0 = tcg_temp_new_i64();
4696 TCGv_i64 t1 = tcg_temp_new_i64();
4697 TCGv t2 = tcg_temp_new();
4698 /* Start with XER OV disabled, the most likely case */
4699 tcg_gen_movi_tl(cpu_ov, 0);
4700 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4701 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4702 tcg_gen_mul_i64(t0, t0, t1);
4703 tcg_gen_trunc_i64_tl(t2, t0);
4704 gen_store_spr(SPR_MQ, t2);
4705 tcg_gen_shri_i64(t1, t0, 32);
4706 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4707 tcg_gen_ext32s_i64(t1, t0);
4708 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4709 tcg_gen_movi_tl(cpu_ov, 1);
4710 tcg_gen_movi_tl(cpu_so, 1);
4711 gen_set_label(l1);
4712 tcg_temp_free_i64(t0);
4713 tcg_temp_free_i64(t1);
4714 tcg_temp_free(t2);
4715 if (unlikely(Rc(ctx->opcode) != 0))
4716 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4717 }
4718
4719 /* nabs - nabs. */
4720 static void gen_nabs(DisasContext *ctx)
4721 {
4722 TCGLabel *l1 = gen_new_label();
4723 TCGLabel *l2 = gen_new_label();
4724 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4725 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4726 tcg_gen_br(l2);
4727 gen_set_label(l1);
4728 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4729 gen_set_label(l2);
4730 if (unlikely(Rc(ctx->opcode) != 0))
4731 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4732 }
4733
4734 /* nabso - nabso. */
4735 static void gen_nabso(DisasContext *ctx)
4736 {
4737 TCGLabel *l1 = gen_new_label();
4738 TCGLabel *l2 = gen_new_label();
4739 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4741 tcg_gen_br(l2);
4742 gen_set_label(l1);
4743 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4744 gen_set_label(l2);
4745 /* nabs never overflows */
4746 tcg_gen_movi_tl(cpu_ov, 0);
4747 if (unlikely(Rc(ctx->opcode) != 0))
4748 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4749 }
4750
4751 /* rlmi - rlmi. */
4752 static void gen_rlmi(DisasContext *ctx)
4753 {
4754 uint32_t mb = MB(ctx->opcode);
4755 uint32_t me = ME(ctx->opcode);
4756 TCGv t0 = tcg_temp_new();
4757 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4758 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4759 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4760 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4761 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4762 tcg_temp_free(t0);
4763 if (unlikely(Rc(ctx->opcode) != 0))
4764 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4765 }
4766
4767 /* rrib - rrib. */
4768 static void gen_rrib(DisasContext *ctx)
4769 {
4770 TCGv t0 = tcg_temp_new();
4771 TCGv t1 = tcg_temp_new();
4772 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4773 tcg_gen_movi_tl(t1, 0x80000000);
4774 tcg_gen_shr_tl(t1, t1, t0);
4775 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4776 tcg_gen_and_tl(t0, t0, t1);
4777 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4778 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4779 tcg_temp_free(t0);
4780 tcg_temp_free(t1);
4781 if (unlikely(Rc(ctx->opcode) != 0))
4782 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4783 }
4784
4785 /* sle - sle. */
4786 static void gen_sle(DisasContext *ctx)
4787 {
4788 TCGv t0 = tcg_temp_new();
4789 TCGv t1 = tcg_temp_new();
4790 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4791 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4792 tcg_gen_subfi_tl(t1, 32, t1);
4793 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4794 tcg_gen_or_tl(t1, t0, t1);
4795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4796 gen_store_spr(SPR_MQ, t1);
4797 tcg_temp_free(t0);
4798 tcg_temp_free(t1);
4799 if (unlikely(Rc(ctx->opcode) != 0))
4800 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4801 }
4802
4803 /* sleq - sleq. */
4804 static void gen_sleq(DisasContext *ctx)
4805 {
4806 TCGv t0 = tcg_temp_new();
4807 TCGv t1 = tcg_temp_new();
4808 TCGv t2 = tcg_temp_new();
4809 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4810 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4811 tcg_gen_shl_tl(t2, t2, t0);
4812 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4813 gen_load_spr(t1, SPR_MQ);
4814 gen_store_spr(SPR_MQ, t0);
4815 tcg_gen_and_tl(t0, t0, t2);
4816 tcg_gen_andc_tl(t1, t1, t2);
4817 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4818 tcg_temp_free(t0);
4819 tcg_temp_free(t1);
4820 tcg_temp_free(t2);
4821 if (unlikely(Rc(ctx->opcode) != 0))
4822 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4823 }
4824
4825 /* sliq - sliq. */
4826 static void gen_sliq(DisasContext *ctx)
4827 {
4828 int sh = SH(ctx->opcode);
4829 TCGv t0 = tcg_temp_new();
4830 TCGv t1 = tcg_temp_new();
4831 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4832 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4833 tcg_gen_or_tl(t1, t0, t1);
4834 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4835 gen_store_spr(SPR_MQ, t1);
4836 tcg_temp_free(t0);
4837 tcg_temp_free(t1);
4838 if (unlikely(Rc(ctx->opcode) != 0))
4839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4840 }
4841
4842 /* slliq - slliq. */
4843 static void gen_slliq(DisasContext *ctx)
4844 {
4845 int sh = SH(ctx->opcode);
4846 TCGv t0 = tcg_temp_new();
4847 TCGv t1 = tcg_temp_new();
4848 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4849 gen_load_spr(t1, SPR_MQ);
4850 gen_store_spr(SPR_MQ, t0);
4851 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4852 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4853 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4854 tcg_temp_free(t0);
4855 tcg_temp_free(t1);
4856 if (unlikely(Rc(ctx->opcode) != 0))
4857 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4858 }
4859
4860 /* sllq - sllq. */
4861 static void gen_sllq(DisasContext *ctx)
4862 {
4863 TCGLabel *l1 = gen_new_label();
4864 TCGLabel *l2 = gen_new_label();
4865 TCGv t0 = tcg_temp_local_new();
4866 TCGv t1 = tcg_temp_local_new();
4867 TCGv t2 = tcg_temp_local_new();
4868 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4869 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4870 tcg_gen_shl_tl(t1, t1, t2);
4871 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4872 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4873 gen_load_spr(t0, SPR_MQ);
4874 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4875 tcg_gen_br(l2);
4876 gen_set_label(l1);
4877 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4878 gen_load_spr(t2, SPR_MQ);
4879 tcg_gen_andc_tl(t1, t2, t1);
4880 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4881 gen_set_label(l2);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 tcg_temp_free(t2);
4885 if (unlikely(Rc(ctx->opcode) != 0))
4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4887 }
4888
4889 /* slq - slq. */
4890 static void gen_slq(DisasContext *ctx)
4891 {
4892 TCGLabel *l1 = gen_new_label();
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_new();
4895 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4896 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4897 tcg_gen_subfi_tl(t1, 32, t1);
4898 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4899 tcg_gen_or_tl(t1, t0, t1);
4900 gen_store_spr(SPR_MQ, t1);
4901 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4902 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4903 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4904 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4905 gen_set_label(l1);
4906 tcg_temp_free(t0);
4907 tcg_temp_free(t1);
4908 if (unlikely(Rc(ctx->opcode) != 0))
4909 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4910 }
4911
4912 /* sraiq - sraiq. */
4913 static void gen_sraiq(DisasContext *ctx)
4914 {
4915 int sh = SH(ctx->opcode);
4916 TCGLabel *l1 = gen_new_label();
4917 TCGv t0 = tcg_temp_new();
4918 TCGv t1 = tcg_temp_new();
4919 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4920 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4921 tcg_gen_or_tl(t0, t0, t1);
4922 gen_store_spr(SPR_MQ, t0);
4923 tcg_gen_movi_tl(cpu_ca, 0);
4924 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4925 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4926 tcg_gen_movi_tl(cpu_ca, 1);
4927 gen_set_label(l1);
4928 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4929 tcg_temp_free(t0);
4930 tcg_temp_free(t1);
4931 if (unlikely(Rc(ctx->opcode) != 0))
4932 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4933 }
4934
4935 /* sraq - sraq. */
4936 static void gen_sraq(DisasContext *ctx)
4937 {
4938 TCGLabel *l1 = gen_new_label();
4939 TCGLabel *l2 = gen_new_label();
4940 TCGv t0 = tcg_temp_new();
4941 TCGv t1 = tcg_temp_local_new();
4942 TCGv t2 = tcg_temp_local_new();
4943 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4944 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4945 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4946 tcg_gen_subfi_tl(t2, 32, t2);
4947 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4948 tcg_gen_or_tl(t0, t0, t2);
4949 gen_store_spr(SPR_MQ, t0);
4950 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4951 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4952 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4953 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4954 gen_set_label(l1);
4955 tcg_temp_free(t0);
4956 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4957 tcg_gen_movi_tl(cpu_ca, 0);
4958 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4959 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4960 tcg_gen_movi_tl(cpu_ca, 1);
4961 gen_set_label(l2);
4962 tcg_temp_free(t1);
4963 tcg_temp_free(t2);
4964 if (unlikely(Rc(ctx->opcode) != 0))
4965 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4966 }
4967
4968 /* sre - sre. */
4969 static void gen_sre(DisasContext *ctx)
4970 {
4971 TCGv t0 = tcg_temp_new();
4972 TCGv t1 = tcg_temp_new();
4973 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4974 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4975 tcg_gen_subfi_tl(t1, 32, t1);
4976 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4977 tcg_gen_or_tl(t1, t0, t1);
4978 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4979 gen_store_spr(SPR_MQ, t1);
4980 tcg_temp_free(t0);
4981 tcg_temp_free(t1);
4982 if (unlikely(Rc(ctx->opcode) != 0))
4983 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4984 }
4985
4986 /* srea - srea. */
4987 static void gen_srea(DisasContext *ctx)
4988 {
4989 TCGv t0 = tcg_temp_new();
4990 TCGv t1 = tcg_temp_new();
4991 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4992 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4993 gen_store_spr(SPR_MQ, t0);
4994 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4995 tcg_temp_free(t0);
4996 tcg_temp_free(t1);
4997 if (unlikely(Rc(ctx->opcode) != 0))
4998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4999 }
5000
5001 /* sreq */
5002 static void gen_sreq(DisasContext *ctx)
5003 {
5004 TCGv t0 = tcg_temp_new();
5005 TCGv t1 = tcg_temp_new();
5006 TCGv t2 = tcg_temp_new();
5007 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5009 tcg_gen_shr_tl(t1, t1, t0);
5010 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5011 gen_load_spr(t2, SPR_MQ);
5012 gen_store_spr(SPR_MQ, t0);
5013 tcg_gen_and_tl(t0, t0, t1);
5014 tcg_gen_andc_tl(t2, t2, t1);
5015 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5016 tcg_temp_free(t0);
5017 tcg_temp_free(t1);
5018 tcg_temp_free(t2);
5019 if (unlikely(Rc(ctx->opcode) != 0))
5020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5021 }
5022
5023 /* sriq */
5024 static void gen_sriq(DisasContext *ctx)
5025 {
5026 int sh = SH(ctx->opcode);
5027 TCGv t0 = tcg_temp_new();
5028 TCGv t1 = tcg_temp_new();
5029 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5030 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5031 tcg_gen_or_tl(t1, t0, t1);
5032 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5033 gen_store_spr(SPR_MQ, t1);
5034 tcg_temp_free(t0);
5035 tcg_temp_free(t1);
5036 if (unlikely(Rc(ctx->opcode) != 0))
5037 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5038 }
5039
5040 /* srliq */
5041 static void gen_srliq(DisasContext *ctx)
5042 {
5043 int sh = SH(ctx->opcode);
5044 TCGv t0 = tcg_temp_new();
5045 TCGv t1 = tcg_temp_new();
5046 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5047 gen_load_spr(t1, SPR_MQ);
5048 gen_store_spr(SPR_MQ, t0);
5049 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5050 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5051 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5052 tcg_temp_free(t0);
5053 tcg_temp_free(t1);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* srlq */
5059 static void gen_srlq(DisasContext *ctx)
5060 {
5061 TCGLabel *l1 = gen_new_label();
5062 TCGLabel *l2 = gen_new_label();
5063 TCGv t0 = tcg_temp_local_new();
5064 TCGv t1 = tcg_temp_local_new();
5065 TCGv t2 = tcg_temp_local_new();
5066 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5067 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5068 tcg_gen_shr_tl(t2, t1, t2);
5069 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5070 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5071 gen_load_spr(t0, SPR_MQ);
5072 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5073 tcg_gen_br(l2);
5074 gen_set_label(l1);
5075 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5076 tcg_gen_and_tl(t0, t0, t2);
5077 gen_load_spr(t1, SPR_MQ);
5078 tcg_gen_andc_tl(t1, t1, t2);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5080 gen_set_label(l2);
5081 tcg_temp_free(t0);
5082 tcg_temp_free(t1);
5083 tcg_temp_free(t2);
5084 if (unlikely(Rc(ctx->opcode) != 0))
5085 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5086 }
5087
5088 /* srq */
5089 static void gen_srq(DisasContext *ctx)
5090 {
5091 TCGLabel *l1 = gen_new_label();
5092 TCGv t0 = tcg_temp_new();
5093 TCGv t1 = tcg_temp_new();
5094 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5095 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5096 tcg_gen_subfi_tl(t1, 32, t1);
5097 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5098 tcg_gen_or_tl(t1, t0, t1);
5099 gen_store_spr(SPR_MQ, t1);
5100 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5101 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5102 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5103 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5104 gen_set_label(l1);
5105 tcg_temp_free(t0);
5106 tcg_temp_free(t1);
5107 if (unlikely(Rc(ctx->opcode) != 0))
5108 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5109 }
5110
5111 /* PowerPC 602 specific instructions */
5112
5113 /* dsa */
5114 static void gen_dsa(DisasContext *ctx)
5115 {
5116 /* XXX: TODO */
5117 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5118 }
5119
5120 /* esa */
5121 static void gen_esa(DisasContext *ctx)
5122 {
5123 /* XXX: TODO */
5124 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5125 }
5126
5127 /* mfrom */
5128 static void gen_mfrom(DisasContext *ctx)
5129 {
5130 #if defined(CONFIG_USER_ONLY)
5131 GEN_PRIV;
5132 #else
5133 CHK_SV;
5134 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5135 #endif /* defined(CONFIG_USER_ONLY) */
5136 }
5137
5138 /* 602 - 603 - G2 TLB management */
5139
5140 /* tlbld */
5141 static void gen_tlbld_6xx(DisasContext *ctx)
5142 {
5143 #if defined(CONFIG_USER_ONLY)
5144 GEN_PRIV;
5145 #else
5146 CHK_SV;
5147 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5148 #endif /* defined(CONFIG_USER_ONLY) */
5149 }
5150
5151 /* tlbli */
5152 static void gen_tlbli_6xx(DisasContext *ctx)
5153 {
5154 #if defined(CONFIG_USER_ONLY)
5155 GEN_PRIV;
5156 #else
5157 CHK_SV;
5158 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5159 #endif /* defined(CONFIG_USER_ONLY) */
5160 }
5161
5162 /* 74xx TLB management */
5163
5164 /* tlbld */
5165 static void gen_tlbld_74xx(DisasContext *ctx)
5166 {
5167 #if defined(CONFIG_USER_ONLY)
5168 GEN_PRIV;
5169 #else
5170 CHK_SV;
5171 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5172 #endif /* defined(CONFIG_USER_ONLY) */
5173 }
5174
5175 /* tlbli */
5176 static void gen_tlbli_74xx(DisasContext *ctx)
5177 {
5178 #if defined(CONFIG_USER_ONLY)
5179 GEN_PRIV;
5180 #else
5181 CHK_SV;
5182 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5183 #endif /* defined(CONFIG_USER_ONLY) */
5184 }
5185
5186 /* POWER instructions not in PowerPC 601 */
5187
5188 /* clf */
5189 static void gen_clf(DisasContext *ctx)
5190 {
5191 /* Cache line flush: implemented as no-op */
5192 }
5193
5194 /* cli */
5195 static void gen_cli(DisasContext *ctx)
5196 {
5197 #if defined(CONFIG_USER_ONLY)
5198 GEN_PRIV;
5199 #else
5200 /* Cache line invalidate: privileged and treated as no-op */
5201 CHK_SV;
5202 #endif /* defined(CONFIG_USER_ONLY) */
5203 }
5204
5205 /* dclst */
5206 static void gen_dclst(DisasContext *ctx)
5207 {
5208 /* Data cache line store: treated as no-op */
5209 }
5210
5211 static void gen_mfsri(DisasContext *ctx)
5212 {
5213 #if defined(CONFIG_USER_ONLY)
5214 GEN_PRIV;
5215 #else
5216 int ra = rA(ctx->opcode);
5217 int rd = rD(ctx->opcode);
5218 TCGv t0;
5219
5220 CHK_SV;
5221 t0 = tcg_temp_new();
5222 gen_addr_reg_index(ctx, t0);
5223 tcg_gen_shri_tl(t0, t0, 28);
5224 tcg_gen_andi_tl(t0, t0, 0xF);
5225 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5226 tcg_temp_free(t0);
5227 if (ra != 0 && ra != rd)
5228 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5229 #endif /* defined(CONFIG_USER_ONLY) */
5230 }
5231
5232 static void gen_rac(DisasContext *ctx)
5233 {
5234 #if defined(CONFIG_USER_ONLY)
5235 GEN_PRIV;
5236 #else
5237 TCGv t0;
5238
5239 CHK_SV;
5240 t0 = tcg_temp_new();
5241 gen_addr_reg_index(ctx, t0);
5242 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5243 tcg_temp_free(t0);
5244 #endif /* defined(CONFIG_USER_ONLY) */
5245 }
5246
5247 static void gen_rfsvc(DisasContext *ctx)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250 GEN_PRIV;
5251 #else
5252 CHK_SV;
5253
5254 gen_helper_rfsvc(cpu_env);
5255 gen_sync_exception(ctx);
5256 #endif /* defined(CONFIG_USER_ONLY) */
5257 }
5258
5259 #include "translate/fp-impl.c"
5260
5261 #include "translate/vmx-impl.c"
5262
5263 #include "translate/vsx-impl.c"
5264
5265 /* svc is not implemented for now */
5266
5267 /* BookE specific instructions */
5268
5269 /* XXX: not implemented on 440 ? */
5270 static void gen_mfapidi(DisasContext *ctx)
5271 {
5272 /* XXX: TODO */
5273 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5274 }
5275
5276 /* XXX: not implemented on 440 ? */
5277 static void gen_tlbiva(DisasContext *ctx)
5278 {
5279 #if defined(CONFIG_USER_ONLY)
5280 GEN_PRIV;
5281 #else
5282 TCGv t0;
5283
5284 CHK_SV;
5285 t0 = tcg_temp_new();
5286 gen_addr_reg_index(ctx, t0);
5287 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5288 tcg_temp_free(t0);
5289 #endif /* defined(CONFIG_USER_ONLY) */
5290 }
5291
5292 /* All 405 MAC instructions are translated here */
5293 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5294 int ra, int rb, int rt, int Rc)
5295 {
5296 TCGv t0, t1;
5297
5298 t0 = tcg_temp_local_new();
5299 t1 = tcg_temp_local_new();
5300
5301 switch (opc3 & 0x0D) {
5302 case 0x05:
5303 /* macchw - macchw. - macchwo - macchwo. */
5304 /* macchws - macchws. - macchwso - macchwso. */
5305 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5306 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5307 /* mulchw - mulchw. */
5308 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5309 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5310 tcg_gen_ext16s_tl(t1, t1);
5311 break;
5312 case 0x04:
5313 /* macchwu - macchwu. - macchwuo - macchwuo. */
5314 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5315 /* mulchwu - mulchwu. */
5316 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5317 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5318 tcg_gen_ext16u_tl(t1, t1);
5319 break;
5320 case 0x01:
5321 /* machhw - machhw. - machhwo - machhwo. */
5322 /* machhws - machhws. - machhwso - machhwso. */
5323 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5324 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5325 /* mulhhw - mulhhw. */
5326 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5327 tcg_gen_ext16s_tl(t0, t0);
5328 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5329 tcg_gen_ext16s_tl(t1, t1);
5330 break;
5331 case 0x00:
5332 /* machhwu - machhwu. - machhwuo - machhwuo. */
5333 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5334 /* mulhhwu - mulhhwu. */
5335 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5336 tcg_gen_ext16u_tl(t0, t0);
5337 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5338 tcg_gen_ext16u_tl(t1, t1);
5339 break;
5340 case 0x0D:
5341 /* maclhw - maclhw. - maclhwo - maclhwo. */
5342 /* maclhws - maclhws. - maclhwso - maclhwso. */
5343 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5344 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5345 /* mullhw - mullhw. */
5346 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5347 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5348 break;
5349 case 0x0C:
5350 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5351 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5352 /* mullhwu - mullhwu. */
5353 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5354 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5355 break;
5356 }
5357 if (opc2 & 0x04) {
5358 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5359 tcg_gen_mul_tl(t1, t0, t1);
5360 if (opc2 & 0x02) {
5361 /* nmultiply-and-accumulate (0x0E) */
5362 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5363 } else {
5364 /* multiply-and-accumulate (0x0C) */
5365 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5366 }
5367
5368 if (opc3 & 0x12) {
5369 /* Check overflow and/or saturate */
5370 TCGLabel *l1 = gen_new_label();
5371
5372 if (opc3 & 0x10) {
5373 /* Start with XER OV disabled, the most likely case */
5374 tcg_gen_movi_tl(cpu_ov, 0);
5375 }
5376 if (opc3 & 0x01) {
5377 /* Signed */
5378 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5379 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5380 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5381 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5382 if (opc3 & 0x02) {
5383 /* Saturate */
5384 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5385 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5386 }
5387 } else {
5388 /* Unsigned */
5389 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5390 if (opc3 & 0x02) {
5391 /* Saturate */
5392 tcg_gen_movi_tl(t0, UINT32_MAX);
5393 }
5394 }
5395 if (opc3 & 0x10) {
5396 /* Check overflow */
5397 tcg_gen_movi_tl(cpu_ov, 1);
5398 tcg_gen_movi_tl(cpu_so, 1);
5399 }
5400 gen_set_label(l1);
5401 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5402 }
5403 } else {
5404 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5405 }
5406 tcg_temp_free(t0);
5407 tcg_temp_free(t1);
5408 if (unlikely(Rc) != 0) {
5409 /* Update Rc0 */
5410 gen_set_Rc0(ctx, cpu_gpr[rt]);
5411 }
5412 }
5413
5414 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5415 static void glue(gen_, name)(DisasContext *ctx) \
5416 { \
5417 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5418 rD(ctx->opcode), Rc(ctx->opcode)); \
5419 }
5420
5421 /* macchw - macchw. */
5422 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5423 /* macchwo - macchwo. */
5424 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5425 /* macchws - macchws. */
5426 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5427 /* macchwso - macchwso. */
5428 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5429 /* macchwsu - macchwsu. */
5430 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5431 /* macchwsuo - macchwsuo. */
5432 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5433 /* macchwu - macchwu. */
5434 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5435 /* macchwuo - macchwuo. */
5436 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5437 /* machhw - machhw. */
5438 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5439 /* machhwo - machhwo. */
5440 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5441 /* machhws - machhws. */
5442 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5443 /* machhwso - machhwso. */
5444 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5445 /* machhwsu - machhwsu. */
5446 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5447 /* machhwsuo - machhwsuo. */
5448 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5449 /* machhwu - machhwu. */
5450 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5451 /* machhwuo - machhwuo. */
5452 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5453 /* maclhw - maclhw. */
5454 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5455 /* maclhwo - maclhwo. */
5456 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5457 /* maclhws - maclhws. */
5458 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5459 /* maclhwso - maclhwso. */
5460 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5461 /* maclhwu - maclhwu. */
5462 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5463 /* maclhwuo - maclhwuo. */
5464 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5465 /* maclhwsu - maclhwsu. */
5466 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5467 /* maclhwsuo - maclhwsuo. */
5468 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5469 /* nmacchw - nmacchw. */
5470 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5471 /* nmacchwo - nmacchwo. */
5472 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5473 /* nmacchws - nmacchws. */
5474 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5475 /* nmacchwso - nmacchwso. */
5476 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5477 /* nmachhw - nmachhw. */
5478 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5479 /* nmachhwo - nmachhwo. */
5480 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5481 /* nmachhws - nmachhws. */
5482 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5483 /* nmachhwso - nmachhwso. */
5484 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5485 /* nmaclhw - nmaclhw. */
5486 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5487 /* nmaclhwo - nmaclhwo. */
5488 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5489 /* nmaclhws - nmaclhws. */
5490 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5491 /* nmaclhwso - nmaclhwso. */
5492 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5493
5494 /* mulchw - mulchw. */
5495 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5496 /* mulchwu - mulchwu. */
5497 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5498 /* mulhhw - mulhhw. */
5499 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5500 /* mulhhwu - mulhhwu. */
5501 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5502 /* mullhw - mullhw. */
5503 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5504 /* mullhwu - mullhwu. */
5505 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5506
5507 /* mfdcr */
5508 static void gen_mfdcr(DisasContext *ctx)
5509 {
5510 #if defined(CONFIG_USER_ONLY)
5511 GEN_PRIV;
5512 #else
5513 TCGv dcrn;
5514
5515 CHK_SV;
5516 dcrn = tcg_const_tl(SPR(ctx->opcode));
5517 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5518 tcg_temp_free(dcrn);
5519 #endif /* defined(CONFIG_USER_ONLY) */
5520 }
5521
5522 /* mtdcr */
5523 static void gen_mtdcr(DisasContext *ctx)
5524 {
5525 #if defined(CONFIG_USER_ONLY)
5526 GEN_PRIV;
5527 #else
5528 TCGv dcrn;
5529
5530 CHK_SV;
5531 dcrn = tcg_const_tl(SPR(ctx->opcode));
5532 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5533 tcg_temp_free(dcrn);
5534 #endif /* defined(CONFIG_USER_ONLY) */
5535 }
5536
5537 /* mfdcrx */
5538 /* XXX: not implemented on 440 ? */
5539 static void gen_mfdcrx(DisasContext *ctx)
5540 {
5541 #if defined(CONFIG_USER_ONLY)
5542 GEN_PRIV;
5543 #else
5544 CHK_SV;
5545 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5546 cpu_gpr[rA(ctx->opcode)]);
5547 /* Note: Rc update flag set leads to undefined state of Rc0 */
5548 #endif /* defined(CONFIG_USER_ONLY) */
5549 }
5550
5551 /* mtdcrx */
5552 /* XXX: not implemented on 440 ? */
5553 static void gen_mtdcrx(DisasContext *ctx)
5554 {
5555 #if defined(CONFIG_USER_ONLY)
5556 GEN_PRIV;
5557 #else
5558 CHK_SV;
5559 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5560 cpu_gpr[rS(ctx->opcode)]);
5561 /* Note: Rc update flag set leads to undefined state of Rc0 */
5562 #endif /* defined(CONFIG_USER_ONLY) */
5563 }
5564
5565 /* mfdcrux (PPC 460) : user-mode access to DCR */
5566 static void gen_mfdcrux(DisasContext *ctx)
5567 {
5568 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5569 cpu_gpr[rA(ctx->opcode)]);
5570 /* Note: Rc update flag set leads to undefined state of Rc0 */
5571 }
5572
5573 /* mtdcrux (PPC 460) : user-mode access to DCR */
5574 static void gen_mtdcrux(DisasContext *ctx)
5575 {
5576 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5577 cpu_gpr[rS(ctx->opcode)]);
5578 /* Note: Rc update flag set leads to undefined state of Rc0 */
5579 }
5580
5581 /* dccci */
5582 static void gen_dccci(DisasContext *ctx)
5583 {
5584 CHK_SV;
5585 /* interpreted as no-op */
5586 }
5587
5588 /* dcread */
5589 static void gen_dcread(DisasContext *ctx)
5590 {
5591 #if defined(CONFIG_USER_ONLY)
5592 GEN_PRIV;
5593 #else
5594 TCGv EA, val;
5595
5596 CHK_SV;
5597 gen_set_access_type(ctx, ACCESS_CACHE);
5598 EA = tcg_temp_new();
5599 gen_addr_reg_index(ctx, EA);
5600 val = tcg_temp_new();
5601 gen_qemu_ld32u(ctx, val, EA);
5602 tcg_temp_free(val);
5603 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5604 tcg_temp_free(EA);
5605 #endif /* defined(CONFIG_USER_ONLY) */
5606 }
5607
5608 /* icbt */
5609 static void gen_icbt_40x(DisasContext *ctx)
5610 {
5611 /* interpreted as no-op */
5612 /* XXX: specification say this is treated as a load by the MMU
5613 * but does not generate any exception
5614 */
5615 }
5616
5617 /* iccci */
5618 static void gen_iccci(DisasContext *ctx)
5619 {
5620 CHK_SV;
5621 /* interpreted as no-op */
5622 }
5623
5624 /* icread */
5625 static void gen_icread(DisasContext *ctx)
5626 {
5627 CHK_SV;
5628 /* interpreted as no-op */
5629 }
5630
5631 /* rfci (supervisor only) */
5632 static void gen_rfci_40x(DisasContext *ctx)
5633 {
5634 #if defined(CONFIG_USER_ONLY)
5635 GEN_PRIV;
5636 #else
5637 CHK_SV;
5638 /* Restore CPU state */
5639 gen_helper_40x_rfci(cpu_env);
5640 gen_sync_exception(ctx);
5641 #endif /* defined(CONFIG_USER_ONLY) */
5642 }
5643
5644 static void gen_rfci(DisasContext *ctx)
5645 {
5646 #if defined(CONFIG_USER_ONLY)
5647 GEN_PRIV;
5648 #else
5649 CHK_SV;
5650 /* Restore CPU state */
5651 gen_helper_rfci(cpu_env);
5652 gen_sync_exception(ctx);
5653 #endif /* defined(CONFIG_USER_ONLY) */
5654 }
5655
5656 /* BookE specific */
5657
5658 /* XXX: not implemented on 440 ? */
5659 static void gen_rfdi(DisasContext *ctx)
5660 {
5661 #if defined(CONFIG_USER_ONLY)
5662 GEN_PRIV;
5663 #else
5664 CHK_SV;
5665 /* Restore CPU state */
5666 gen_helper_rfdi(cpu_env);
5667 gen_sync_exception(ctx);
5668 #endif /* defined(CONFIG_USER_ONLY) */
5669 }
5670
5671 /* XXX: not implemented on 440 ? */
5672 static void gen_rfmci(DisasContext *ctx)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675 GEN_PRIV;
5676 #else
5677 CHK_SV;
5678 /* Restore CPU state */
5679 gen_helper_rfmci(cpu_env);
5680 gen_sync_exception(ctx);
5681 #endif /* defined(CONFIG_USER_ONLY) */
5682 }
5683
5684 /* TLB management - PowerPC 405 implementation */
5685
5686 /* tlbre */
5687 static void gen_tlbre_40x(DisasContext *ctx)
5688 {
5689 #if defined(CONFIG_USER_ONLY)
5690 GEN_PRIV;
5691 #else
5692 CHK_SV;
5693 switch (rB(ctx->opcode)) {
5694 case 0:
5695 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5696 cpu_gpr[rA(ctx->opcode)]);
5697 break;
5698 case 1:
5699 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5700 cpu_gpr[rA(ctx->opcode)]);
5701 break;
5702 default:
5703 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5704 break;
5705 }
5706 #endif /* defined(CONFIG_USER_ONLY) */
5707 }
5708
5709 /* tlbsx - tlbsx. */
5710 static void gen_tlbsx_40x(DisasContext *ctx)
5711 {
5712 #if defined(CONFIG_USER_ONLY)
5713 GEN_PRIV;
5714 #else
5715 TCGv t0;
5716
5717 CHK_SV;
5718 t0 = tcg_temp_new();
5719 gen_addr_reg_index(ctx, t0);
5720 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5721 tcg_temp_free(t0);
5722 if (Rc(ctx->opcode)) {
5723 TCGLabel *l1 = gen_new_label();
5724 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5725 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5726 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5727 gen_set_label(l1);
5728 }
5729 #endif /* defined(CONFIG_USER_ONLY) */
5730 }
5731
5732 /* tlbwe */
5733 static void gen_tlbwe_40x(DisasContext *ctx)
5734 {
5735 #if defined(CONFIG_USER_ONLY)
5736 GEN_PRIV;
5737 #else
5738 CHK_SV;
5739
5740 switch (rB(ctx->opcode)) {
5741 case 0:
5742 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5743 cpu_gpr[rS(ctx->opcode)]);
5744 break;
5745 case 1:
5746 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5747 cpu_gpr[rS(ctx->opcode)]);
5748 break;
5749 default:
5750 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5751 break;
5752 }
5753 #endif /* defined(CONFIG_USER_ONLY) */
5754 }
5755
5756 /* TLB management - PowerPC 440 implementation */
5757
5758 /* tlbre */
5759 static void gen_tlbre_440(DisasContext *ctx)
5760 {
5761 #if defined(CONFIG_USER_ONLY)
5762 GEN_PRIV;
5763 #else
5764 CHK_SV;
5765
5766 switch (rB(ctx->opcode)) {
5767 case 0:
5768 case 1:
5769 case 2:
5770 {
5771 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5772 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5773 t0, cpu_gpr[rA(ctx->opcode)]);
5774 tcg_temp_free_i32(t0);
5775 }
5776 break;
5777 default:
5778 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5779 break;
5780 }
5781 #endif /* defined(CONFIG_USER_ONLY) */
5782 }
5783
5784 /* tlbsx - tlbsx. */
5785 static void gen_tlbsx_440(DisasContext *ctx)
5786 {
5787 #if defined(CONFIG_USER_ONLY)
5788 GEN_PRIV;
5789 #else
5790 TCGv t0;
5791
5792 CHK_SV;
5793 t0 = tcg_temp_new();
5794 gen_addr_reg_index(ctx, t0);
5795 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5796 tcg_temp_free(t0);
5797 if (Rc(ctx->opcode)) {
5798 TCGLabel *l1 = gen_new_label();
5799 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5800 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5801 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5802 gen_set_label(l1);
5803 }
5804 #endif /* defined(CONFIG_USER_ONLY) */
5805 }
5806
5807 /* tlbwe */
5808 static void gen_tlbwe_440(DisasContext *ctx)
5809 {
5810 #if defined(CONFIG_USER_ONLY)
5811 GEN_PRIV;
5812 #else
5813 CHK_SV;
5814 switch (rB(ctx->opcode)) {
5815 case 0:
5816 case 1:
5817 case 2:
5818 {
5819 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5820 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5821 cpu_gpr[rS(ctx->opcode)]);
5822 tcg_temp_free_i32(t0);
5823 }
5824 break;
5825 default:
5826 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5827 break;
5828 }
5829 #endif /* defined(CONFIG_USER_ONLY) */
5830 }
5831
5832 /* TLB management - PowerPC BookE 2.06 implementation */
5833
5834 /* tlbre */
5835 static void gen_tlbre_booke206(DisasContext *ctx)
5836 {
5837 #if defined(CONFIG_USER_ONLY)
5838 GEN_PRIV;
5839 #else
5840 CHK_SV;
5841 gen_helper_booke206_tlbre(cpu_env);
5842 #endif /* defined(CONFIG_USER_ONLY) */
5843 }
5844
5845 /* tlbsx - tlbsx. */
5846 static void gen_tlbsx_booke206(DisasContext *ctx)
5847 {
5848 #if defined(CONFIG_USER_ONLY)
5849 GEN_PRIV;
5850 #else
5851 TCGv t0;
5852
5853 CHK_SV;
5854 if (rA(ctx->opcode)) {
5855 t0 = tcg_temp_new();
5856 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5857 } else {
5858 t0 = tcg_const_tl(0);
5859 }
5860
5861 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5862 gen_helper_booke206_tlbsx(cpu_env, t0);
5863 tcg_temp_free(t0);
5864 #endif /* defined(CONFIG_USER_ONLY) */
5865 }
5866
5867 /* tlbwe */
5868 static void gen_tlbwe_booke206(DisasContext *ctx)
5869 {
5870 #if defined(CONFIG_USER_ONLY)
5871 GEN_PRIV;
5872 #else
5873 CHK_SV;
5874 gen_helper_booke206_tlbwe(cpu_env);
5875 #endif /* defined(CONFIG_USER_ONLY) */
5876 }
5877
5878 static void gen_tlbivax_booke206(DisasContext *ctx)
5879 {
5880 #if defined(CONFIG_USER_ONLY)
5881 GEN_PRIV;
5882 #else
5883 TCGv t0;
5884
5885 CHK_SV;
5886 t0 = tcg_temp_new();
5887 gen_addr_reg_index(ctx, t0);
5888 gen_helper_booke206_tlbivax(cpu_env, t0);
5889 tcg_temp_free(t0);
5890 #endif /* defined(CONFIG_USER_ONLY) */
5891 }
5892
5893 static void gen_tlbilx_booke206(DisasContext *ctx)
5894 {
5895 #if defined(CONFIG_USER_ONLY)
5896 GEN_PRIV;
5897 #else
5898 TCGv t0;
5899
5900 CHK_SV;
5901 t0 = tcg_temp_new();
5902 gen_addr_reg_index(ctx, t0);
5903
5904 switch((ctx->opcode >> 21) & 0x3) {
5905 case 0:
5906 gen_helper_booke206_tlbilx0(cpu_env, t0);
5907 break;
5908 case 1:
5909 gen_helper_booke206_tlbilx1(cpu_env, t0);
5910 break;
5911 case 3:
5912 gen_helper_booke206_tlbilx3(cpu_env, t0);
5913 break;
5914 default:
5915 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5916 break;
5917 }
5918
5919 tcg_temp_free(t0);
5920 #endif /* defined(CONFIG_USER_ONLY) */
5921 }
5922
5923
5924 /* wrtee */
5925 static void gen_wrtee(DisasContext *ctx)
5926 {
5927 #if defined(CONFIG_USER_ONLY)
5928 GEN_PRIV;
5929 #else
5930 TCGv t0;
5931
5932 CHK_SV;
5933 t0 = tcg_temp_new();
5934 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5935 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5936 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5937 tcg_temp_free(t0);
5938 /* Stop translation to have a chance to raise an exception
5939 * if we just set msr_ee to 1
5940 */
5941 gen_stop_exception(ctx);
5942 #endif /* defined(CONFIG_USER_ONLY) */
5943 }
5944
5945 /* wrteei */
5946 static void gen_wrteei(DisasContext *ctx)
5947 {
5948 #if defined(CONFIG_USER_ONLY)
5949 GEN_PRIV;
5950 #else
5951 CHK_SV;
5952 if (ctx->opcode & 0x00008000) {
5953 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5954 /* Stop translation to have a chance to raise an exception */
5955 gen_stop_exception(ctx);
5956 } else {
5957 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5958 }
5959 #endif /* defined(CONFIG_USER_ONLY) */
5960 }
5961
5962 /* PowerPC 440 specific instructions */
5963
5964 /* dlmzb */
5965 static void gen_dlmzb(DisasContext *ctx)
5966 {
5967 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5968 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5969 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5970 tcg_temp_free_i32(t0);
5971 }
5972
5973 /* mbar replaces eieio on 440 */
5974 static void gen_mbar(DisasContext *ctx)
5975 {
5976 /* interpreted as no-op */
5977 }
5978
5979 /* msync replaces sync on 440 */
5980 static void gen_msync_4xx(DisasContext *ctx)
5981 {
5982 /* interpreted as no-op */
5983 }
5984
5985 /* icbt */
5986 static void gen_icbt_440(DisasContext *ctx)
5987 {
5988 /* interpreted as no-op */
5989 /* XXX: specification say this is treated as a load by the MMU
5990 * but does not generate any exception
5991 */
5992 }
5993
5994 /* Embedded.Processor Control */
5995
5996 static void gen_msgclr(DisasContext *ctx)
5997 {
5998 #if defined(CONFIG_USER_ONLY)
5999 GEN_PRIV;
6000 #else
6001 CHK_SV;
6002 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6003 #endif /* defined(CONFIG_USER_ONLY) */
6004 }
6005
6006 static void gen_msgsnd(DisasContext *ctx)
6007 {
6008 #if defined(CONFIG_USER_ONLY)
6009 GEN_PRIV;
6010 #else
6011 CHK_SV;
6012 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6013 #endif /* defined(CONFIG_USER_ONLY) */
6014 }
6015
6016
6017 #if defined(TARGET_PPC64)
6018 static void gen_maddld(DisasContext *ctx)
6019 {
6020 TCGv_i64 t1 = tcg_temp_new_i64();
6021
6022 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6023 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6024 tcg_temp_free_i64(t1);
6025 }
6026
6027 /* maddhd maddhdu */
6028 static void gen_maddhd_maddhdu(DisasContext *ctx)
6029 {
6030 TCGv_i64 lo = tcg_temp_new_i64();
6031 TCGv_i64 hi = tcg_temp_new_i64();
6032 TCGv_i64 t1 = tcg_temp_new_i64();
6033
6034 if (Rc(ctx->opcode)) {
6035 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6036 cpu_gpr[rB(ctx->opcode)]);
6037 tcg_gen_movi_i64(t1, 0);
6038 } else {
6039 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6040 cpu_gpr[rB(ctx->opcode)]);
6041 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6042 }
6043 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6044 cpu_gpr[rC(ctx->opcode)], t1);
6045 tcg_temp_free_i64(lo);
6046 tcg_temp_free_i64(hi);
6047 tcg_temp_free_i64(t1);
6048 }
6049 #endif /* defined(TARGET_PPC64) */
6050
6051 #include "translate/dfp-impl.c"
6052
6053 #include "translate/spe-impl.c"
6054
6055 static void gen_tbegin(DisasContext *ctx)
6056 {
6057 if (unlikely(!ctx->tm_enabled)) {
6058 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6059 return;
6060 }
6061 gen_helper_tbegin(cpu_env);
6062 }
6063
6064 #define GEN_TM_NOOP(name) \
6065 static inline void gen_##name(DisasContext *ctx) \
6066 { \
6067 if (unlikely(!ctx->tm_enabled)) { \
6068 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6069 return; \
6070 } \
6071 /* Because tbegin always fails in QEMU, these user \
6072 * space instructions all have a simple implementation: \
6073 * \
6074 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6075 * = 0b0 || 0b00 || 0b0 \
6076 */ \
6077 tcg_gen_movi_i32(cpu_crf[0], 0); \
6078 }
6079
6080 GEN_TM_NOOP(tend);
6081 GEN_TM_NOOP(tabort);
6082 GEN_TM_NOOP(tabortwc);
6083 GEN_TM_NOOP(tabortwci);
6084 GEN_TM_NOOP(tabortdc);
6085 GEN_TM_NOOP(tabortdci);
6086 GEN_TM_NOOP(tsr);
6087
6088 static void gen_tcheck(DisasContext *ctx)
6089 {
6090 if (unlikely(!ctx->tm_enabled)) {
6091 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6092 return;
6093 }
6094 /* Because tbegin always fails, the tcheck implementation
6095 * is simple:
6096 *
6097 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6098 * = 0b1 || 0b00 || 0b0
6099 */
6100 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6101 }
6102
6103 #if defined(CONFIG_USER_ONLY)
6104 #define GEN_TM_PRIV_NOOP(name) \
6105 static inline void gen_##name(DisasContext *ctx) \
6106 { \
6107 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6108 }
6109
6110 #else
6111
6112 #define GEN_TM_PRIV_NOOP(name) \
6113 static inline void gen_##name(DisasContext *ctx) \
6114 { \
6115 CHK_SV; \
6116 if (unlikely(!ctx->tm_enabled)) { \
6117 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6118 return; \
6119 } \
6120 /* Because tbegin always fails, the implementation is \
6121 * simple: \
6122 * \
6123 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6124 * = 0b0 || 0b00 | 0b0 \
6125 */ \
6126 tcg_gen_movi_i32(cpu_crf[0], 0); \
6127 }
6128
6129 #endif
6130
6131 GEN_TM_PRIV_NOOP(treclaim);
6132 GEN_TM_PRIV_NOOP(trechkpt);
6133
6134 static opcode_t opcodes[] = {
6135 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6136 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6137 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6138 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6139 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6140 #if defined(TARGET_PPC64)
6141 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6142 #endif
6143 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6144 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6145 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6146 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6147 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6148 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6149 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6150 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6151 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6152 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6153 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6154 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6155 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6156 #if defined(TARGET_PPC64)
6157 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6158 #endif
6159 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6160 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6161 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6162 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6163 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6164 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6165 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6166 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6167 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6168 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6169 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6170 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6171 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6172 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6173 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6174 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6175 #if defined(TARGET_PPC64)
6176 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6177 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6178 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6179 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6180 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6181 #endif
6182 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6183 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6184 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6185 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6186 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6187 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6188 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6189 #if defined(TARGET_PPC64)
6190 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6191 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6192 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6193 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6194 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6195 #endif
6196 #if defined(TARGET_PPC64)
6197 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6198 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6199 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6200 #endif
6201 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6202 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6203 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6204 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6205 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6206 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6207 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6208 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6209 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6210 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6211 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6212 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6213 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6214 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6215 #if defined(TARGET_PPC64)
6216 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6217 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6218 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6219 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6220 #endif
6221 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6222 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6223 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6224 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6225 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6226 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6227 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6228 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6229 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6230 #if defined(TARGET_PPC64)
6231 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6232 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6233 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6234 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6235 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6236 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6237 #endif
6238 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6239 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6240 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6241 #if defined(TARGET_PPC64)
6242 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6243 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6244 #endif
6245 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6246 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6247 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6248 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6249 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6250 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6251 #if defined(TARGET_PPC64)
6252 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6253 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6254 #endif
6255 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6256 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6257 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6258 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6259 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6260 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6261 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6262 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6263 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6264 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6265 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6266 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6267 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6268 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6269 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6270 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6271 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6272 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6273 #if defined(TARGET_PPC64)
6274 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6275 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6276 PPC_SEGMENT_64B),
6277 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6278 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6279 PPC_SEGMENT_64B),
6280 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6281 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6282 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6283 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6284 #endif
6285 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6286 /* XXX Those instructions will need to be handled differently for
6287 * different ISA versions */
6288 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6289 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6290 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6291 #if defined(TARGET_PPC64)
6292 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6293 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6294 #endif
6295 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6296 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6297 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6298 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6299 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6300 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6301 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6302 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6303 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6304 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6305 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6306 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6307 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6308 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6309 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6310 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6311 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6312 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6313 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6314 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6315 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6316 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6317 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6318 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6319 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6320 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6321 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6322 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6323 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6324 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6325 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6326 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6327 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6328 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6329 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6330 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6331 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6332 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6333 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6334 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6335 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6336 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6337 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6338 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6339 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6340 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6341 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6342 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6343 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6344 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6345 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6346 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6347 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6348 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6349 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6350 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6351 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6352 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6353 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6354 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6355 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6356 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6357 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6358 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6359 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6360 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6361 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6362 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6363 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6364 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6365 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6366 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6367 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6368 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6369 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6370 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6371 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6372 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6373 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6374 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6375 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6376 PPC_NONE, PPC2_BOOKE206),
6377 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6378 PPC_NONE, PPC2_BOOKE206),
6379 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6380 PPC_NONE, PPC2_BOOKE206),
6381 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6382 PPC_NONE, PPC2_BOOKE206),
6383 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6384 PPC_NONE, PPC2_BOOKE206),
6385 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6386 PPC_NONE, PPC2_PRCNTL),
6387 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6388 PPC_NONE, PPC2_PRCNTL),
6389 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6390 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6391 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6392 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6393 PPC_BOOKE, PPC2_BOOKE206),
6394 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6395 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6396 PPC_BOOKE, PPC2_BOOKE206),
6397 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6398 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6399 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6400 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6401 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6402 #if defined(TARGET_PPC64)
6403 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6404 PPC2_ISA300),
6405 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6406 #endif
6407
6408 #undef GEN_INT_ARITH_ADD
6409 #undef GEN_INT_ARITH_ADD_CONST
6410 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6411 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6412 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6413 add_ca, compute_ca, compute_ov) \
6414 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6415 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6416 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6417 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6418 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6419 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6420 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6421 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6422 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6423 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6424 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6425
6426 #undef GEN_INT_ARITH_DIVW
6427 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6428 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6429 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6430 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6431 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6432 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6433 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6434 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6435 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6436 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6437 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6438 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6439
6440 #if defined(TARGET_PPC64)
6441 #undef GEN_INT_ARITH_DIVD
6442 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6443 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6444 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6445 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6446 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6447 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6448
6449 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6450 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6451 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6452 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6453 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6454 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6455
6456 #undef GEN_INT_ARITH_MUL_HELPER
6457 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6458 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6459 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6460 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6461 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6462 #endif
6463
6464 #undef GEN_INT_ARITH_SUBF
6465 #undef GEN_INT_ARITH_SUBF_CONST
6466 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6467 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6468 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6469 add_ca, compute_ca, compute_ov) \
6470 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6471 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6472 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6473 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6474 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6475 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6476 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6479 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6480 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6481
6482 #undef GEN_LOGICAL1
6483 #undef GEN_LOGICAL2
6484 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6485 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6486 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6487 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6488 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6489 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6490 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6491 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6492 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6493 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6494 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6495 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6496 #if defined(TARGET_PPC64)
6497 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6498 #endif
6499
6500 #if defined(TARGET_PPC64)
6501 #undef GEN_PPC64_R2
6502 #undef GEN_PPC64_R4
6503 #define GEN_PPC64_R2(name, opc1, opc2) \
6504 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6505 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6506 PPC_64B)
6507 #define GEN_PPC64_R4(name, opc1, opc2) \
6508 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6509 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6510 PPC_64B), \
6511 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6512 PPC_64B), \
6513 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6514 PPC_64B)
6515 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6516 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6517 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6518 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6519 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6520 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6521 #endif
6522
6523 #undef GEN_LD
6524 #undef GEN_LDU
6525 #undef GEN_LDUX
6526 #undef GEN_LDX_E
6527 #undef GEN_LDS
6528 #define GEN_LD(name, ldop, opc, type) \
6529 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6530 #define GEN_LDU(name, ldop, opc, type) \
6531 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6532 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6533 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6534 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6535 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6536 #define GEN_LDS(name, ldop, op, type) \
6537 GEN_LD(name, ldop, op | 0x20, type) \
6538 GEN_LDU(name, ldop, op | 0x21, type) \
6539 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6540 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6541
6542 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6543 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6544 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6545 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6546 #if defined(TARGET_PPC64)
6547 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6548 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6549 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6550 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6551 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6552
6553 /* HV/P7 and later only */
6554 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6555 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6556 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6557 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6558 #endif
6559 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6560 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6561
6562 #undef GEN_ST
6563 #undef GEN_STU
6564 #undef GEN_STUX
6565 #undef GEN_STX_E
6566 #undef GEN_STS
6567 #define GEN_ST(name, stop, opc, type) \
6568 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6569 #define GEN_STU(name, stop, opc, type) \
6570 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6571 #define GEN_STUX(name, stop, opc2, opc3, type) \
6572 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6573 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6574 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6575 #define GEN_STS(name, stop, op, type) \
6576 GEN_ST(name, stop, op | 0x20, type) \
6577 GEN_STU(name, stop, op | 0x21, type) \
6578 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6579 GEN_STX(name, stop, 0x17, op | 0x00, type)
6580
6581 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6582 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6583 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6584 #if defined(TARGET_PPC64)
6585 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6586 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6587 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6588 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6589 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6590 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6591 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6592 #endif
6593 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6594 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6595
6596 #undef GEN_CRLOGIC
6597 #define GEN_CRLOGIC(name, tcg_op, opc) \
6598 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6599 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6600 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6601 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6602 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6603 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6604 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6605 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6606 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6607
6608 #undef GEN_MAC_HANDLER
6609 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6610 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6611 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6612 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6613 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6614 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6615 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6616 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6617 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6618 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6619 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6620 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6621 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6622 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6623 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6624 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6625 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6626 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6627 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6628 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6629 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6630 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6631 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6632 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6633 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6634 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6635 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6636 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6637 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6638 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6639 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6640 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6641 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6642 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6643 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6644 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6645 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6646 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6647 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6648 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6649 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6650 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6651 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6652 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6653
6654 #include "translate/fp-ops.c"
6655
6656 #include "translate/vmx-ops.c"
6657
6658 #include "translate/vsx-ops.c"
6659
6660 #include "translate/dfp-ops.c"
6661
6662 #include "translate/spe-ops.c"
6663
6664 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6665 PPC_NONE, PPC2_TM),
6666 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6667 PPC_NONE, PPC2_TM),
6668 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6669 PPC_NONE, PPC2_TM),
6670 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6671 PPC_NONE, PPC2_TM),
6672 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6673 PPC_NONE, PPC2_TM),
6674 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6675 PPC_NONE, PPC2_TM),
6676 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6677 PPC_NONE, PPC2_TM),
6678 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6679 PPC_NONE, PPC2_TM),
6680 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6681 PPC_NONE, PPC2_TM),
6682 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6683 PPC_NONE, PPC2_TM),
6684 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6685 PPC_NONE, PPC2_TM),
6686 };
6687
6688 #include "helper_regs.h"
6689 #include "translate_init.c"
6690
6691 /*****************************************************************************/
6692 /* Misc PowerPC helpers */
6693 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6694 int flags)
6695 {
6696 #define RGPL 4
6697 #define RFPL 4
6698
6699 PowerPCCPU *cpu = POWERPC_CPU(cs);
6700 CPUPPCState *env = &cpu->env;
6701 int i;
6702
6703 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6704 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6705 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6706 cs->cpu_index);
6707 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6708 TARGET_FMT_lx " iidx %d didx %d\n",
6709 env->msr, env->spr[SPR_HID0],
6710 env->hflags, env->immu_idx, env->dmmu_idx);
6711 #if !defined(NO_TIMER_DUMP)
6712 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6713 #if !defined(CONFIG_USER_ONLY)
6714 " DECR %08" PRIu32
6715 #endif
6716 "\n",
6717 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6718 #if !defined(CONFIG_USER_ONLY)
6719 , cpu_ppc_load_decr(env)
6720 #endif
6721 );
6722 #endif
6723 for (i = 0; i < 32; i++) {
6724 if ((i & (RGPL - 1)) == 0)
6725 cpu_fprintf(f, "GPR%02d", i);
6726 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6727 if ((i & (RGPL - 1)) == (RGPL - 1))
6728 cpu_fprintf(f, "\n");
6729 }
6730 cpu_fprintf(f, "CR ");
6731 for (i = 0; i < 8; i++)
6732 cpu_fprintf(f, "%01x", env->crf[i]);
6733 cpu_fprintf(f, " [");
6734 for (i = 0; i < 8; i++) {
6735 char a = '-';
6736 if (env->crf[i] & 0x08)
6737 a = 'L';
6738 else if (env->crf[i] & 0x04)
6739 a = 'G';
6740 else if (env->crf[i] & 0x02)
6741 a = 'E';
6742 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6743 }
6744 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6745 env->reserve_addr);
6746 for (i = 0; i < 32; i++) {
6747 if ((i & (RFPL - 1)) == 0)
6748 cpu_fprintf(f, "FPR%02d", i);
6749 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6750 if ((i & (RFPL - 1)) == (RFPL - 1))
6751 cpu_fprintf(f, "\n");
6752 }
6753 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6754 #if !defined(CONFIG_USER_ONLY)
6755 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6756 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6757 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6758 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6759
6760 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6761 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6762 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6763 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6764
6765 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6766 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6767 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6768 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6769
6770 #if defined(TARGET_PPC64)
6771 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6772 env->excp_model == POWERPC_EXCP_POWER8) {
6773 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6774 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6775 }
6776 #endif
6777 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6778 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6779 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6780 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6781 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6782
6783 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6784 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6785 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6786 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6787
6788 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6789 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6790 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6791 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6792
6793 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6794 " EPR " TARGET_FMT_lx "\n",
6795 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6796 env->spr[SPR_BOOKE_EPR]);
6797
6798 /* FSL-specific */
6799 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6800 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6801 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6802 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6803
6804 /*
6805 * IVORs are left out as they are large and do not change often --
6806 * they can be read with "p $ivor0", "p $ivor1", etc.
6807 */
6808 }
6809
6810 #if defined(TARGET_PPC64)
6811 if (env->flags & POWERPC_FLAG_CFAR) {
6812 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6813 }
6814 #endif
6815
6816 switch (env->mmu_model) {
6817 case POWERPC_MMU_32B:
6818 case POWERPC_MMU_601:
6819 case POWERPC_MMU_SOFT_6xx:
6820 case POWERPC_MMU_SOFT_74xx:
6821 #if defined(TARGET_PPC64)
6822 case POWERPC_MMU_64B:
6823 case POWERPC_MMU_2_03:
6824 case POWERPC_MMU_2_06:
6825 case POWERPC_MMU_2_06a:
6826 case POWERPC_MMU_2_07:
6827 case POWERPC_MMU_2_07a:
6828 #endif
6829 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6830 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6831 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6832 break;
6833 case POWERPC_MMU_BOOKE206:
6834 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6835 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6836 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6837 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6838
6839 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6840 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6841 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6842 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6843
6844 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6845 " TLB1CFG " TARGET_FMT_lx "\n",
6846 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6847 env->spr[SPR_BOOKE_TLB1CFG]);
6848 break;
6849 default:
6850 break;
6851 }
6852 #endif
6853
6854 #undef RGPL
6855 #undef RFPL
6856 }
6857
6858 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6859 fprintf_function cpu_fprintf, int flags)
6860 {
6861 #if defined(DO_PPC_STATISTICS)
6862 PowerPCCPU *cpu = POWERPC_CPU(cs);
6863 opc_handler_t **t1, **t2, **t3, *handler;
6864 int op1, op2, op3;
6865
6866 t1 = cpu->env.opcodes;
6867 for (op1 = 0; op1 < 64; op1++) {
6868 handler = t1[op1];
6869 if (is_indirect_opcode(handler)) {
6870 t2 = ind_table(handler);
6871 for (op2 = 0; op2 < 32; op2++) {
6872 handler = t2[op2];
6873 if (is_indirect_opcode(handler)) {
6874 t3 = ind_table(handler);
6875 for (op3 = 0; op3 < 32; op3++) {
6876 handler = t3[op3];
6877 if (handler->count == 0)
6878 continue;
6879 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6880 "%016" PRIx64 " %" PRId64 "\n",
6881 op1, op2, op3, op1, (op3 << 5) | op2,
6882 handler->oname,
6883 handler->count, handler->count);
6884 }
6885 } else {
6886 if (handler->count == 0)
6887 continue;
6888 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6889 "%016" PRIx64 " %" PRId64 "\n",
6890 op1, op2, op1, op2, handler->oname,
6891 handler->count, handler->count);
6892 }
6893 }
6894 } else {
6895 if (handler->count == 0)
6896 continue;
6897 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6898 " %" PRId64 "\n",
6899 op1, op1, handler->oname,
6900 handler->count, handler->count);
6901 }
6902 }
6903 #endif
6904 }
6905
6906 /*****************************************************************************/
6907 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6908 {
6909 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6910 CPUState *cs = CPU(cpu);
6911 DisasContext ctx, *ctxp = &ctx;
6912 opc_handler_t **table, *handler;
6913 target_ulong pc_start;
6914 int num_insns;
6915 int max_insns;
6916
6917 pc_start = tb->pc;
6918 ctx.nip = pc_start;
6919 ctx.tb = tb;
6920 ctx.exception = POWERPC_EXCP_NONE;
6921 ctx.spr_cb = env->spr_cb;
6922 ctx.pr = msr_pr;
6923 ctx.mem_idx = env->dmmu_idx;
6924 ctx.dr = msr_dr;
6925 #if !defined(CONFIG_USER_ONLY)
6926 ctx.hv = msr_hv || !env->has_hv_mode;
6927 #endif
6928 ctx.insns_flags = env->insns_flags;
6929 ctx.insns_flags2 = env->insns_flags2;
6930 ctx.access_type = -1;
6931 ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
6932 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6933 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6934 #if defined(TARGET_PPC64)
6935 ctx.sf_mode = msr_is_64bit(env, env->msr);
6936 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6937 #endif
6938 if (env->mmu_model == POWERPC_MMU_32B ||
6939 env->mmu_model == POWERPC_MMU_601 ||
6940 (env->mmu_model & POWERPC_MMU_64B))
6941 ctx.lazy_tlb_flush = true;
6942
6943 ctx.fpu_enabled = !!msr_fp;
6944 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6945 ctx.spe_enabled = !!msr_spe;
6946 else
6947 ctx.spe_enabled = false;
6948 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6949 ctx.altivec_enabled = !!msr_vr;
6950 else
6951 ctx.altivec_enabled = false;
6952 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6953 ctx.vsx_enabled = !!msr_vsx;
6954 } else {
6955 ctx.vsx_enabled = false;
6956 }
6957 #if defined(TARGET_PPC64)
6958 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6959 ctx.tm_enabled = !!msr_tm;
6960 } else {
6961 ctx.tm_enabled = false;
6962 }
6963 #endif
6964 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6965 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6966 else
6967 ctx.singlestep_enabled = 0;
6968 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6969 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6970 if (unlikely(cs->singlestep_enabled)) {
6971 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6972 }
6973 #if defined (DO_SINGLE_STEP) && 0
6974 /* Single step trace mode */
6975 msr_se = 1;
6976 #endif
6977 num_insns = 0;
6978 max_insns = tb->cflags & CF_COUNT_MASK;
6979 if (max_insns == 0) {
6980 max_insns = CF_COUNT_MASK;
6981 }
6982 if (max_insns > TCG_MAX_INSNS) {
6983 max_insns = TCG_MAX_INSNS;
6984 }
6985
6986 gen_tb_start(tb);
6987 tcg_clear_temp_count();
6988 /* Set env in case of segfault during code fetch */
6989 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
6990 tcg_gen_insn_start(ctx.nip);
6991 num_insns++;
6992
6993 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
6994 gen_debug_exception(ctxp);
6995 /* The address covered by the breakpoint must be included in
6996 [tb->pc, tb->pc + tb->size) in order to for it to be
6997 properly cleared -- thus we increment the PC here so that
6998 the logic setting tb->size below does the right thing. */
6999 ctx.nip += 4;
7000 break;
7001 }
7002
7003 LOG_DISAS("----------------\n");
7004 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7005 ctx.nip, ctx.mem_idx, (int)msr_ir);
7006 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
7007 gen_io_start();
7008 if (unlikely(need_byteswap(&ctx))) {
7009 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
7010 } else {
7011 ctx.opcode = cpu_ldl_code(env, ctx.nip);
7012 }
7013 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7014 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
7015 opc3(ctx.opcode), opc4(ctx.opcode),
7016 ctx.le_mode ? "little" : "big");
7017 ctx.nip += 4;
7018 table = env->opcodes;
7019 handler = table[opc1(ctx.opcode)];
7020 if (is_indirect_opcode(handler)) {
7021 table = ind_table(handler);
7022 handler = table[opc2(ctx.opcode)];
7023 if (is_indirect_opcode(handler)) {
7024 table = ind_table(handler);
7025 handler = table[opc3(ctx.opcode)];
7026 if (is_indirect_opcode(handler)) {
7027 table = ind_table(handler);
7028 handler = table[opc4(ctx.opcode)];
7029 }
7030 }
7031 }
7032 /* Is opcode *REALLY* valid ? */
7033 if (unlikely(handler->handler == &gen_invalid)) {
7034 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7035 "%02x - %02x - %02x - %02x (%08x) "
7036 TARGET_FMT_lx " %d\n",
7037 opc1(ctx.opcode), opc2(ctx.opcode),
7038 opc3(ctx.opcode), opc4(ctx.opcode),
7039 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7040 } else {
7041 uint32_t inval;
7042
7043 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7044 inval = handler->inval2;
7045 } else {
7046 inval = handler->inval1;
7047 }
7048
7049 if (unlikely((ctx.opcode & inval) != 0)) {
7050 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7051 "%02x - %02x - %02x - %02x (%08x) "
7052 TARGET_FMT_lx "\n", ctx.opcode & inval,
7053 opc1(ctx.opcode), opc2(ctx.opcode),
7054 opc3(ctx.opcode), opc4(ctx.opcode),
7055 ctx.opcode, ctx.nip - 4);
7056 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7057 break;
7058 }
7059 }
7060 (*(handler->handler))(&ctx);
7061 #if defined(DO_PPC_STATISTICS)
7062 handler->count++;
7063 #endif
7064 /* Check trace mode exceptions */
7065 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7066 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7067 ctx.exception != POWERPC_SYSCALL &&
7068 ctx.exception != POWERPC_EXCP_TRAP &&
7069 ctx.exception != POWERPC_EXCP_BRANCH)) {
7070 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7071 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7072 (cs->singlestep_enabled) ||
7073 singlestep ||
7074 num_insns >= max_insns)) {
7075 /* if we reach a page boundary or are single stepping, stop
7076 * generation
7077 */
7078 break;
7079 }
7080 if (tcg_check_temp_count()) {
7081 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7082 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7083 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7084 exit(1);
7085 }
7086 }
7087 if (tb->cflags & CF_LAST_IO)
7088 gen_io_end();
7089 if (ctx.exception == POWERPC_EXCP_NONE) {
7090 gen_goto_tb(&ctx, 0, ctx.nip);
7091 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7092 if (unlikely(cs->singlestep_enabled)) {
7093 gen_debug_exception(ctxp);
7094 }
7095 /* Generate the return instruction */
7096 tcg_gen_exit_tb(0);
7097 }
7098 gen_tb_end(tb, num_insns);
7099
7100 tb->size = ctx.nip - pc_start;
7101 tb->icount = num_insns;
7102
7103 #if defined(DEBUG_DISAS)
7104 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7105 && qemu_log_in_addr_range(pc_start)) {
7106 int flags;
7107 flags = env->bfd_mach;
7108 flags |= ctx.le_mode << 16;
7109 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7110 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7111 qemu_log("\n");
7112 }
7113 #endif
7114 }
7115
7116 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7117 target_ulong *data)
7118 {
7119 env->nip = data[0];
7120 }
QEmu