2 * TriCore emulation for qemu: main translation routines.
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "tricore-opcodes.h"
42 static TCGv cpu_gpr_a
[16];
43 static TCGv cpu_gpr_d
[16];
45 static TCGv cpu_PSW_C
;
46 static TCGv cpu_PSW_V
;
47 static TCGv cpu_PSW_SV
;
48 static TCGv cpu_PSW_AV
;
49 static TCGv cpu_PSW_SAV
;
51 #include "exec/gen-icount.h"
53 static const char *regnames_a
[] = {
54 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
55 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
56 "a12" , "a13" , "a14" , "a15",
59 static const char *regnames_d
[] = {
60 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
61 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
62 "d12" , "d13" , "d14" , "d15",
65 typedef struct DisasContext
{
66 struct TranslationBlock
*tb
;
67 target_ulong pc
, saved_pc
, next_pc
;
69 int singlestep_enabled
;
70 /* Routine used to access memory */
72 uint32_t hflags
, saved_hflags
;
91 void tricore_cpu_dump_state(CPUState
*cs
, FILE *f
,
92 fprintf_function cpu_fprintf
, int flags
)
94 TriCoreCPU
*cpu
= TRICORE_CPU(cs
);
95 CPUTriCoreState
*env
= &cpu
->env
;
101 cpu_fprintf(f
, "PC: " TARGET_FMT_lx
, env
->PC
);
102 cpu_fprintf(f
, " PSW: " TARGET_FMT_lx
, psw
);
103 cpu_fprintf(f
, " ICR: " TARGET_FMT_lx
, env
->ICR
);
104 cpu_fprintf(f
, "\nPCXI: " TARGET_FMT_lx
, env
->PCXI
);
105 cpu_fprintf(f
, " FCX: " TARGET_FMT_lx
, env
->FCX
);
106 cpu_fprintf(f
, " LCX: " TARGET_FMT_lx
, env
->LCX
);
108 for (i
= 0; i
< 16; ++i
) {
110 cpu_fprintf(f
, "\nGPR A%02d:", i
);
112 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_a
[i
]);
114 for (i
= 0; i
< 16; ++i
) {
116 cpu_fprintf(f
, "\nGPR D%02d:", i
);
118 cpu_fprintf(f
, " " TARGET_FMT_lx
, env
->gpr_d
[i
]);
120 cpu_fprintf(f
, "\n");
124 * Functions to generate micro-ops
127 /* Makros for generating helpers */
129 #define gen_helper_1arg(name, arg) do { \
130 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
131 gen_helper_##name(cpu_env, helper_tmp); \
132 tcg_temp_free_i32(helper_tmp); \
135 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
136 TCGv arg00 = tcg_temp_new(); \
137 TCGv arg01 = tcg_temp_new(); \
138 TCGv arg11 = tcg_temp_new(); \
139 tcg_gen_sari_tl(arg00, arg0, 16); \
140 tcg_gen_ext16s_tl(arg01, arg0); \
141 tcg_gen_ext16s_tl(arg11, arg1); \
142 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
143 tcg_temp_free(arg00); \
144 tcg_temp_free(arg01); \
145 tcg_temp_free(arg11); \
148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
149 TCGv arg00 = tcg_temp_new(); \
150 TCGv arg01 = tcg_temp_new(); \
151 TCGv arg10 = tcg_temp_new(); \
152 TCGv arg11 = tcg_temp_new(); \
153 tcg_gen_sari_tl(arg00, arg0, 16); \
154 tcg_gen_ext16s_tl(arg01, arg0); \
155 tcg_gen_sari_tl(arg11, arg1, 16); \
156 tcg_gen_ext16s_tl(arg10, arg1); \
157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
158 tcg_temp_free(arg00); \
159 tcg_temp_free(arg01); \
160 tcg_temp_free(arg10); \
161 tcg_temp_free(arg11); \
164 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
165 TCGv arg00 = tcg_temp_new(); \
166 TCGv arg01 = tcg_temp_new(); \
167 TCGv arg10 = tcg_temp_new(); \
168 TCGv arg11 = tcg_temp_new(); \
169 tcg_gen_sari_tl(arg00, arg0, 16); \
170 tcg_gen_ext16s_tl(arg01, arg0); \
171 tcg_gen_sari_tl(arg10, arg1, 16); \
172 tcg_gen_ext16s_tl(arg11, arg1); \
173 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
174 tcg_temp_free(arg00); \
175 tcg_temp_free(arg01); \
176 tcg_temp_free(arg10); \
177 tcg_temp_free(arg11); \
180 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
181 TCGv arg00 = tcg_temp_new(); \
182 TCGv arg01 = tcg_temp_new(); \
183 TCGv arg11 = tcg_temp_new(); \
184 tcg_gen_sari_tl(arg01, arg0, 16); \
185 tcg_gen_ext16s_tl(arg00, arg0); \
186 tcg_gen_sari_tl(arg11, arg1, 16); \
187 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
188 tcg_temp_free(arg00); \
189 tcg_temp_free(arg01); \
190 tcg_temp_free(arg11); \
193 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
194 TCGv_i64 ret = tcg_temp_new_i64(); \
195 TCGv_i64 arg1 = tcg_temp_new_i64(); \
197 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
198 gen_helper_##name(ret, arg1, arg2); \
199 tcg_gen_extr_i64_i32(rl, rh, ret); \
201 tcg_temp_free_i64(ret); \
202 tcg_temp_free_i64(arg1); \
205 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \
206 TCGv_i64 ret = tcg_temp_new_i64(); \
208 gen_helper_##name(ret, cpu_env, arg1, arg2); \
209 tcg_gen_extr_i64_i32(rl, rh, ret); \
211 tcg_temp_free_i64(ret); \
214 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
215 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
216 ((offset & 0x0fffff) << 1))
218 /* For two 32-bit registers used a 64-bit register, the first
219 registernumber needs to be even. Otherwise we trap. */
220 static inline void generate_trap(DisasContext
*ctx
, int class, int tin
);
221 #define CHECK_REG_PAIR(reg) do { \
223 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
227 /* Functions for load/save to/from memory */
229 static inline void gen_offset_ld(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
230 int16_t con
, TCGMemOp mop
)
232 TCGv temp
= tcg_temp_new();
233 tcg_gen_addi_tl(temp
, r2
, con
);
234 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
238 static inline void gen_offset_st(DisasContext
*ctx
, TCGv r1
, TCGv r2
,
239 int16_t con
, TCGMemOp mop
)
241 TCGv temp
= tcg_temp_new();
242 tcg_gen_addi_tl(temp
, r2
, con
);
243 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
247 static void gen_st_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
249 TCGv_i64 temp
= tcg_temp_new_i64();
251 tcg_gen_concat_i32_i64(temp
, rl
, rh
);
252 tcg_gen_qemu_st_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
254 tcg_temp_free_i64(temp
);
257 static void gen_offset_st_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
260 TCGv temp
= tcg_temp_new();
261 tcg_gen_addi_tl(temp
, base
, con
);
262 gen_st_2regs_64(rh
, rl
, temp
, ctx
);
266 static void gen_ld_2regs_64(TCGv rh
, TCGv rl
, TCGv address
, DisasContext
*ctx
)
268 TCGv_i64 temp
= tcg_temp_new_i64();
270 tcg_gen_qemu_ld_i64(temp
, address
, ctx
->mem_idx
, MO_LEQ
);
271 /* write back to two 32 bit regs */
272 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
274 tcg_temp_free_i64(temp
);
277 static void gen_offset_ld_2regs(TCGv rh
, TCGv rl
, TCGv base
, int16_t con
,
280 TCGv temp
= tcg_temp_new();
281 tcg_gen_addi_tl(temp
, base
, con
);
282 gen_ld_2regs_64(rh
, rl
, temp
, ctx
);
286 static void gen_st_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
289 TCGv temp
= tcg_temp_new();
290 tcg_gen_addi_tl(temp
, r2
, off
);
291 tcg_gen_qemu_st_tl(r1
, temp
, ctx
->mem_idx
, mop
);
292 tcg_gen_mov_tl(r2
, temp
);
296 static void gen_ld_preincr(DisasContext
*ctx
, TCGv r1
, TCGv r2
, int16_t off
,
299 TCGv temp
= tcg_temp_new();
300 tcg_gen_addi_tl(temp
, r2
, off
);
301 tcg_gen_qemu_ld_tl(r1
, temp
, ctx
->mem_idx
, mop
);
302 tcg_gen_mov_tl(r2
, temp
);
306 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
307 static void gen_ldmst(DisasContext
*ctx
, int ereg
, TCGv ea
)
309 TCGv temp
= tcg_temp_new();
310 TCGv temp2
= tcg_temp_new();
312 CHECK_REG_PAIR(ereg
);
313 /* temp = (M(EA, word) */
314 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
315 /* temp = temp & ~E[a][63:32]) */
316 tcg_gen_andc_tl(temp
, temp
, cpu_gpr_d
[ereg
+1]);
317 /* temp2 = (E[a][31:0] & E[a][63:32]); */
318 tcg_gen_and_tl(temp2
, cpu_gpr_d
[ereg
], cpu_gpr_d
[ereg
+1]);
319 /* temp = temp | temp2; */
320 tcg_gen_or_tl(temp
, temp
, temp2
);
321 /* M(EA, word) = temp; */
322 tcg_gen_qemu_st_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
325 tcg_temp_free(temp2
);
328 /* tmp = M(EA, word);
331 static void gen_swap(DisasContext
*ctx
, int reg
, TCGv ea
)
333 TCGv temp
= tcg_temp_new();
335 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
336 tcg_gen_qemu_st_tl(cpu_gpr_d
[reg
], ea
, ctx
->mem_idx
, MO_LEUL
);
337 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
342 static void gen_cmpswap(DisasContext
*ctx
, int reg
, TCGv ea
)
344 TCGv temp
= tcg_temp_new();
345 TCGv temp2
= tcg_temp_new();
346 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
347 tcg_gen_movcond_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[reg
+1], temp
,
348 cpu_gpr_d
[reg
], temp
);
349 tcg_gen_qemu_st_tl(temp2
, ea
, ctx
->mem_idx
, MO_LEUL
);
350 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
353 tcg_temp_free(temp2
);
356 static void gen_swapmsk(DisasContext
*ctx
, int reg
, TCGv ea
)
358 TCGv temp
= tcg_temp_new();
359 TCGv temp2
= tcg_temp_new();
360 TCGv temp3
= tcg_temp_new();
362 tcg_gen_qemu_ld_tl(temp
, ea
, ctx
->mem_idx
, MO_LEUL
);
363 tcg_gen_and_tl(temp2
, cpu_gpr_d
[reg
], cpu_gpr_d
[reg
+1]);
364 tcg_gen_andc_tl(temp3
, temp
, cpu_gpr_d
[reg
+1]);
365 tcg_gen_or_tl(temp2
, temp2
, temp3
);
366 tcg_gen_qemu_st_tl(temp2
, ea
, ctx
->mem_idx
, MO_LEUL
);
367 tcg_gen_mov_tl(cpu_gpr_d
[reg
], temp
);
370 tcg_temp_free(temp2
);
371 tcg_temp_free(temp3
);
375 /* We generate loads and store to core special function register (csfr) through
376 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
377 makros R, A and E, which allow read-only, all and endinit protected access.
378 These makros also specify in which ISA version the csfr was introduced. */
379 #define R(ADDRESS, REG, FEATURE) \
381 if (tricore_feature(env, FEATURE)) { \
382 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
385 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
386 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
387 static inline void gen_mfcr(CPUTriCoreState
*env
, TCGv ret
, int32_t offset
)
389 /* since we're caching PSW make this a special case */
390 if (offset
== 0xfe04) {
391 gen_helper_psw_read(ret
, cpu_env
);
402 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
403 since no execption occurs */
404 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
406 if (tricore_feature(env, FEATURE)) { \
407 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
410 /* Endinit protected registers
411 TODO: Since the endinit bit is in a register of a not yet implemented
412 watchdog device, we handle endinit protected registers like
413 all-access registers for now. */
414 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
415 static inline void gen_mtcr(CPUTriCoreState
*env
, DisasContext
*ctx
, TCGv r1
,
418 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
) {
419 /* since we're caching PSW make this a special case */
420 if (offset
== 0xfe04) {
421 gen_helper_psw_write(cpu_env
, r1
);
428 /* generate privilege trap */
432 /* Functions for arithmetic instructions */
434 static inline void gen_add_d(TCGv ret
, TCGv r1
, TCGv r2
)
436 TCGv t0
= tcg_temp_new_i32();
437 TCGv result
= tcg_temp_new_i32();
438 /* Addition and set V/SV bits */
439 tcg_gen_add_tl(result
, r1
, r2
);
441 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
442 tcg_gen_xor_tl(t0
, r1
, r2
);
443 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
445 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
446 /* Calc AV/SAV bits */
447 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
448 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
450 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
451 /* write back result */
452 tcg_gen_mov_tl(ret
, result
);
454 tcg_temp_free(result
);
459 gen_add64_d(TCGv_i64 ret
, TCGv_i64 r1
, TCGv_i64 r2
)
461 TCGv temp
= tcg_temp_new();
462 TCGv_i64 t0
= tcg_temp_new_i64();
463 TCGv_i64 t1
= tcg_temp_new_i64();
464 TCGv_i64 result
= tcg_temp_new_i64();
466 tcg_gen_add_i64(result
, r1
, r2
);
468 tcg_gen_xor_i64(t1
, result
, r1
);
469 tcg_gen_xor_i64(t0
, r1
, r2
);
470 tcg_gen_andc_i64(t1
, t1
, t0
);
471 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t1
);
473 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
474 /* calc AV/SAV bits */
475 tcg_gen_extrh_i64_i32(temp
, result
);
476 tcg_gen_add_tl(cpu_PSW_AV
, temp
, temp
);
477 tcg_gen_xor_tl(cpu_PSW_AV
, temp
, cpu_PSW_AV
);
479 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
480 /* write back result */
481 tcg_gen_mov_i64(ret
, result
);
484 tcg_temp_free_i64(result
);
485 tcg_temp_free_i64(t0
);
486 tcg_temp_free_i64(t1
);
490 gen_addsub64_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
491 TCGv r3
, void(*op1
)(TCGv
, TCGv
, TCGv
),
492 void(*op2
)(TCGv
, TCGv
, TCGv
))
494 TCGv temp
= tcg_temp_new();
495 TCGv temp2
= tcg_temp_new();
496 TCGv temp3
= tcg_temp_new();
497 TCGv temp4
= tcg_temp_new();
499 (*op1
)(temp
, r1_low
, r2
);
501 tcg_gen_xor_tl(temp2
, temp
, r1_low
);
502 tcg_gen_xor_tl(temp3
, r1_low
, r2
);
503 if (op1
== tcg_gen_add_tl
) {
504 tcg_gen_andc_tl(temp2
, temp2
, temp3
);
506 tcg_gen_and_tl(temp2
, temp2
, temp3
);
509 (*op2
)(temp3
, r1_high
, r3
);
511 tcg_gen_xor_tl(cpu_PSW_V
, temp3
, r1_high
);
512 tcg_gen_xor_tl(temp4
, r1_high
, r3
);
513 if (op2
== tcg_gen_add_tl
) {
514 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
516 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp4
);
518 /* combine V0/V1 bits */
519 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp2
);
521 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
523 tcg_gen_mov_tl(ret_low
, temp
);
524 tcg_gen_mov_tl(ret_high
, temp3
);
526 tcg_gen_add_tl(temp
, ret_low
, ret_low
);
527 tcg_gen_xor_tl(temp
, temp
, ret_low
);
528 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
529 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, ret_high
);
530 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
532 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
535 tcg_temp_free(temp2
);
536 tcg_temp_free(temp3
);
537 tcg_temp_free(temp4
);
540 /* ret = r2 + (r1 * r3); */
541 static inline void gen_madd32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
543 TCGv_i64 t1
= tcg_temp_new_i64();
544 TCGv_i64 t2
= tcg_temp_new_i64();
545 TCGv_i64 t3
= tcg_temp_new_i64();
547 tcg_gen_ext_i32_i64(t1
, r1
);
548 tcg_gen_ext_i32_i64(t2
, r2
);
549 tcg_gen_ext_i32_i64(t3
, r3
);
551 tcg_gen_mul_i64(t1
, t1
, t3
);
552 tcg_gen_add_i64(t1
, t2
, t1
);
554 tcg_gen_extrl_i64_i32(ret
, t1
);
557 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
558 /* t1 < -0x80000000 */
559 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
560 tcg_gen_or_i64(t2
, t2
, t3
);
561 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
562 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
564 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
565 /* Calc AV/SAV bits */
566 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
567 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
569 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
571 tcg_temp_free_i64(t1
);
572 tcg_temp_free_i64(t2
);
573 tcg_temp_free_i64(t3
);
576 static inline void gen_maddi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
578 TCGv temp
= tcg_const_i32(con
);
579 gen_madd32_d(ret
, r1
, r2
, temp
);
584 gen_madd64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
587 TCGv t1
= tcg_temp_new();
588 TCGv t2
= tcg_temp_new();
589 TCGv t3
= tcg_temp_new();
590 TCGv t4
= tcg_temp_new();
592 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
593 /* only the add can overflow */
594 tcg_gen_add2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
596 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
597 tcg_gen_xor_tl(t1
, r2_high
, t2
);
598 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
600 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
601 /* Calc AV/SAV bits */
602 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
603 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
605 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
606 /* write back the result */
607 tcg_gen_mov_tl(ret_low
, t3
);
608 tcg_gen_mov_tl(ret_high
, t4
);
617 gen_maddu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
620 TCGv_i64 t1
= tcg_temp_new_i64();
621 TCGv_i64 t2
= tcg_temp_new_i64();
622 TCGv_i64 t3
= tcg_temp_new_i64();
624 tcg_gen_extu_i32_i64(t1
, r1
);
625 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
626 tcg_gen_extu_i32_i64(t3
, r3
);
628 tcg_gen_mul_i64(t1
, t1
, t3
);
629 tcg_gen_add_i64(t2
, t2
, t1
);
630 /* write back result */
631 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t2
);
632 /* only the add overflows, if t2 < t1
634 tcg_gen_setcond_i64(TCG_COND_LTU
, t2
, t2
, t1
);
635 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
636 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
638 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
639 /* Calc AV/SAV bits */
640 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
641 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
643 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
645 tcg_temp_free_i64(t1
);
646 tcg_temp_free_i64(t2
);
647 tcg_temp_free_i64(t3
);
651 gen_maddi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
654 TCGv temp
= tcg_const_i32(con
);
655 gen_madd64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
660 gen_maddui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
663 TCGv temp
= tcg_const_i32(con
);
664 gen_maddu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
669 gen_madd_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
670 TCGv r3
, uint32_t n
, uint32_t mode
)
672 TCGv temp
= tcg_const_i32(n
);
673 TCGv temp2
= tcg_temp_new();
674 TCGv_i64 temp64
= tcg_temp_new_i64();
677 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
680 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
683 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
686 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
689 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
690 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
691 tcg_gen_add_tl
, tcg_gen_add_tl
);
693 tcg_temp_free(temp2
);
694 tcg_temp_free_i64(temp64
);
698 gen_maddsu_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
699 TCGv r3
, uint32_t n
, uint32_t mode
)
701 TCGv temp
= tcg_const_i32(n
);
702 TCGv temp2
= tcg_temp_new();
703 TCGv_i64 temp64
= tcg_temp_new_i64();
706 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
709 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
712 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
715 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
718 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
719 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
720 tcg_gen_sub_tl
, tcg_gen_add_tl
);
722 tcg_temp_free(temp2
);
723 tcg_temp_free_i64(temp64
);
727 gen_maddsum_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
728 TCGv r3
, uint32_t n
, uint32_t mode
)
730 TCGv temp
= tcg_const_i32(n
);
731 TCGv_i64 temp64
= tcg_temp_new_i64();
732 TCGv_i64 temp64_2
= tcg_temp_new_i64();
733 TCGv_i64 temp64_3
= tcg_temp_new_i64();
736 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
739 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
742 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
745 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
748 tcg_gen_concat_i32_i64(temp64_3
, r1_low
, r1_high
);
749 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
750 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
751 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
752 tcg_gen_shli_i64(temp64
, temp64
, 16);
754 gen_add64_d(temp64_2
, temp64_3
, temp64
);
755 /* write back result */
756 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_2
);
759 tcg_temp_free_i64(temp64
);
760 tcg_temp_free_i64(temp64_2
);
761 tcg_temp_free_i64(temp64_3
);
764 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
);
767 gen_madds_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
768 TCGv r3
, uint32_t n
, uint32_t mode
)
770 TCGv temp
= tcg_const_i32(n
);
771 TCGv temp2
= tcg_temp_new();
772 TCGv temp3
= tcg_temp_new();
773 TCGv_i64 temp64
= tcg_temp_new_i64();
777 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
780 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
783 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
786 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
789 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
790 gen_adds(ret_low
, r1_low
, temp
);
791 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
792 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
793 gen_adds(ret_high
, r1_high
, temp2
);
795 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
796 /* combine av bits */
797 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
800 tcg_temp_free(temp2
);
801 tcg_temp_free(temp3
);
802 tcg_temp_free_i64(temp64
);
806 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
);
809 gen_maddsus_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
810 TCGv r3
, uint32_t n
, uint32_t mode
)
812 TCGv temp
= tcg_const_i32(n
);
813 TCGv temp2
= tcg_temp_new();
814 TCGv temp3
= tcg_temp_new();
815 TCGv_i64 temp64
= tcg_temp_new_i64();
819 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
822 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
825 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
828 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
831 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
832 gen_subs(ret_low
, r1_low
, temp
);
833 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
834 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
835 gen_adds(ret_high
, r1_high
, temp2
);
837 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
838 /* combine av bits */
839 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
842 tcg_temp_free(temp2
);
843 tcg_temp_free(temp3
);
844 tcg_temp_free_i64(temp64
);
849 gen_maddsums_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
850 TCGv r3
, uint32_t n
, uint32_t mode
)
852 TCGv temp
= tcg_const_i32(n
);
853 TCGv_i64 temp64
= tcg_temp_new_i64();
854 TCGv_i64 temp64_2
= tcg_temp_new_i64();
858 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
861 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
864 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
867 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
870 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
871 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
872 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
873 tcg_gen_shli_i64(temp64
, temp64
, 16);
874 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
876 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
877 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
880 tcg_temp_free_i64(temp64
);
881 tcg_temp_free_i64(temp64_2
);
886 gen_maddm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
887 TCGv r3
, uint32_t n
, uint32_t mode
)
889 TCGv temp
= tcg_const_i32(n
);
890 TCGv_i64 temp64
= tcg_temp_new_i64();
891 TCGv_i64 temp64_2
= tcg_temp_new_i64();
892 TCGv_i64 temp64_3
= tcg_temp_new_i64();
895 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
898 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
901 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
904 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
907 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
908 gen_add64_d(temp64_3
, temp64_2
, temp64
);
909 /* write back result */
910 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_3
);
913 tcg_temp_free_i64(temp64
);
914 tcg_temp_free_i64(temp64_2
);
915 tcg_temp_free_i64(temp64_3
);
919 gen_maddms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
920 TCGv r3
, uint32_t n
, uint32_t mode
)
922 TCGv temp
= tcg_const_i32(n
);
923 TCGv_i64 temp64
= tcg_temp_new_i64();
924 TCGv_i64 temp64_2
= tcg_temp_new_i64();
927 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
930 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
933 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
936 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
939 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
940 gen_helper_add64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
941 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
944 tcg_temp_free_i64(temp64
);
945 tcg_temp_free_i64(temp64_2
);
949 gen_maddr64_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
, uint32_t n
,
952 TCGv temp
= tcg_const_i32(n
);
953 TCGv_i64 temp64
= tcg_temp_new_i64();
956 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
959 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
962 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
965 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
968 gen_helper_addr_h(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
971 tcg_temp_free_i64(temp64
);
975 gen_maddr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
977 TCGv temp
= tcg_temp_new();
978 TCGv temp2
= tcg_temp_new();
980 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
981 tcg_gen_shli_tl(temp
, r1
, 16);
982 gen_maddr64_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
985 tcg_temp_free(temp2
);
989 gen_maddsur32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
991 TCGv temp
= tcg_const_i32(n
);
992 TCGv temp2
= tcg_temp_new();
993 TCGv_i64 temp64
= tcg_temp_new_i64();
996 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
999 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1002 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1005 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1008 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1009 tcg_gen_shli_tl(temp
, r1
, 16);
1010 gen_helper_addsur_h(ret
, cpu_env
, temp64
, temp
, temp2
);
1012 tcg_temp_free(temp
);
1013 tcg_temp_free(temp2
);
1014 tcg_temp_free_i64(temp64
);
1019 gen_maddr64s_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
,
1020 uint32_t n
, uint32_t mode
)
1022 TCGv temp
= tcg_const_i32(n
);
1023 TCGv_i64 temp64
= tcg_temp_new_i64();
1026 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1029 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1032 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1035 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1038 gen_helper_addr_h_ssov(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1040 tcg_temp_free(temp
);
1041 tcg_temp_free_i64(temp64
);
1045 gen_maddr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1047 TCGv temp
= tcg_temp_new();
1048 TCGv temp2
= tcg_temp_new();
1050 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1051 tcg_gen_shli_tl(temp
, r1
, 16);
1052 gen_maddr64s_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1054 tcg_temp_free(temp
);
1055 tcg_temp_free(temp2
);
1059 gen_maddsur32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1061 TCGv temp
= tcg_const_i32(n
);
1062 TCGv temp2
= tcg_temp_new();
1063 TCGv_i64 temp64
= tcg_temp_new_i64();
1066 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1069 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1072 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1075 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1078 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1079 tcg_gen_shli_tl(temp
, r1
, 16);
1080 gen_helper_addsur_h_ssov(ret
, cpu_env
, temp64
, temp
, temp2
);
1082 tcg_temp_free(temp
);
1083 tcg_temp_free(temp2
);
1084 tcg_temp_free_i64(temp64
);
1088 gen_maddr_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1090 TCGv temp
= tcg_const_i32(n
);
1091 gen_helper_maddr_q(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1092 tcg_temp_free(temp
);
1096 gen_maddrs_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1098 TCGv temp
= tcg_const_i32(n
);
1099 gen_helper_maddr_q_ssov(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1100 tcg_temp_free(temp
);
1104 gen_madd32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1105 uint32_t up_shift
, CPUTriCoreState
*env
)
1107 TCGv temp
= tcg_temp_new();
1108 TCGv temp2
= tcg_temp_new();
1109 TCGv temp3
= tcg_temp_new();
1110 TCGv_i64 t1
= tcg_temp_new_i64();
1111 TCGv_i64 t2
= tcg_temp_new_i64();
1112 TCGv_i64 t3
= tcg_temp_new_i64();
1114 tcg_gen_ext_i32_i64(t2
, arg2
);
1115 tcg_gen_ext_i32_i64(t3
, arg3
);
1117 tcg_gen_mul_i64(t2
, t2
, t3
);
1118 tcg_gen_shli_i64(t2
, t2
, n
);
1120 tcg_gen_ext_i32_i64(t1
, arg1
);
1121 tcg_gen_sari_i64(t2
, t2
, up_shift
);
1123 tcg_gen_add_i64(t3
, t1
, t2
);
1124 tcg_gen_extrl_i64_i32(temp3
, t3
);
1126 tcg_gen_setcondi_i64(TCG_COND_GT
, t1
, t3
, 0x7fffffffLL
);
1127 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t3
, -0x80000000LL
);
1128 tcg_gen_or_i64(t1
, t1
, t2
);
1129 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1130 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1131 /* We produce an overflow on the host if the mul before was
1132 (0x80000000 * 0x80000000) << 1). If this is the
1133 case, we negate the ovf. */
1135 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1136 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1137 tcg_gen_and_tl(temp
, temp
, temp2
);
1138 tcg_gen_shli_tl(temp
, temp
, 31);
1139 /* negate v bit, if special condition */
1140 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1143 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1144 /* Calc AV/SAV bits */
1145 tcg_gen_add_tl(cpu_PSW_AV
, temp3
, temp3
);
1146 tcg_gen_xor_tl(cpu_PSW_AV
, temp3
, cpu_PSW_AV
);
1148 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1149 /* write back result */
1150 tcg_gen_mov_tl(ret
, temp3
);
1152 tcg_temp_free(temp
);
1153 tcg_temp_free(temp2
);
1154 tcg_temp_free(temp3
);
1155 tcg_temp_free_i64(t1
);
1156 tcg_temp_free_i64(t2
);
1157 tcg_temp_free_i64(t3
);
1161 gen_m16add32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1163 TCGv temp
= tcg_temp_new();
1164 TCGv temp2
= tcg_temp_new();
1166 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1167 } else { /* n is expected to be 1 */
1168 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1169 tcg_gen_shli_tl(temp
, temp
, 1);
1170 /* catch special case r1 = r2 = 0x8000 */
1171 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1172 tcg_gen_sub_tl(temp
, temp
, temp2
);
1174 gen_add_d(ret
, arg1
, temp
);
1176 tcg_temp_free(temp
);
1177 tcg_temp_free(temp2
);
1181 gen_m16adds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
1183 TCGv temp
= tcg_temp_new();
1184 TCGv temp2
= tcg_temp_new();
1186 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1187 } else { /* n is expected to be 1 */
1188 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1189 tcg_gen_shli_tl(temp
, temp
, 1);
1190 /* catch special case r1 = r2 = 0x8000 */
1191 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1192 tcg_gen_sub_tl(temp
, temp
, temp2
);
1194 gen_adds(ret
, arg1
, temp
);
1196 tcg_temp_free(temp
);
1197 tcg_temp_free(temp2
);
1201 gen_m16add64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1202 TCGv arg3
, uint32_t n
)
1204 TCGv temp
= tcg_temp_new();
1205 TCGv temp2
= tcg_temp_new();
1206 TCGv_i64 t1
= tcg_temp_new_i64();
1207 TCGv_i64 t2
= tcg_temp_new_i64();
1208 TCGv_i64 t3
= tcg_temp_new_i64();
1211 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1212 } else { /* n is expected to be 1 */
1213 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1214 tcg_gen_shli_tl(temp
, temp
, 1);
1215 /* catch special case r1 = r2 = 0x8000 */
1216 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1217 tcg_gen_sub_tl(temp
, temp
, temp2
);
1219 tcg_gen_ext_i32_i64(t2
, temp
);
1220 tcg_gen_shli_i64(t2
, t2
, 16);
1221 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1222 gen_add64_d(t3
, t1
, t2
);
1223 /* write back result */
1224 tcg_gen_extr_i64_i32(rl
, rh
, t3
);
1226 tcg_temp_free_i64(t1
);
1227 tcg_temp_free_i64(t2
);
1228 tcg_temp_free_i64(t3
);
1229 tcg_temp_free(temp
);
1230 tcg_temp_free(temp2
);
1234 gen_m16adds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1235 TCGv arg3
, uint32_t n
)
1237 TCGv temp
= tcg_temp_new();
1238 TCGv temp2
= tcg_temp_new();
1239 TCGv_i64 t1
= tcg_temp_new_i64();
1240 TCGv_i64 t2
= tcg_temp_new_i64();
1243 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1244 } else { /* n is expected to be 1 */
1245 tcg_gen_mul_tl(temp
, arg2
, arg3
);
1246 tcg_gen_shli_tl(temp
, temp
, 1);
1247 /* catch special case r1 = r2 = 0x8000 */
1248 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
1249 tcg_gen_sub_tl(temp
, temp
, temp2
);
1251 tcg_gen_ext_i32_i64(t2
, temp
);
1252 tcg_gen_shli_i64(t2
, t2
, 16);
1253 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1255 gen_helper_add64_ssov(t1
, cpu_env
, t1
, t2
);
1256 tcg_gen_extr_i64_i32(rl
, rh
, t1
);
1258 tcg_temp_free(temp
);
1259 tcg_temp_free(temp2
);
1260 tcg_temp_free_i64(t1
);
1261 tcg_temp_free_i64(t2
);
1265 gen_madd64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1266 TCGv arg3
, uint32_t n
, CPUTriCoreState
*env
)
1268 TCGv_i64 t1
= tcg_temp_new_i64();
1269 TCGv_i64 t2
= tcg_temp_new_i64();
1270 TCGv_i64 t3
= tcg_temp_new_i64();
1271 TCGv_i64 t4
= tcg_temp_new_i64();
1274 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
1275 tcg_gen_ext_i32_i64(t2
, arg2
);
1276 tcg_gen_ext_i32_i64(t3
, arg3
);
1278 tcg_gen_mul_i64(t2
, t2
, t3
);
1280 tcg_gen_shli_i64(t2
, t2
, 1);
1282 tcg_gen_add_i64(t4
, t1
, t2
);
1284 tcg_gen_xor_i64(t3
, t4
, t1
);
1285 tcg_gen_xor_i64(t2
, t1
, t2
);
1286 tcg_gen_andc_i64(t3
, t3
, t2
);
1287 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t3
);
1288 /* We produce an overflow on the host if the mul before was
1289 (0x80000000 * 0x80000000) << 1). If this is the
1290 case, we negate the ovf. */
1292 temp
= tcg_temp_new();
1293 temp2
= tcg_temp_new();
1294 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
1295 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
1296 tcg_gen_and_tl(temp
, temp
, temp2
);
1297 tcg_gen_shli_tl(temp
, temp
, 31);
1298 /* negate v bit, if special condition */
1299 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1301 tcg_temp_free(temp
);
1302 tcg_temp_free(temp2
);
1304 /* write back result */
1305 tcg_gen_extr_i64_i32(rl
, rh
, t4
);
1307 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1308 /* Calc AV/SAV bits */
1309 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
1310 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
1312 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1314 tcg_temp_free_i64(t1
);
1315 tcg_temp_free_i64(t2
);
1316 tcg_temp_free_i64(t3
);
1317 tcg_temp_free_i64(t4
);
1321 gen_madds32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1324 TCGv_i64 t1
= tcg_temp_new_i64();
1325 TCGv_i64 t2
= tcg_temp_new_i64();
1326 TCGv_i64 t3
= tcg_temp_new_i64();
1328 tcg_gen_ext_i32_i64(t1
, arg1
);
1329 tcg_gen_ext_i32_i64(t2
, arg2
);
1330 tcg_gen_ext_i32_i64(t3
, arg3
);
1332 tcg_gen_mul_i64(t2
, t2
, t3
);
1333 tcg_gen_sari_i64(t2
, t2
, up_shift
- n
);
1335 gen_helper_madd32_q_add_ssov(ret
, cpu_env
, t1
, t2
);
1337 tcg_temp_free_i64(t1
);
1338 tcg_temp_free_i64(t2
);
1339 tcg_temp_free_i64(t3
);
1343 gen_madds64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
1344 TCGv arg3
, uint32_t n
)
1346 TCGv_i64 r1
= tcg_temp_new_i64();
1347 TCGv temp
= tcg_const_i32(n
);
1349 tcg_gen_concat_i32_i64(r1
, arg1_low
, arg1_high
);
1350 gen_helper_madd64_q_ssov(r1
, cpu_env
, r1
, arg2
, arg3
, temp
);
1351 tcg_gen_extr_i64_i32(rl
, rh
, r1
);
1353 tcg_temp_free_i64(r1
);
1354 tcg_temp_free(temp
);
1356 /* ret = r2 - (r1 * r3); */
1357 static inline void gen_msub32_d(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
)
1359 TCGv_i64 t1
= tcg_temp_new_i64();
1360 TCGv_i64 t2
= tcg_temp_new_i64();
1361 TCGv_i64 t3
= tcg_temp_new_i64();
1363 tcg_gen_ext_i32_i64(t1
, r1
);
1364 tcg_gen_ext_i32_i64(t2
, r2
);
1365 tcg_gen_ext_i32_i64(t3
, r3
);
1367 tcg_gen_mul_i64(t1
, t1
, t3
);
1368 tcg_gen_sub_i64(t1
, t2
, t1
);
1370 tcg_gen_extrl_i64_i32(ret
, t1
);
1373 tcg_gen_setcondi_i64(TCG_COND_GT
, t3
, t1
, 0x7fffffffLL
);
1374 /* result < -0x80000000 */
1375 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t1
, -0x80000000LL
);
1376 tcg_gen_or_i64(t2
, t2
, t3
);
1377 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t2
);
1378 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1381 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1382 /* Calc AV/SAV bits */
1383 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
1384 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
1386 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1388 tcg_temp_free_i64(t1
);
1389 tcg_temp_free_i64(t2
);
1390 tcg_temp_free_i64(t3
);
1393 static inline void gen_msubi32_d(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
1395 TCGv temp
= tcg_const_i32(con
);
1396 gen_msub32_d(ret
, r1
, r2
, temp
);
1397 tcg_temp_free(temp
);
1401 gen_msub64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1404 TCGv t1
= tcg_temp_new();
1405 TCGv t2
= tcg_temp_new();
1406 TCGv t3
= tcg_temp_new();
1407 TCGv t4
= tcg_temp_new();
1409 tcg_gen_muls2_tl(t1
, t2
, r1
, r3
);
1410 /* only the sub can overflow */
1411 tcg_gen_sub2_tl(t3
, t4
, r2_low
, r2_high
, t1
, t2
);
1413 tcg_gen_xor_tl(cpu_PSW_V
, t4
, r2_high
);
1414 tcg_gen_xor_tl(t1
, r2_high
, t2
);
1415 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, t1
);
1417 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1418 /* Calc AV/SAV bits */
1419 tcg_gen_add_tl(cpu_PSW_AV
, t4
, t4
);
1420 tcg_gen_xor_tl(cpu_PSW_AV
, t4
, cpu_PSW_AV
);
1422 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1423 /* write back the result */
1424 tcg_gen_mov_tl(ret_low
, t3
);
1425 tcg_gen_mov_tl(ret_high
, t4
);
1434 gen_msubi64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1437 TCGv temp
= tcg_const_i32(con
);
1438 gen_msub64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1439 tcg_temp_free(temp
);
1443 gen_msubu64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1446 TCGv_i64 t1
= tcg_temp_new_i64();
1447 TCGv_i64 t2
= tcg_temp_new_i64();
1448 TCGv_i64 t3
= tcg_temp_new_i64();
1450 tcg_gen_extu_i32_i64(t1
, r1
);
1451 tcg_gen_concat_i32_i64(t2
, r2_low
, r2_high
);
1452 tcg_gen_extu_i32_i64(t3
, r3
);
1454 tcg_gen_mul_i64(t1
, t1
, t3
);
1455 tcg_gen_sub_i64(t3
, t2
, t1
);
1456 tcg_gen_extr_i64_i32(ret_low
, ret_high
, t3
);
1457 /* calc V bit, only the sub can overflow, if t1 > t2 */
1458 tcg_gen_setcond_i64(TCG_COND_GTU
, t1
, t1
, t2
);
1459 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1460 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1462 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1463 /* Calc AV/SAV bits */
1464 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
1465 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
1467 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1469 tcg_temp_free_i64(t1
);
1470 tcg_temp_free_i64(t2
);
1471 tcg_temp_free_i64(t3
);
1475 gen_msubui64_d(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
1478 TCGv temp
= tcg_const_i32(con
);
1479 gen_msubu64_d(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
1480 tcg_temp_free(temp
);
1483 static inline void gen_addi_d(TCGv ret
, TCGv r1
, target_ulong r2
)
1485 TCGv temp
= tcg_const_i32(r2
);
1486 gen_add_d(ret
, r1
, temp
);
1487 tcg_temp_free(temp
);
1489 /* calculate the carry bit too */
1490 static inline void gen_add_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1492 TCGv t0
= tcg_temp_new_i32();
1493 TCGv result
= tcg_temp_new_i32();
1495 tcg_gen_movi_tl(t0
, 0);
1496 /* Addition and set C/V/SV bits */
1497 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, r2
, t0
);
1499 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1500 tcg_gen_xor_tl(t0
, r1
, r2
);
1501 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1503 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1504 /* Calc AV/SAV bits */
1505 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1506 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1508 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1509 /* write back result */
1510 tcg_gen_mov_tl(ret
, result
);
1512 tcg_temp_free(result
);
1516 static inline void gen_addi_CC(TCGv ret
, TCGv r1
, int32_t con
)
1518 TCGv temp
= tcg_const_i32(con
);
1519 gen_add_CC(ret
, r1
, temp
);
1520 tcg_temp_free(temp
);
1523 static inline void gen_addc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1525 TCGv carry
= tcg_temp_new_i32();
1526 TCGv t0
= tcg_temp_new_i32();
1527 TCGv result
= tcg_temp_new_i32();
1529 tcg_gen_movi_tl(t0
, 0);
1530 tcg_gen_setcondi_tl(TCG_COND_NE
, carry
, cpu_PSW_C
, 0);
1531 /* Addition, carry and set C/V/SV bits */
1532 tcg_gen_add2_i32(result
, cpu_PSW_C
, r1
, t0
, carry
, t0
);
1533 tcg_gen_add2_i32(result
, cpu_PSW_C
, result
, cpu_PSW_C
, r2
, t0
);
1535 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1536 tcg_gen_xor_tl(t0
, r1
, r2
);
1537 tcg_gen_andc_tl(cpu_PSW_V
, cpu_PSW_V
, t0
);
1539 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1540 /* Calc AV/SAV bits */
1541 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1542 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1544 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1545 /* write back result */
1546 tcg_gen_mov_tl(ret
, result
);
1548 tcg_temp_free(result
);
1550 tcg_temp_free(carry
);
1553 static inline void gen_addci_CC(TCGv ret
, TCGv r1
, int32_t con
)
1555 TCGv temp
= tcg_const_i32(con
);
1556 gen_addc_CC(ret
, r1
, temp
);
1557 tcg_temp_free(temp
);
1560 static inline void gen_cond_add(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1563 TCGv temp
= tcg_temp_new();
1564 TCGv temp2
= tcg_temp_new();
1565 TCGv result
= tcg_temp_new();
1566 TCGv mask
= tcg_temp_new();
1567 TCGv t0
= tcg_const_i32(0);
1569 /* create mask for sticky bits */
1570 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1571 tcg_gen_shli_tl(mask
, mask
, 31);
1573 tcg_gen_add_tl(result
, r1
, r2
);
1575 tcg_gen_xor_tl(temp
, result
, r1
);
1576 tcg_gen_xor_tl(temp2
, r1
, r2
);
1577 tcg_gen_andc_tl(temp
, temp
, temp2
);
1578 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1580 tcg_gen_and_tl(temp
, temp
, mask
);
1581 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1583 tcg_gen_add_tl(temp
, result
, result
);
1584 tcg_gen_xor_tl(temp
, temp
, result
);
1585 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1587 tcg_gen_and_tl(temp
, temp
, mask
);
1588 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1589 /* write back result */
1590 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1593 tcg_temp_free(temp
);
1594 tcg_temp_free(temp2
);
1595 tcg_temp_free(result
);
1596 tcg_temp_free(mask
);
1599 static inline void gen_condi_add(TCGCond cond
, TCGv r1
, int32_t r2
,
1602 TCGv temp
= tcg_const_i32(r2
);
1603 gen_cond_add(cond
, r1
, temp
, r3
, r4
);
1604 tcg_temp_free(temp
);
1607 static inline void gen_sub_d(TCGv ret
, TCGv r1
, TCGv r2
)
1609 TCGv temp
= tcg_temp_new_i32();
1610 TCGv result
= tcg_temp_new_i32();
1612 tcg_gen_sub_tl(result
, r1
, r2
);
1614 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1615 tcg_gen_xor_tl(temp
, r1
, r2
);
1616 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1618 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1620 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1621 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1623 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1624 /* write back result */
1625 tcg_gen_mov_tl(ret
, result
);
1627 tcg_temp_free(temp
);
1628 tcg_temp_free(result
);
1632 gen_sub64_d(TCGv_i64 ret
, TCGv_i64 r1
, TCGv_i64 r2
)
1634 TCGv temp
= tcg_temp_new();
1635 TCGv_i64 t0
= tcg_temp_new_i64();
1636 TCGv_i64 t1
= tcg_temp_new_i64();
1637 TCGv_i64 result
= tcg_temp_new_i64();
1639 tcg_gen_sub_i64(result
, r1
, r2
);
1641 tcg_gen_xor_i64(t1
, result
, r1
);
1642 tcg_gen_xor_i64(t0
, r1
, r2
);
1643 tcg_gen_and_i64(t1
, t1
, t0
);
1644 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t1
);
1646 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1647 /* calc AV/SAV bits */
1648 tcg_gen_extrh_i64_i32(temp
, result
);
1649 tcg_gen_add_tl(cpu_PSW_AV
, temp
, temp
);
1650 tcg_gen_xor_tl(cpu_PSW_AV
, temp
, cpu_PSW_AV
);
1652 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1653 /* write back result */
1654 tcg_gen_mov_i64(ret
, result
);
1656 tcg_temp_free(temp
);
1657 tcg_temp_free_i64(result
);
1658 tcg_temp_free_i64(t0
);
1659 tcg_temp_free_i64(t1
);
1662 static inline void gen_sub_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1664 TCGv result
= tcg_temp_new();
1665 TCGv temp
= tcg_temp_new();
1667 tcg_gen_sub_tl(result
, r1
, r2
);
1669 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_PSW_C
, r1
, r2
);
1671 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
1672 tcg_gen_xor_tl(temp
, r1
, r2
);
1673 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1675 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1677 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
1678 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
1680 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
1681 /* write back result */
1682 tcg_gen_mov_tl(ret
, result
);
1684 tcg_temp_free(result
);
1685 tcg_temp_free(temp
);
1688 static inline void gen_subc_CC(TCGv ret
, TCGv r1
, TCGv r2
)
1690 TCGv temp
= tcg_temp_new();
1691 tcg_gen_not_tl(temp
, r2
);
1692 gen_addc_CC(ret
, r1
, temp
);
1693 tcg_temp_free(temp
);
1696 static inline void gen_cond_sub(TCGCond cond
, TCGv r1
, TCGv r2
, TCGv r3
,
1699 TCGv temp
= tcg_temp_new();
1700 TCGv temp2
= tcg_temp_new();
1701 TCGv result
= tcg_temp_new();
1702 TCGv mask
= tcg_temp_new();
1703 TCGv t0
= tcg_const_i32(0);
1705 /* create mask for sticky bits */
1706 tcg_gen_setcond_tl(cond
, mask
, r4
, t0
);
1707 tcg_gen_shli_tl(mask
, mask
, 31);
1709 tcg_gen_sub_tl(result
, r1
, r2
);
1711 tcg_gen_xor_tl(temp
, result
, r1
);
1712 tcg_gen_xor_tl(temp2
, r1
, r2
);
1713 tcg_gen_and_tl(temp
, temp
, temp2
);
1714 tcg_gen_movcond_tl(cond
, cpu_PSW_V
, r4
, t0
, temp
, cpu_PSW_V
);
1716 tcg_gen_and_tl(temp
, temp
, mask
);
1717 tcg_gen_or_tl(cpu_PSW_SV
, temp
, cpu_PSW_SV
);
1719 tcg_gen_add_tl(temp
, result
, result
);
1720 tcg_gen_xor_tl(temp
, temp
, result
);
1721 tcg_gen_movcond_tl(cond
, cpu_PSW_AV
, r4
, t0
, temp
, cpu_PSW_AV
);
1723 tcg_gen_and_tl(temp
, temp
, mask
);
1724 tcg_gen_or_tl(cpu_PSW_SAV
, temp
, cpu_PSW_SAV
);
1725 /* write back result */
1726 tcg_gen_movcond_tl(cond
, r3
, r4
, t0
, result
, r1
);
1729 tcg_temp_free(temp
);
1730 tcg_temp_free(temp2
);
1731 tcg_temp_free(result
);
1732 tcg_temp_free(mask
);
1736 gen_msub_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1737 TCGv r3
, uint32_t n
, uint32_t mode
)
1739 TCGv temp
= tcg_const_i32(n
);
1740 TCGv temp2
= tcg_temp_new();
1741 TCGv_i64 temp64
= tcg_temp_new_i64();
1744 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1747 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1750 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1753 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1756 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
1757 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
1758 tcg_gen_sub_tl
, tcg_gen_sub_tl
);
1759 tcg_temp_free(temp
);
1760 tcg_temp_free(temp2
);
1761 tcg_temp_free_i64(temp64
);
1765 gen_msubs_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1766 TCGv r3
, uint32_t n
, uint32_t mode
)
1768 TCGv temp
= tcg_const_i32(n
);
1769 TCGv temp2
= tcg_temp_new();
1770 TCGv temp3
= tcg_temp_new();
1771 TCGv_i64 temp64
= tcg_temp_new_i64();
1775 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1778 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1781 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1784 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1787 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
1788 gen_subs(ret_low
, r1_low
, temp
);
1789 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
1790 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
1791 gen_subs(ret_high
, r1_high
, temp2
);
1792 /* combine v bits */
1793 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
1794 /* combine av bits */
1795 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
1797 tcg_temp_free(temp
);
1798 tcg_temp_free(temp2
);
1799 tcg_temp_free(temp3
);
1800 tcg_temp_free_i64(temp64
);
1804 gen_msubm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1805 TCGv r3
, uint32_t n
, uint32_t mode
)
1807 TCGv temp
= tcg_const_i32(n
);
1808 TCGv_i64 temp64
= tcg_temp_new_i64();
1809 TCGv_i64 temp64_2
= tcg_temp_new_i64();
1810 TCGv_i64 temp64_3
= tcg_temp_new_i64();
1813 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
1816 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
1819 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
1822 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
1825 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
1826 gen_sub64_d(temp64_3
, temp64_2
, temp64
);
1827 /* write back result */
1828 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_3
);
1830 tcg_temp_free(temp
);
1831 tcg_temp_free_i64(temp64
);
1832 tcg_temp_free_i64(temp64_2
);
1833 tcg_temp_free_i64(temp64_3
);
1837 gen_msubms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
1838 TCGv r3
, uint32_t n
, uint32_t mode
)
1840 TCGv temp
= tcg_const_i32(n
);
1841 TCGv_i64 temp64
= tcg_temp_new_i64();
1842 TCGv_i64 temp64_2
= tcg_temp_new_i64();
1845 GEN_HELPER_LL(mulm_h
, temp64
, r2
, r3
, temp
);
1848 GEN_HELPER_LU(mulm_h
, temp64
, r2
, r3
, temp
);
1851 GEN_HELPER_UL(mulm_h
, temp64
, r2
, r3
, temp
);
1854 GEN_HELPER_UU(mulm_h
, temp64
, r2
, r3
, temp
);
1857 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
1858 gen_helper_sub64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
1859 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
1861 tcg_temp_free(temp
);
1862 tcg_temp_free_i64(temp64
);
1863 tcg_temp_free_i64(temp64_2
);
1867 gen_msubr64_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
, uint32_t n
,
1870 TCGv temp
= tcg_const_i32(n
);
1871 TCGv_i64 temp64
= tcg_temp_new_i64();
1874 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1877 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1880 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1883 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1886 gen_helper_subr_h(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1888 tcg_temp_free(temp
);
1889 tcg_temp_free_i64(temp64
);
1893 gen_msubr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1895 TCGv temp
= tcg_temp_new();
1896 TCGv temp2
= tcg_temp_new();
1898 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1899 tcg_gen_shli_tl(temp
, r1
, 16);
1900 gen_msubr64_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1902 tcg_temp_free(temp
);
1903 tcg_temp_free(temp2
);
1907 gen_msubr64s_h(TCGv ret
, TCGv r1_low
, TCGv r1_high
, TCGv r2
, TCGv r3
,
1908 uint32_t n
, uint32_t mode
)
1910 TCGv temp
= tcg_const_i32(n
);
1911 TCGv_i64 temp64
= tcg_temp_new_i64();
1914 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
1917 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
1920 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
1923 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
1926 gen_helper_subr_h_ssov(ret
, cpu_env
, temp64
, r1_low
, r1_high
);
1928 tcg_temp_free(temp
);
1929 tcg_temp_free_i64(temp64
);
1933 gen_msubr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
1935 TCGv temp
= tcg_temp_new();
1936 TCGv temp2
= tcg_temp_new();
1938 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
1939 tcg_gen_shli_tl(temp
, r1
, 16);
1940 gen_msubr64s_h(ret
, temp
, temp2
, r2
, r3
, n
, mode
);
1942 tcg_temp_free(temp
);
1943 tcg_temp_free(temp2
);
1947 gen_msubr_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1949 TCGv temp
= tcg_const_i32(n
);
1950 gen_helper_msubr_q(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1951 tcg_temp_free(temp
);
1955 gen_msubrs_q(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
)
1957 TCGv temp
= tcg_const_i32(n
);
1958 gen_helper_msubr_q_ssov(ret
, cpu_env
, r1
, r2
, r3
, temp
);
1959 tcg_temp_free(temp
);
1963 gen_msub32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
1964 uint32_t up_shift
, CPUTriCoreState
*env
)
1966 TCGv temp
= tcg_temp_new();
1967 TCGv temp2
= tcg_temp_new();
1968 TCGv temp3
= tcg_temp_new();
1969 TCGv_i64 t1
= tcg_temp_new_i64();
1970 TCGv_i64 t2
= tcg_temp_new_i64();
1971 TCGv_i64 t3
= tcg_temp_new_i64();
1972 TCGv_i64 t4
= tcg_temp_new_i64();
1974 tcg_gen_ext_i32_i64(t2
, arg2
);
1975 tcg_gen_ext_i32_i64(t3
, arg3
);
1977 tcg_gen_mul_i64(t2
, t2
, t3
);
1979 tcg_gen_ext_i32_i64(t1
, arg1
);
1980 /* if we shift part of the fraction out, we need to round up */
1981 tcg_gen_andi_i64(t4
, t2
, (1ll << (up_shift
- n
)) - 1);
1982 tcg_gen_setcondi_i64(TCG_COND_NE
, t4
, t4
, 0);
1983 tcg_gen_sari_i64(t2
, t2
, up_shift
- n
);
1984 tcg_gen_add_i64(t2
, t2
, t4
);
1986 tcg_gen_sub_i64(t3
, t1
, t2
);
1987 tcg_gen_extrl_i64_i32(temp3
, t3
);
1989 tcg_gen_setcondi_i64(TCG_COND_GT
, t1
, t3
, 0x7fffffffLL
);
1990 tcg_gen_setcondi_i64(TCG_COND_LT
, t2
, t3
, -0x80000000LL
);
1991 tcg_gen_or_i64(t1
, t1
, t2
);
1992 tcg_gen_extrl_i64_i32(cpu_PSW_V
, t1
);
1993 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
1995 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
1996 /* Calc AV/SAV bits */
1997 tcg_gen_add_tl(cpu_PSW_AV
, temp3
, temp3
);
1998 tcg_gen_xor_tl(cpu_PSW_AV
, temp3
, cpu_PSW_AV
);
2000 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2001 /* write back result */
2002 tcg_gen_mov_tl(ret
, temp3
);
2004 tcg_temp_free(temp
);
2005 tcg_temp_free(temp2
);
2006 tcg_temp_free(temp3
);
2007 tcg_temp_free_i64(t1
);
2008 tcg_temp_free_i64(t2
);
2009 tcg_temp_free_i64(t3
);
2010 tcg_temp_free_i64(t4
);
2014 gen_m16sub32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
2016 TCGv temp
= tcg_temp_new();
2017 TCGv temp2
= tcg_temp_new();
2019 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2020 } else { /* n is expected to be 1 */
2021 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2022 tcg_gen_shli_tl(temp
, temp
, 1);
2023 /* catch special case r1 = r2 = 0x8000 */
2024 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2025 tcg_gen_sub_tl(temp
, temp
, temp2
);
2027 gen_sub_d(ret
, arg1
, temp
);
2029 tcg_temp_free(temp
);
2030 tcg_temp_free(temp2
);
2034 gen_m16subs32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
)
2036 TCGv temp
= tcg_temp_new();
2037 TCGv temp2
= tcg_temp_new();
2039 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2040 } else { /* n is expected to be 1 */
2041 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2042 tcg_gen_shli_tl(temp
, temp
, 1);
2043 /* catch special case r1 = r2 = 0x8000 */
2044 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2045 tcg_gen_sub_tl(temp
, temp
, temp2
);
2047 gen_subs(ret
, arg1
, temp
);
2049 tcg_temp_free(temp
);
2050 tcg_temp_free(temp2
);
2054 gen_m16sub64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2055 TCGv arg3
, uint32_t n
)
2057 TCGv temp
= tcg_temp_new();
2058 TCGv temp2
= tcg_temp_new();
2059 TCGv_i64 t1
= tcg_temp_new_i64();
2060 TCGv_i64 t2
= tcg_temp_new_i64();
2061 TCGv_i64 t3
= tcg_temp_new_i64();
2064 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2065 } else { /* n is expected to be 1 */
2066 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2067 tcg_gen_shli_tl(temp
, temp
, 1);
2068 /* catch special case r1 = r2 = 0x8000 */
2069 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2070 tcg_gen_sub_tl(temp
, temp
, temp2
);
2072 tcg_gen_ext_i32_i64(t2
, temp
);
2073 tcg_gen_shli_i64(t2
, t2
, 16);
2074 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2075 gen_sub64_d(t3
, t1
, t2
);
2076 /* write back result */
2077 tcg_gen_extr_i64_i32(rl
, rh
, t3
);
2079 tcg_temp_free_i64(t1
);
2080 tcg_temp_free_i64(t2
);
2081 tcg_temp_free_i64(t3
);
2082 tcg_temp_free(temp
);
2083 tcg_temp_free(temp2
);
2087 gen_m16subs64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2088 TCGv arg3
, uint32_t n
)
2090 TCGv temp
= tcg_temp_new();
2091 TCGv temp2
= tcg_temp_new();
2092 TCGv_i64 t1
= tcg_temp_new_i64();
2093 TCGv_i64 t2
= tcg_temp_new_i64();
2096 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2097 } else { /* n is expected to be 1 */
2098 tcg_gen_mul_tl(temp
, arg2
, arg3
);
2099 tcg_gen_shli_tl(temp
, temp
, 1);
2100 /* catch special case r1 = r2 = 0x8000 */
2101 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, temp
, 0x80000000);
2102 tcg_gen_sub_tl(temp
, temp
, temp2
);
2104 tcg_gen_ext_i32_i64(t2
, temp
);
2105 tcg_gen_shli_i64(t2
, t2
, 16);
2106 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2108 gen_helper_sub64_ssov(t1
, cpu_env
, t1
, t2
);
2109 tcg_gen_extr_i64_i32(rl
, rh
, t1
);
2111 tcg_temp_free(temp
);
2112 tcg_temp_free(temp2
);
2113 tcg_temp_free_i64(t1
);
2114 tcg_temp_free_i64(t2
);
2118 gen_msub64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2119 TCGv arg3
, uint32_t n
, CPUTriCoreState
*env
)
2121 TCGv_i64 t1
= tcg_temp_new_i64();
2122 TCGv_i64 t2
= tcg_temp_new_i64();
2123 TCGv_i64 t3
= tcg_temp_new_i64();
2124 TCGv_i64 t4
= tcg_temp_new_i64();
2127 tcg_gen_concat_i32_i64(t1
, arg1_low
, arg1_high
);
2128 tcg_gen_ext_i32_i64(t2
, arg2
);
2129 tcg_gen_ext_i32_i64(t3
, arg3
);
2131 tcg_gen_mul_i64(t2
, t2
, t3
);
2133 tcg_gen_shli_i64(t2
, t2
, 1);
2135 tcg_gen_sub_i64(t4
, t1
, t2
);
2137 tcg_gen_xor_i64(t3
, t4
, t1
);
2138 tcg_gen_xor_i64(t2
, t1
, t2
);
2139 tcg_gen_and_i64(t3
, t3
, t2
);
2140 tcg_gen_extrh_i64_i32(cpu_PSW_V
, t3
);
2141 /* We produce an overflow on the host if the mul before was
2142 (0x80000000 * 0x80000000) << 1). If this is the
2143 case, we negate the ovf. */
2145 temp
= tcg_temp_new();
2146 temp2
= tcg_temp_new();
2147 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, arg2
, 0x80000000);
2148 tcg_gen_setcond_tl(TCG_COND_EQ
, temp2
, arg2
, arg3
);
2149 tcg_gen_and_tl(temp
, temp
, temp2
);
2150 tcg_gen_shli_tl(temp
, temp
, 31);
2151 /* negate v bit, if special condition */
2152 tcg_gen_xor_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2154 tcg_temp_free(temp
);
2155 tcg_temp_free(temp2
);
2157 /* write back result */
2158 tcg_gen_extr_i64_i32(rl
, rh
, t4
);
2160 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2161 /* Calc AV/SAV bits */
2162 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
2163 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
2165 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2167 tcg_temp_free_i64(t1
);
2168 tcg_temp_free_i64(t2
);
2169 tcg_temp_free_i64(t3
);
2170 tcg_temp_free_i64(t4
);
2174 gen_msubs32_q(TCGv ret
, TCGv arg1
, TCGv arg2
, TCGv arg3
, uint32_t n
,
2177 TCGv_i64 t1
= tcg_temp_new_i64();
2178 TCGv_i64 t2
= tcg_temp_new_i64();
2179 TCGv_i64 t3
= tcg_temp_new_i64();
2180 TCGv_i64 t4
= tcg_temp_new_i64();
2182 tcg_gen_ext_i32_i64(t1
, arg1
);
2183 tcg_gen_ext_i32_i64(t2
, arg2
);
2184 tcg_gen_ext_i32_i64(t3
, arg3
);
2186 tcg_gen_mul_i64(t2
, t2
, t3
);
2187 /* if we shift part of the fraction out, we need to round up */
2188 tcg_gen_andi_i64(t4
, t2
, (1ll << (up_shift
- n
)) - 1);
2189 tcg_gen_setcondi_i64(TCG_COND_NE
, t4
, t4
, 0);
2190 tcg_gen_sari_i64(t3
, t2
, up_shift
- n
);
2191 tcg_gen_add_i64(t3
, t3
, t4
);
2193 gen_helper_msub32_q_sub_ssov(ret
, cpu_env
, t1
, t3
);
2195 tcg_temp_free_i64(t1
);
2196 tcg_temp_free_i64(t2
);
2197 tcg_temp_free_i64(t3
);
2198 tcg_temp_free_i64(t4
);
2202 gen_msubs64_q(TCGv rl
, TCGv rh
, TCGv arg1_low
, TCGv arg1_high
, TCGv arg2
,
2203 TCGv arg3
, uint32_t n
)
2205 TCGv_i64 r1
= tcg_temp_new_i64();
2206 TCGv temp
= tcg_const_i32(n
);
2208 tcg_gen_concat_i32_i64(r1
, arg1_low
, arg1_high
);
2209 gen_helper_msub64_q_ssov(r1
, cpu_env
, r1
, arg2
, arg3
, temp
);
2210 tcg_gen_extr_i64_i32(rl
, rh
, r1
);
2212 tcg_temp_free_i64(r1
);
2213 tcg_temp_free(temp
);
2217 gen_msubad_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2218 TCGv r3
, uint32_t n
, uint32_t mode
)
2220 TCGv temp
= tcg_const_i32(n
);
2221 TCGv temp2
= tcg_temp_new();
2222 TCGv_i64 temp64
= tcg_temp_new_i64();
2225 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2228 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2231 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2234 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2237 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
2238 gen_addsub64_h(ret_low
, ret_high
, r1_low
, r1_high
, temp
, temp2
,
2239 tcg_gen_add_tl
, tcg_gen_sub_tl
);
2240 tcg_temp_free(temp
);
2241 tcg_temp_free(temp2
);
2242 tcg_temp_free_i64(temp64
);
2246 gen_msubadm_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2247 TCGv r3
, uint32_t n
, uint32_t mode
)
2249 TCGv temp
= tcg_const_i32(n
);
2250 TCGv_i64 temp64
= tcg_temp_new_i64();
2251 TCGv_i64 temp64_2
= tcg_temp_new_i64();
2252 TCGv_i64 temp64_3
= tcg_temp_new_i64();
2255 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2258 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2261 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2264 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2267 tcg_gen_concat_i32_i64(temp64_3
, r1_low
, r1_high
);
2268 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
2269 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
2270 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
2271 tcg_gen_shli_i64(temp64
, temp64
, 16);
2273 gen_sub64_d(temp64_2
, temp64_3
, temp64
);
2274 /* write back result */
2275 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64_2
);
2277 tcg_temp_free(temp
);
2278 tcg_temp_free_i64(temp64
);
2279 tcg_temp_free_i64(temp64_2
);
2280 tcg_temp_free_i64(temp64_3
);
2284 gen_msubadr32_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
2286 TCGv temp
= tcg_const_i32(n
);
2287 TCGv temp2
= tcg_temp_new();
2288 TCGv_i64 temp64
= tcg_temp_new_i64();
2291 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2294 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2297 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2300 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2303 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
2304 tcg_gen_shli_tl(temp
, r1
, 16);
2305 gen_helper_subadr_h(ret
, cpu_env
, temp64
, temp
, temp2
);
2307 tcg_temp_free(temp
);
2308 tcg_temp_free(temp2
);
2309 tcg_temp_free_i64(temp64
);
2313 gen_msubads_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2314 TCGv r3
, uint32_t n
, uint32_t mode
)
2316 TCGv temp
= tcg_const_i32(n
);
2317 TCGv temp2
= tcg_temp_new();
2318 TCGv temp3
= tcg_temp_new();
2319 TCGv_i64 temp64
= tcg_temp_new_i64();
2323 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2326 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2329 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2332 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2335 tcg_gen_extr_i64_i32(temp
, temp2
, temp64
);
2336 gen_adds(ret_low
, r1_low
, temp
);
2337 tcg_gen_mov_tl(temp
, cpu_PSW_V
);
2338 tcg_gen_mov_tl(temp3
, cpu_PSW_AV
);
2339 gen_subs(ret_high
, r1_high
, temp2
);
2340 /* combine v bits */
2341 tcg_gen_or_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2342 /* combine av bits */
2343 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp3
);
2345 tcg_temp_free(temp
);
2346 tcg_temp_free(temp2
);
2347 tcg_temp_free(temp3
);
2348 tcg_temp_free_i64(temp64
);
2352 gen_msubadms_h(TCGv ret_low
, TCGv ret_high
, TCGv r1_low
, TCGv r1_high
, TCGv r2
,
2353 TCGv r3
, uint32_t n
, uint32_t mode
)
2355 TCGv temp
= tcg_const_i32(n
);
2356 TCGv_i64 temp64
= tcg_temp_new_i64();
2357 TCGv_i64 temp64_2
= tcg_temp_new_i64();
2361 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2364 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2367 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2370 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2373 tcg_gen_sari_i64(temp64_2
, temp64
, 32); /* high */
2374 tcg_gen_ext32s_i64(temp64
, temp64
); /* low */
2375 tcg_gen_sub_i64(temp64
, temp64_2
, temp64
);
2376 tcg_gen_shli_i64(temp64
, temp64
, 16);
2377 tcg_gen_concat_i32_i64(temp64_2
, r1_low
, r1_high
);
2379 gen_helper_sub64_ssov(temp64
, cpu_env
, temp64_2
, temp64
);
2380 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2382 tcg_temp_free(temp
);
2383 tcg_temp_free_i64(temp64
);
2384 tcg_temp_free_i64(temp64_2
);
2388 gen_msubadr32s_h(TCGv ret
, TCGv r1
, TCGv r2
, TCGv r3
, uint32_t n
, uint32_t mode
)
2390 TCGv temp
= tcg_const_i32(n
);
2391 TCGv temp2
= tcg_temp_new();
2392 TCGv_i64 temp64
= tcg_temp_new_i64();
2395 GEN_HELPER_LL(mul_h
, temp64
, r2
, r3
, temp
);
2398 GEN_HELPER_LU(mul_h
, temp64
, r2
, r3
, temp
);
2401 GEN_HELPER_UL(mul_h
, temp64
, r2
, r3
, temp
);
2404 GEN_HELPER_UU(mul_h
, temp64
, r2
, r3
, temp
);
2407 tcg_gen_andi_tl(temp2
, r1
, 0xffff0000);
2408 tcg_gen_shli_tl(temp
, r1
, 16);
2409 gen_helper_subadr_h_ssov(ret
, cpu_env
, temp64
, temp
, temp2
);
2411 tcg_temp_free(temp
);
2412 tcg_temp_free(temp2
);
2413 tcg_temp_free_i64(temp64
);
2416 static inline void gen_abs(TCGv ret
, TCGv r1
)
2418 TCGv temp
= tcg_temp_new();
2419 TCGv t0
= tcg_const_i32(0);
2421 tcg_gen_neg_tl(temp
, r1
);
2422 tcg_gen_movcond_tl(TCG_COND_GE
, ret
, r1
, t0
, r1
, temp
);
2423 /* overflow can only happen, if r1 = 0x80000000 */
2424 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, r1
, 0x80000000);
2425 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2427 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2429 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2430 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2432 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2434 tcg_temp_free(temp
);
2438 static inline void gen_absdif(TCGv ret
, TCGv r1
, TCGv r2
)
2440 TCGv temp
= tcg_temp_new_i32();
2441 TCGv result
= tcg_temp_new_i32();
2443 tcg_gen_sub_tl(result
, r1
, r2
);
2444 tcg_gen_sub_tl(temp
, r2
, r1
);
2445 tcg_gen_movcond_tl(TCG_COND_GT
, result
, r1
, r2
, result
, temp
);
2448 tcg_gen_xor_tl(cpu_PSW_V
, result
, r1
);
2449 tcg_gen_xor_tl(temp
, result
, r2
);
2450 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_PSW_V
, r1
, r2
, cpu_PSW_V
, temp
);
2451 tcg_gen_xor_tl(temp
, r1
, r2
);
2452 tcg_gen_and_tl(cpu_PSW_V
, cpu_PSW_V
, temp
);
2454 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2456 tcg_gen_add_tl(cpu_PSW_AV
, result
, result
);
2457 tcg_gen_xor_tl(cpu_PSW_AV
, result
, cpu_PSW_AV
);
2459 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2460 /* write back result */
2461 tcg_gen_mov_tl(ret
, result
);
2463 tcg_temp_free(temp
);
2464 tcg_temp_free(result
);
2467 static inline void gen_absdifi(TCGv ret
, TCGv r1
, int32_t con
)
2469 TCGv temp
= tcg_const_i32(con
);
2470 gen_absdif(ret
, r1
, temp
);
2471 tcg_temp_free(temp
);
2474 static inline void gen_absdifsi(TCGv ret
, TCGv r1
, int32_t con
)
2476 TCGv temp
= tcg_const_i32(con
);
2477 gen_helper_absdif_ssov(ret
, cpu_env
, r1
, temp
);
2478 tcg_temp_free(temp
);
2481 static inline void gen_mul_i32s(TCGv ret
, TCGv r1
, TCGv r2
)
2483 TCGv high
= tcg_temp_new();
2484 TCGv low
= tcg_temp_new();
2486 tcg_gen_muls2_tl(low
, high
, r1
, r2
);
2487 tcg_gen_mov_tl(ret
, low
);
2489 tcg_gen_sari_tl(low
, low
, 31);
2490 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_PSW_V
, high
, low
);
2491 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2493 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2495 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2496 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2498 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2500 tcg_temp_free(high
);
2504 static inline void gen_muli_i32s(TCGv ret
, TCGv r1
, int32_t con
)
2506 TCGv temp
= tcg_const_i32(con
);
2507 gen_mul_i32s(ret
, r1
, temp
);
2508 tcg_temp_free(temp
);
2511 static inline void gen_mul_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
2513 tcg_gen_muls2_tl(ret_low
, ret_high
, r1
, r2
);
2515 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2517 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2519 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
2520 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
2522 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2525 static inline void gen_muli_i64s(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
2528 TCGv temp
= tcg_const_i32(con
);
2529 gen_mul_i64s(ret_low
, ret_high
, r1
, temp
);
2530 tcg_temp_free(temp
);
2533 static inline void gen_mul_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2
)
2535 tcg_gen_mulu2_tl(ret_low
, ret_high
, r1
, r2
);
2537 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2539 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2541 tcg_gen_add_tl(cpu_PSW_AV
, ret_high
, ret_high
);
2542 tcg_gen_xor_tl(cpu_PSW_AV
, ret_high
, cpu_PSW_AV
);
2544 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2547 static inline void gen_muli_i64u(TCGv ret_low
, TCGv ret_high
, TCGv r1
,
2550 TCGv temp
= tcg_const_i32(con
);
2551 gen_mul_i64u(ret_low
, ret_high
, r1
, temp
);
2552 tcg_temp_free(temp
);
2555 static inline void gen_mulsi_i32(TCGv ret
, TCGv r1
, int32_t con
)
2557 TCGv temp
= tcg_const_i32(con
);
2558 gen_helper_mul_ssov(ret
, cpu_env
, r1
, temp
);
2559 tcg_temp_free(temp
);
2562 static inline void gen_mulsui_i32(TCGv ret
, TCGv r1
, int32_t con
)
2564 TCGv temp
= tcg_const_i32(con
);
2565 gen_helper_mul_suov(ret
, cpu_env
, r1
, temp
);
2566 tcg_temp_free(temp
);
2568 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2569 static inline void gen_maddsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2571 TCGv temp
= tcg_const_i32(con
);
2572 gen_helper_madd32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
2573 tcg_temp_free(temp
);
2576 static inline void gen_maddsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2578 TCGv temp
= tcg_const_i32(con
);
2579 gen_helper_madd32_suov(ret
, cpu_env
, r1
, r2
, temp
);
2580 tcg_temp_free(temp
);
2584 gen_mul_q(TCGv rl
, TCGv rh
, TCGv arg1
, TCGv arg2
, uint32_t n
, uint32_t up_shift
)
2586 TCGv temp
= tcg_temp_new();
2587 TCGv_i64 temp_64
= tcg_temp_new_i64();
2588 TCGv_i64 temp2_64
= tcg_temp_new_i64();
2591 if (up_shift
== 32) {
2592 tcg_gen_muls2_tl(rh
, rl
, arg1
, arg2
);
2593 } else if (up_shift
== 16) {
2594 tcg_gen_ext_i32_i64(temp_64
, arg1
);
2595 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
2597 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
2598 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
);
2599 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
2601 tcg_gen_muls2_tl(rl
, rh
, arg1
, arg2
);
2604 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2605 } else { /* n is expected to be 1 */
2606 tcg_gen_ext_i32_i64(temp_64
, arg1
);
2607 tcg_gen_ext_i32_i64(temp2_64
, arg2
);
2609 tcg_gen_mul_i64(temp_64
, temp_64
, temp2_64
);
2611 if (up_shift
== 0) {
2612 tcg_gen_shli_i64(temp_64
, temp_64
, 1);
2614 tcg_gen_shri_i64(temp_64
, temp_64
, up_shift
- 1);
2616 tcg_gen_extr_i64_i32(rl
, rh
, temp_64
);
2617 /* overflow only occurs if r1 = r2 = 0x8000 */
2618 if (up_shift
== 0) {/* result is 64 bit */
2619 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rh
,
2621 } else { /* result is 32 bit */
2622 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, rl
,
2625 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2626 /* calc sv overflow bit */
2627 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
2629 /* calc av overflow bit */
2630 if (up_shift
== 0) {
2631 tcg_gen_add_tl(cpu_PSW_AV
, rh
, rh
);
2632 tcg_gen_xor_tl(cpu_PSW_AV
, rh
, cpu_PSW_AV
);
2634 tcg_gen_add_tl(cpu_PSW_AV
, rl
, rl
);
2635 tcg_gen_xor_tl(cpu_PSW_AV
, rl
, cpu_PSW_AV
);
2637 /* calc sav overflow bit */
2638 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2639 tcg_temp_free(temp
);
2640 tcg_temp_free_i64(temp_64
);
2641 tcg_temp_free_i64(temp2_64
);
2645 gen_mul_q_16(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
2647 TCGv temp
= tcg_temp_new();
2649 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2650 } else { /* n is expected to be 1 */
2651 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2652 tcg_gen_shli_tl(ret
, ret
, 1);
2653 /* catch special case r1 = r2 = 0x8000 */
2654 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80000000);
2655 tcg_gen_sub_tl(ret
, ret
, temp
);
2658 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2659 /* calc av overflow bit */
2660 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2661 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2662 /* calc sav overflow bit */
2663 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2665 tcg_temp_free(temp
);
2668 static void gen_mulr_q(TCGv ret
, TCGv arg1
, TCGv arg2
, uint32_t n
)
2670 TCGv temp
= tcg_temp_new();
2672 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2673 tcg_gen_addi_tl(ret
, ret
, 0x8000);
2675 tcg_gen_mul_tl(ret
, arg1
, arg2
);
2676 tcg_gen_shli_tl(ret
, ret
, 1);
2677 tcg_gen_addi_tl(ret
, ret
, 0x8000);
2678 /* catch special case r1 = r2 = 0x8000 */
2679 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, ret
, 0x80008000);
2680 tcg_gen_muli_tl(temp
, temp
, 0x8001);
2681 tcg_gen_sub_tl(ret
, ret
, temp
);
2684 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2685 /* calc av overflow bit */
2686 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2687 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2688 /* calc sav overflow bit */
2689 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2690 /* cut halfword off */
2691 tcg_gen_andi_tl(ret
, ret
, 0xffff0000);
2693 tcg_temp_free(temp
);
2697 gen_madds_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2700 TCGv_i64 temp64
= tcg_temp_new_i64();
2701 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2702 gen_helper_madd64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
2703 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2704 tcg_temp_free_i64(temp64
);
2708 gen_maddsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2711 TCGv temp
= tcg_const_i32(con
);
2712 gen_madds_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2713 tcg_temp_free(temp
);
2717 gen_maddsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2720 TCGv_i64 temp64
= tcg_temp_new_i64();
2721 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2722 gen_helper_madd64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
2723 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2724 tcg_temp_free_i64(temp64
);
2728 gen_maddsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2731 TCGv temp
= tcg_const_i32(con
);
2732 gen_maddsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2733 tcg_temp_free(temp
);
2736 static inline void gen_msubsi_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2738 TCGv temp
= tcg_const_i32(con
);
2739 gen_helper_msub32_ssov(ret
, cpu_env
, r1
, r2
, temp
);
2740 tcg_temp_free(temp
);
2743 static inline void gen_msubsui_32(TCGv ret
, TCGv r1
, TCGv r2
, int32_t con
)
2745 TCGv temp
= tcg_const_i32(con
);
2746 gen_helper_msub32_suov(ret
, cpu_env
, r1
, r2
, temp
);
2747 tcg_temp_free(temp
);
2751 gen_msubs_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2754 TCGv_i64 temp64
= tcg_temp_new_i64();
2755 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2756 gen_helper_msub64_ssov(temp64
, cpu_env
, r1
, temp64
, r3
);
2757 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2758 tcg_temp_free_i64(temp64
);
2762 gen_msubsi_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2765 TCGv temp
= tcg_const_i32(con
);
2766 gen_msubs_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2767 tcg_temp_free(temp
);
2771 gen_msubsu_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2774 TCGv_i64 temp64
= tcg_temp_new_i64();
2775 tcg_gen_concat_i32_i64(temp64
, r2_low
, r2_high
);
2776 gen_helper_msub64_suov(temp64
, cpu_env
, r1
, temp64
, r3
);
2777 tcg_gen_extr_i64_i32(ret_low
, ret_high
, temp64
);
2778 tcg_temp_free_i64(temp64
);
2782 gen_msubsui_64(TCGv ret_low
, TCGv ret_high
, TCGv r1
, TCGv r2_low
, TCGv r2_high
,
2785 TCGv temp
= tcg_const_i32(con
);
2786 gen_msubsu_64(ret_low
, ret_high
, r1
, r2_low
, r2_high
, temp
);
2787 tcg_temp_free(temp
);
2790 static void gen_saturate(TCGv ret
, TCGv arg
, int32_t up
, int32_t low
)
2792 TCGv sat_neg
= tcg_const_i32(low
);
2793 TCGv temp
= tcg_const_i32(up
);
2795 /* sat_neg = (arg < low ) ? low : arg; */
2796 tcg_gen_movcond_tl(TCG_COND_LT
, sat_neg
, arg
, sat_neg
, sat_neg
, arg
);
2798 /* ret = (sat_neg > up ) ? up : sat_neg; */
2799 tcg_gen_movcond_tl(TCG_COND_GT
, ret
, sat_neg
, temp
, temp
, sat_neg
);
2801 tcg_temp_free(sat_neg
);
2802 tcg_temp_free(temp
);
2805 static void gen_saturate_u(TCGv ret
, TCGv arg
, int32_t up
)
2807 TCGv temp
= tcg_const_i32(up
);
2808 /* sat_neg = (arg > up ) ? up : arg; */
2809 tcg_gen_movcond_tl(TCG_COND_GTU
, ret
, arg
, temp
, temp
, arg
);
2810 tcg_temp_free(temp
);
2813 static void gen_shi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2815 if (shift_count
== -32) {
2816 tcg_gen_movi_tl(ret
, 0);
2817 } else if (shift_count
>= 0) {
2818 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2820 tcg_gen_shri_tl(ret
, r1
, -shift_count
);
2824 static void gen_sh_hi(TCGv ret
, TCGv r1
, int32_t shiftcount
)
2826 TCGv temp_low
, temp_high
;
2828 if (shiftcount
== -16) {
2829 tcg_gen_movi_tl(ret
, 0);
2831 temp_high
= tcg_temp_new();
2832 temp_low
= tcg_temp_new();
2834 tcg_gen_andi_tl(temp_low
, r1
, 0xffff);
2835 tcg_gen_andi_tl(temp_high
, r1
, 0xffff0000);
2836 gen_shi(temp_low
, temp_low
, shiftcount
);
2837 gen_shi(ret
, temp_high
, shiftcount
);
2838 tcg_gen_deposit_tl(ret
, ret
, temp_low
, 0, 16);
2840 tcg_temp_free(temp_low
);
2841 tcg_temp_free(temp_high
);
2845 static void gen_shaci(TCGv ret
, TCGv r1
, int32_t shift_count
)
2847 uint32_t msk
, msk_start
;
2848 TCGv temp
= tcg_temp_new();
2849 TCGv temp2
= tcg_temp_new();
2850 TCGv t_0
= tcg_const_i32(0);
2852 if (shift_count
== 0) {
2853 /* Clear PSW.C and PSW.V */
2854 tcg_gen_movi_tl(cpu_PSW_C
, 0);
2855 tcg_gen_mov_tl(cpu_PSW_V
, cpu_PSW_C
);
2856 tcg_gen_mov_tl(ret
, r1
);
2857 } else if (shift_count
== -32) {
2859 tcg_gen_mov_tl(cpu_PSW_C
, r1
);
2860 /* fill ret completely with sign bit */
2861 tcg_gen_sari_tl(ret
, r1
, 31);
2863 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2864 } else if (shift_count
> 0) {
2865 TCGv t_max
= tcg_const_i32(0x7FFFFFFF >> shift_count
);
2866 TCGv t_min
= tcg_const_i32(((int32_t) -0x80000000) >> shift_count
);
2869 msk_start
= 32 - shift_count
;
2870 msk
= ((1 << shift_count
) - 1) << msk_start
;
2871 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2872 /* calc v/sv bits */
2873 tcg_gen_setcond_tl(TCG_COND_GT
, temp
, r1
, t_max
);
2874 tcg_gen_setcond_tl(TCG_COND_LT
, temp2
, r1
, t_min
);
2875 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
2876 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
2878 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_V
, cpu_PSW_SV
);
2880 tcg_gen_shli_tl(ret
, r1
, shift_count
);
2882 tcg_temp_free(t_max
);
2883 tcg_temp_free(t_min
);
2886 tcg_gen_movi_tl(cpu_PSW_V
, 0);
2888 msk
= (1 << -shift_count
) - 1;
2889 tcg_gen_andi_tl(cpu_PSW_C
, r1
, msk
);
2891 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2893 /* calc av overflow bit */
2894 tcg_gen_add_tl(cpu_PSW_AV
, ret
, ret
);
2895 tcg_gen_xor_tl(cpu_PSW_AV
, ret
, cpu_PSW_AV
);
2896 /* calc sav overflow bit */
2897 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
2899 tcg_temp_free(temp
);
2900 tcg_temp_free(temp2
);
2904 static void gen_shas(TCGv ret
, TCGv r1
, TCGv r2
)
2906 gen_helper_sha_ssov(ret
, cpu_env
, r1
, r2
);
2909 static void gen_shasi(TCGv ret
, TCGv r1
, int32_t con
)
2911 TCGv temp
= tcg_const_i32(con
);
2912 gen_shas(ret
, r1
, temp
);
2913 tcg_temp_free(temp
);
2916 static void gen_sha_hi(TCGv ret
, TCGv r1
, int32_t shift_count
)
2920 if (shift_count
== 0) {
2921 tcg_gen_mov_tl(ret
, r1
);
2922 } else if (shift_count
> 0) {
2923 low
= tcg_temp_new();
2924 high
= tcg_temp_new();
2926 tcg_gen_andi_tl(high
, r1
, 0xffff0000);
2927 tcg_gen_shli_tl(low
, r1
, shift_count
);
2928 tcg_gen_shli_tl(ret
, high
, shift_count
);
2929 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2932 tcg_temp_free(high
);
2934 low
= tcg_temp_new();
2935 high
= tcg_temp_new();
2937 tcg_gen_ext16s_tl(low
, r1
);
2938 tcg_gen_sari_tl(low
, low
, -shift_count
);
2939 tcg_gen_sari_tl(ret
, r1
, -shift_count
);
2940 tcg_gen_deposit_tl(ret
, ret
, low
, 0, 16);
2943 tcg_temp_free(high
);
2948 /* ret = {ret[30:0], (r1 cond r2)}; */
2949 static void gen_sh_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
)
2951 TCGv temp
= tcg_temp_new();
2952 TCGv temp2
= tcg_temp_new();
2954 tcg_gen_shli_tl(temp
, ret
, 1);
2955 tcg_gen_setcond_tl(cond
, temp2
, r1
, r2
);
2956 tcg_gen_or_tl(ret
, temp
, temp2
);
2958 tcg_temp_free(temp
);
2959 tcg_temp_free(temp2
);
2962 static void gen_sh_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
)
2964 TCGv temp
= tcg_const_i32(con
);
2965 gen_sh_cond(cond
, ret
, r1
, temp
);
2966 tcg_temp_free(temp
);
2969 static inline void gen_adds(TCGv ret
, TCGv r1
, TCGv r2
)
2971 gen_helper_add_ssov(ret
, cpu_env
, r1
, r2
);
2974 static inline void gen_addsi(TCGv ret
, TCGv r1
, int32_t con
)
2976 TCGv temp
= tcg_const_i32(con
);
2977 gen_helper_add_ssov(ret
, cpu_env
, r1
, temp
);
2978 tcg_temp_free(temp
);
2981 static inline void gen_addsui(TCGv ret
, TCGv r1
, int32_t con
)
2983 TCGv temp
= tcg_const_i32(con
);
2984 gen_helper_add_suov(ret
, cpu_env
, r1
, temp
);
2985 tcg_temp_free(temp
);
2988 static inline void gen_subs(TCGv ret
, TCGv r1
, TCGv r2
)
2990 gen_helper_sub_ssov(ret
, cpu_env
, r1
, r2
);
2993 static inline void gen_subsu(TCGv ret
, TCGv r1
, TCGv r2
)
2995 gen_helper_sub_suov(ret
, cpu_env
, r1
, r2
);
2998 static inline void gen_bit_2op(TCGv ret
, TCGv r1
, TCGv r2
,
3000 void(*op1
)(TCGv
, TCGv
, TCGv
),
3001 void(*op2
)(TCGv
, TCGv
, TCGv
))
3005 temp1
= tcg_temp_new();
3006 temp2
= tcg_temp_new();
3008 tcg_gen_shri_tl(temp2
, r2
, pos2
);
3009 tcg_gen_shri_tl(temp1
, r1
, pos1
);
3011 (*op1
)(temp1
, temp1
, temp2
);
3012 (*op2
)(temp1
, ret
, temp1
);
3014 tcg_gen_deposit_tl(ret
, ret
, temp1
, 0, 1);
3016 tcg_temp_free(temp1
);
3017 tcg_temp_free(temp2
);
3020 /* ret = r1[pos1] op1 r2[pos2]; */
3021 static inline void gen_bit_1op(TCGv ret
, TCGv r1
, TCGv r2
,
3023 void(*op1
)(TCGv
, TCGv
, TCGv
))
3027 temp1
= tcg_temp_new();
3028 temp2
= tcg_temp_new();
3030 tcg_gen_shri_tl(temp2
, r2
, pos2
);
3031 tcg_gen_shri_tl(temp1
, r1
, pos1
);
3033 (*op1
)(ret
, temp1
, temp2
);
3035 tcg_gen_andi_tl(ret
, ret
, 0x1);
3037 tcg_temp_free(temp1
);
3038 tcg_temp_free(temp2
);
3041 static inline void gen_accumulating_cond(int cond
, TCGv ret
, TCGv r1
, TCGv r2
,
3042 void(*op
)(TCGv
, TCGv
, TCGv
))
3044 TCGv temp
= tcg_temp_new();
3045 TCGv temp2
= tcg_temp_new();
3046 /* temp = (arg1 cond arg2 )*/
3047 tcg_gen_setcond_tl(cond
, temp
, r1
, r2
);
3049 tcg_gen_andi_tl(temp2
, ret
, 0x1);
3050 /* temp = temp insn temp2 */
3051 (*op
)(temp
, temp
, temp2
);
3052 /* ret = {ret[31:1], temp} */
3053 tcg_gen_deposit_tl(ret
, ret
, temp
, 0, 1);
3055 tcg_temp_free(temp
);
3056 tcg_temp_free(temp2
);
3060 gen_accumulating_condi(int cond
, TCGv ret
, TCGv r1
, int32_t con
,
3061 void(*op
)(TCGv
, TCGv
, TCGv
))
3063 TCGv temp
= tcg_const_i32(con
);
3064 gen_accumulating_cond(cond
, ret
, r1
, temp
, op
);
3065 tcg_temp_free(temp
);
3068 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3069 static inline void gen_cond_w(TCGCond cond
, TCGv ret
, TCGv r1
, TCGv r2
)
3071 tcg_gen_setcond_tl(cond
, ret
, r1
, r2
);
3072 tcg_gen_neg_tl(ret
, ret
);
3075 static inline void gen_eqany_bi(TCGv ret
, TCGv r1
, int32_t con
)
3077 TCGv b0
= tcg_temp_new();
3078 TCGv b1
= tcg_temp_new();
3079 TCGv b2
= tcg_temp_new();
3080 TCGv b3
= tcg_temp_new();
3083 tcg_gen_andi_tl(b0
, r1
, 0xff);
3084 tcg_gen_setcondi_tl(TCG_COND_EQ
, b0
, b0
, con
& 0xff);
3087 tcg_gen_andi_tl(b1
, r1
, 0xff00);
3088 tcg_gen_setcondi_tl(TCG_COND_EQ
, b1
, b1
, con
& 0xff00);
3091 tcg_gen_andi_tl(b2
, r1
, 0xff0000);
3092 tcg_gen_setcondi_tl(TCG_COND_EQ
, b2
, b2
, con
& 0xff0000);
3095 tcg_gen_andi_tl(b3
, r1
, 0xff000000);
3096 tcg_gen_setcondi_tl(TCG_COND_EQ
, b3
, b3
, con
& 0xff000000);
3099 tcg_gen_or_tl(ret
, b0
, b1
);
3100 tcg_gen_or_tl(ret
, ret
, b2
);
3101 tcg_gen_or_tl(ret
, ret
, b3
);
3109 static inline void gen_eqany_hi(TCGv ret
, TCGv r1
, int32_t con
)
3111 TCGv h0
= tcg_temp_new();
3112 TCGv h1
= tcg_temp_new();
3115 tcg_gen_andi_tl(h0
, r1
, 0xffff);
3116 tcg_gen_setcondi_tl(TCG_COND_EQ
, h0
, h0
, con
& 0xffff);
3119 tcg_gen_andi_tl(h1
, r1
, 0xffff0000);
3120 tcg_gen_setcondi_tl(TCG_COND_EQ
, h1
, h1
, con
& 0xffff0000);
3123 tcg_gen_or_tl(ret
, h0
, h1
);
3128 /* mask = ((1 << width) -1) << pos;
3129 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3130 static inline void gen_insert(TCGv ret
, TCGv r1
, TCGv r2
, TCGv width
, TCGv pos
)
3132 TCGv mask
= tcg_temp_new();
3133 TCGv temp
= tcg_temp_new();
3134 TCGv temp2
= tcg_temp_new();
3136 tcg_gen_movi_tl(mask
, 1);
3137 tcg_gen_shl_tl(mask
, mask
, width
);
3138 tcg_gen_subi_tl(mask
, mask
, 1);
3139 tcg_gen_shl_tl(mask
, mask
, pos
);
3141 tcg_gen_shl_tl(temp
, r2
, pos
);
3142 tcg_gen_and_tl(temp
, temp
, mask
);
3143 tcg_gen_andc_tl(temp2
, r1
, mask
);
3144 tcg_gen_or_tl(ret
, temp
, temp2
);
3146 tcg_temp_free(mask
);
3147 tcg_temp_free(temp
);
3148 tcg_temp_free(temp2
);
3151 static inline void gen_bsplit(TCGv rl
, TCGv rh
, TCGv r1
)
3153 TCGv_i64 temp
= tcg_temp_new_i64();
3155 gen_helper_bsplit(temp
, r1
);
3156 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
3158 tcg_temp_free_i64(temp
);
3161 static inline void gen_unpack(TCGv rl
, TCGv rh
, TCGv r1
)
3163 TCGv_i64 temp
= tcg_temp_new_i64();
3165 gen_helper_unpack(temp
, r1
);
3166 tcg_gen_extr_i64_i32(rl
, rh
, temp
);
3168 tcg_temp_free_i64(temp
);
3172 gen_dvinit_b(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
3174 TCGv_i64 ret
= tcg_temp_new_i64();
3176 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
3177 gen_helper_dvinit_b_13(ret
, cpu_env
, r1
, r2
);
3179 gen_helper_dvinit_b_131(ret
, cpu_env
, r1
, r2
);
3181 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
3183 tcg_temp_free_i64(ret
);
3187 gen_dvinit_h(CPUTriCoreState
*env
, TCGv rl
, TCGv rh
, TCGv r1
, TCGv r2
)
3189 TCGv_i64 ret
= tcg_temp_new_i64();
3191 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
3192 gen_helper_dvinit_h_13(ret
, cpu_env
, r1
, r2
);
3194 gen_helper_dvinit_h_131(ret
, cpu_env
, r1
, r2
);
3196 tcg_gen_extr_i64_i32(rl
, rh
, ret
);
3198 tcg_temp_free_i64(ret
);
3201 static void gen_calc_usb_mul_h(TCGv arg_low
, TCGv arg_high
)
3203 TCGv temp
= tcg_temp_new();
3205 tcg_gen_add_tl(temp
, arg_low
, arg_low
);
3206 tcg_gen_xor_tl(temp
, temp
, arg_low
);
3207 tcg_gen_add_tl(cpu_PSW_AV
, arg_high
, arg_high
);
3208 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_PSW_AV
, arg_high
);
3209 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
3211 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3212 tcg_gen_movi_tl(cpu_PSW_V
, 0);
3213 tcg_temp_free(temp
);
3216 static void gen_calc_usb_mulr_h(TCGv arg
)
3218 TCGv temp
= tcg_temp_new();
3220 tcg_gen_add_tl(temp
, arg
, arg
);
3221 tcg_gen_xor_tl(temp
, temp
, arg
);
3222 tcg_gen_shli_tl(cpu_PSW_AV
, temp
, 16);
3223 tcg_gen_or_tl(cpu_PSW_AV
, cpu_PSW_AV
, temp
);
3225 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3227 tcg_gen_movi_tl(cpu_PSW_V
, 0);
3228 tcg_temp_free(temp
);
3231 /* helpers for generating program flow micro-ops */
3233 static inline void gen_save_pc(target_ulong pc
)
3235 tcg_gen_movi_tl(cpu_PC
, pc
);
3238 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3240 if (unlikely(ctx
->singlestep_enabled
)) {
3244 #ifndef CONFIG_USER_ONLY
3245 return (ctx
->tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3251 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3253 if (use_goto_tb(ctx
, dest
)) {
3256 tcg_gen_exit_tb((uintptr_t)ctx
->tb
+ n
);
3259 if (ctx
->singlestep_enabled
) {
3260 /* raise exception debug */
3266 static void generate_trap(DisasContext
*ctx
, int class, int tin
)
3268 TCGv_i32 classtemp
= tcg_const_i32(class);
3269 TCGv_i32 tintemp
= tcg_const_i32(tin
);
3271 gen_save_pc(ctx
->pc
);
3272 gen_helper_raise_exception_sync(cpu_env
, classtemp
, tintemp
);
3273 ctx
->bstate
= BS_EXCP
;
3275 tcg_temp_free(classtemp
);
3276 tcg_temp_free(tintemp
);
3279 static inline void gen_branch_cond(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
3280 TCGv r2
, int16_t address
)
3282 TCGLabel
*jumpLabel
= gen_new_label();
3283 tcg_gen_brcond_tl(cond
, r1
, r2
, jumpLabel
);
3285 gen_goto_tb(ctx
, 1, ctx
->next_pc
);
3287 gen_set_label(jumpLabel
);
3288 gen_goto_tb(ctx
, 0, ctx
->pc
+ address
* 2);
3291 static inline void gen_branch_condi(DisasContext
*ctx
, TCGCond cond
, TCGv r1
,
3292 int r2
, int16_t address
)
3294 TCGv temp
= tcg_const_i32(r2
);
3295 gen_branch_cond(ctx
, cond
, r1
, temp
, address
);
3296 tcg_temp_free(temp
);
3299 static void gen_loop(DisasContext
*ctx
, int r1
, int32_t offset
)
3301 TCGLabel
*l1
= gen_new_label();
3303 tcg_gen_subi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], 1);
3304 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr_a
[r1
], -1, l1
);
3305 gen_goto_tb(ctx
, 1, ctx
->pc
+ offset
);
3307 gen_goto_tb(ctx
, 0, ctx
->next_pc
);
3310 static void gen_fcall_save_ctx(DisasContext
*ctx
)
3312 TCGv temp
= tcg_temp_new();
3314 tcg_gen_addi_tl(temp
, cpu_gpr_a
[10], -4);
3315 tcg_gen_qemu_st_tl(cpu_gpr_a
[11], temp
, ctx
->mem_idx
, MO_LESL
);
3316 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3317 tcg_gen_mov_tl(cpu_gpr_a
[10], temp
);
3319 tcg_temp_free(temp
);
3322 static void gen_fret(DisasContext
*ctx
)
3324 TCGv temp
= tcg_temp_new();
3326 tcg_gen_andi_tl(temp
, cpu_gpr_a
[11], ~0x1);
3327 tcg_gen_qemu_ld_tl(cpu_gpr_a
[11], cpu_gpr_a
[10], ctx
->mem_idx
, MO_LESL
);
3328 tcg_gen_addi_tl(cpu_gpr_a
[10], cpu_gpr_a
[10], 4);
3329 tcg_gen_mov_tl(cpu_PC
, temp
);
3331 ctx
->bstate
= BS_BRANCH
;
3333 tcg_temp_free(temp
);
3336 static void gen_compute_branch(DisasContext
*ctx
, uint32_t opc
, int r1
,
3337 int r2
, int32_t constant
, int32_t offset
)
3343 /* SB-format jumps */
3346 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3348 case OPC1_32_B_CALL
:
3349 case OPC1_16_SB_CALL
:
3350 gen_helper_1arg(call
, ctx
->next_pc
);
3351 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3354 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], 0, offset
);
3356 case OPC1_16_SB_JNZ
:
3357 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], 0, offset
);
3359 /* SBC-format jumps */
3360 case OPC1_16_SBC_JEQ
:
3361 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], constant
, offset
);
3363 case OPC1_16_SBC_JEQ2
:
3364 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[15], constant
,
3367 case OPC1_16_SBC_JNE
:
3368 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15], constant
, offset
);
3370 case OPC1_16_SBC_JNE2
:
3371 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[15],
3372 constant
, offset
+ 16);
3374 /* SBRN-format jumps */
3375 case OPC1_16_SBRN_JZ_T
:
3376 temp
= tcg_temp_new();
3377 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
3378 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
3379 tcg_temp_free(temp
);
3381 case OPC1_16_SBRN_JNZ_T
:
3382 temp
= tcg_temp_new();
3383 tcg_gen_andi_tl(temp
, cpu_gpr_d
[15], 0x1u
<< constant
);
3384 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
3385 tcg_temp_free(temp
);
3387 /* SBR-format jumps */
3388 case OPC1_16_SBR_JEQ
:
3389 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
3392 case OPC1_16_SBR_JNE
:
3393 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15],
3396 case OPC1_16_SBR_JNZ
:
3397 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], 0, offset
);
3399 case OPC1_16_SBR_JNZ_A
:
3400 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
3402 case OPC1_16_SBR_JGEZ
:
3403 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], 0, offset
);
3405 case OPC1_16_SBR_JGTZ
:
3406 gen_branch_condi(ctx
, TCG_COND_GT
, cpu_gpr_d
[r1
], 0, offset
);
3408 case OPC1_16_SBR_JLEZ
:
3409 gen_branch_condi(ctx
, TCG_COND_LE
, cpu_gpr_d
[r1
], 0, offset
);
3411 case OPC1_16_SBR_JLTZ
:
3412 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], 0, offset
);
3414 case OPC1_16_SBR_JZ
:
3415 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], 0, offset
);
3417 case OPC1_16_SBR_JZ_A
:
3418 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
3420 case OPC1_16_SBR_LOOP
:
3421 gen_loop(ctx
, r1
, offset
* 2 - 32);
3423 /* SR-format jumps */
3425 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], 0xfffffffe);
3428 case OPC2_32_SYS_RET
:
3429 case OPC2_16_SR_RET
:
3430 gen_helper_ret(cpu_env
);
3434 case OPC1_32_B_CALLA
:
3435 gen_helper_1arg(call
, ctx
->next_pc
);
3436 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3438 case OPC1_32_B_FCALL
:
3439 gen_fcall_save_ctx(ctx
);
3440 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3442 case OPC1_32_B_FCALLA
:
3443 gen_fcall_save_ctx(ctx
);
3444 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3447 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3450 gen_goto_tb(ctx
, 0, EA_B_ABSOLUT(offset
));
3453 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
3454 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3457 case OPCM_32_BRC_EQ_NEQ
:
3458 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JEQ
) {
3459 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], constant
, offset
);
3461 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], constant
, offset
);
3464 case OPCM_32_BRC_GE
:
3465 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OP2_32_BRC_JGE
) {
3466 gen_branch_condi(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], constant
, offset
);
3468 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
3469 gen_branch_condi(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], constant
,
3473 case OPCM_32_BRC_JLT
:
3474 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JLT
) {
3475 gen_branch_condi(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], constant
, offset
);
3477 constant
= MASK_OP_BRC_CONST4(ctx
->opcode
);
3478 gen_branch_condi(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], constant
,
3482 case OPCM_32_BRC_JNE
:
3483 temp
= tcg_temp_new();
3484 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRC_JNED
) {
3485 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3486 /* subi is unconditional */
3487 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3488 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
3490 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3491 /* addi is unconditional */
3492 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3493 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, constant
, offset
);
3495 tcg_temp_free(temp
);
3498 case OPCM_32_BRN_JTT
:
3499 n
= MASK_OP_BRN_N(ctx
->opcode
);
3501 temp
= tcg_temp_new();
3502 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r1
], (1 << n
));
3504 if (MASK_OP_BRN_OP2(ctx
->opcode
) == OPC2_32_BRN_JNZ_T
) {
3505 gen_branch_condi(ctx
, TCG_COND_NE
, temp
, 0, offset
);
3507 gen_branch_condi(ctx
, TCG_COND_EQ
, temp
, 0, offset
);
3509 tcg_temp_free(temp
);
3512 case OPCM_32_BRR_EQ_NEQ
:
3513 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ
) {
3514 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3517 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3521 case OPCM_32_BRR_ADDR_EQ_NEQ
:
3522 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JEQ_A
) {
3523 gen_branch_cond(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
3526 gen_branch_cond(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
3530 case OPCM_32_BRR_GE
:
3531 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JGE
) {
3532 gen_branch_cond(ctx
, TCG_COND_GE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3535 gen_branch_cond(ctx
, TCG_COND_GEU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3539 case OPCM_32_BRR_JLT
:
3540 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JLT
) {
3541 gen_branch_cond(ctx
, TCG_COND_LT
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3544 gen_branch_cond(ctx
, TCG_COND_LTU
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
3548 case OPCM_32_BRR_LOOP
:
3549 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_LOOP
) {
3550 gen_loop(ctx
, r2
, offset
* 2);
3552 /* OPC2_32_BRR_LOOPU */
3553 gen_goto_tb(ctx
, 0, ctx
->pc
+ offset
* 2);
3556 case OPCM_32_BRR_JNE
:
3557 temp
= tcg_temp_new();
3558 temp2
= tcg_temp_new();
3559 if (MASK_OP_BRC_OP2(ctx
->opcode
) == OPC2_32_BRR_JNED
) {
3560 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3561 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3562 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
3563 /* subi is unconditional */
3564 tcg_gen_subi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3565 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
3567 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
3568 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3569 tcg_gen_mov_tl(temp2
, cpu_gpr_d
[r2
]);
3570 /* addi is unconditional */
3571 tcg_gen_addi_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 1);
3572 gen_branch_cond(ctx
, TCG_COND_NE
, temp
, temp2
, offset
);
3574 tcg_temp_free(temp
);
3575 tcg_temp_free(temp2
);
3577 case OPCM_32_BRR_JNZ
:
3578 if (MASK_OP_BRR_OP2(ctx
->opcode
) == OPC2_32_BRR_JNZ_A
) {
3579 gen_branch_condi(ctx
, TCG_COND_NE
, cpu_gpr_a
[r1
], 0, offset
);
3581 gen_branch_condi(ctx
, TCG_COND_EQ
, cpu_gpr_a
[r1
], 0, offset
);
3585 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3587 ctx
->bstate
= BS_BRANCH
;
3592 * Functions for decoding instructions
3595 static void decode_src_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int op1
)
3601 r1
= MASK_OP_SRC_S1D(ctx
->opcode
);
3602 const4
= MASK_OP_SRC_CONST4_SEXT(ctx
->opcode
);
3605 case OPC1_16_SRC_ADD
:
3606 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3608 case OPC1_16_SRC_ADD_A15
:
3609 gen_addi_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], const4
);
3611 case OPC1_16_SRC_ADD_15A
:
3612 gen_addi_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], const4
);
3614 case OPC1_16_SRC_ADD_A
:
3615 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], const4
);
3617 case OPC1_16_SRC_CADD
:
3618 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
3621 case OPC1_16_SRC_CADDN
:
3622 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const4
, cpu_gpr_d
[r1
],
3625 case OPC1_16_SRC_CMOV
:
3626 temp
= tcg_const_tl(0);
3627 temp2
= tcg_const_tl(const4
);
3628 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3629 temp2
, cpu_gpr_d
[r1
]);
3630 tcg_temp_free(temp
);
3631 tcg_temp_free(temp2
);
3633 case OPC1_16_SRC_CMOVN
:
3634 temp
= tcg_const_tl(0);
3635 temp2
= tcg_const_tl(const4
);
3636 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3637 temp2
, cpu_gpr_d
[r1
]);
3638 tcg_temp_free(temp
);
3639 tcg_temp_free(temp2
);
3641 case OPC1_16_SRC_EQ
:
3642 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3645 case OPC1_16_SRC_LT
:
3646 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3649 case OPC1_16_SRC_MOV
:
3650 tcg_gen_movi_tl(cpu_gpr_d
[r1
], const4
);
3652 case OPC1_16_SRC_MOV_A
:
3653 const4
= MASK_OP_SRC_CONST4(ctx
->opcode
);
3654 tcg_gen_movi_tl(cpu_gpr_a
[r1
], const4
);
3656 case OPC1_16_SRC_MOV_E
:
3657 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
3658 tcg_gen_movi_tl(cpu_gpr_d
[r1
], const4
);
3659 tcg_gen_sari_tl(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], 31);
3661 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3664 case OPC1_16_SRC_SH
:
3665 gen_shi(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3667 case OPC1_16_SRC_SHA
:
3668 gen_shaci(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], const4
);
3671 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3675 static void decode_srr_opc(DisasContext
*ctx
, int op1
)
3680 r1
= MASK_OP_SRR_S1D(ctx
->opcode
);
3681 r2
= MASK_OP_SRR_S2(ctx
->opcode
);
3684 case OPC1_16_SRR_ADD
:
3685 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3687 case OPC1_16_SRR_ADD_A15
:
3688 gen_add_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
3690 case OPC1_16_SRR_ADD_15A
:
3691 gen_add_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3693 case OPC1_16_SRR_ADD_A
:
3694 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
3696 case OPC1_16_SRR_ADDS
:
3697 gen_adds(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3699 case OPC1_16_SRR_AND
:
3700 tcg_gen_and_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3702 case OPC1_16_SRR_CMOV
:
3703 temp
= tcg_const_tl(0);
3704 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3705 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
3706 tcg_temp_free(temp
);
3708 case OPC1_16_SRR_CMOVN
:
3709 temp
= tcg_const_tl(0);
3710 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[15], temp
,
3711 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
]);
3712 tcg_temp_free(temp
);
3714 case OPC1_16_SRR_EQ
:
3715 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3718 case OPC1_16_SRR_LT
:
3719 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[15], cpu_gpr_d
[r1
],
3722 case OPC1_16_SRR_MOV
:
3723 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3725 case OPC1_16_SRR_MOV_A
:
3726 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_d
[r2
]);
3728 case OPC1_16_SRR_MOV_AA
:
3729 tcg_gen_mov_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
3731 case OPC1_16_SRR_MOV_D
:
3732 tcg_gen_mov_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
]);
3734 case OPC1_16_SRR_MUL
:
3735 gen_mul_i32s(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3737 case OPC1_16_SRR_OR
:
3738 tcg_gen_or_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3740 case OPC1_16_SRR_SUB
:
3741 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3743 case OPC1_16_SRR_SUB_A15B
:
3744 gen_sub_d(cpu_gpr_d
[r1
], cpu_gpr_d
[15], cpu_gpr_d
[r2
]);
3746 case OPC1_16_SRR_SUB_15AB
:
3747 gen_sub_d(cpu_gpr_d
[15], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3749 case OPC1_16_SRR_SUBS
:
3750 gen_subs(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3752 case OPC1_16_SRR_XOR
:
3753 tcg_gen_xor_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
3756 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3760 static void decode_ssr_opc(DisasContext
*ctx
, int op1
)
3764 r1
= MASK_OP_SSR_S1(ctx
->opcode
);
3765 r2
= MASK_OP_SSR_S2(ctx
->opcode
);
3768 case OPC1_16_SSR_ST_A
:
3769 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3771 case OPC1_16_SSR_ST_A_POSTINC
:
3772 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3773 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3775 case OPC1_16_SSR_ST_B
:
3776 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3778 case OPC1_16_SSR_ST_B_POSTINC
:
3779 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3780 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
3782 case OPC1_16_SSR_ST_H
:
3783 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
3785 case OPC1_16_SSR_ST_H_POSTINC
:
3786 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUW
);
3787 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
3789 case OPC1_16_SSR_ST_W
:
3790 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3792 case OPC1_16_SSR_ST_W_POSTINC
:
3793 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LEUL
);
3794 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3797 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3801 static void decode_sc_opc(DisasContext
*ctx
, int op1
)
3805 const16
= MASK_OP_SC_CONST8(ctx
->opcode
);
3808 case OPC1_16_SC_AND
:
3809 tcg_gen_andi_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
3811 case OPC1_16_SC_BISR
:
3812 gen_helper_1arg(bisr
, const16
& 0xff);
3814 case OPC1_16_SC_LD_A
:
3815 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3817 case OPC1_16_SC_LD_W
:
3818 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3820 case OPC1_16_SC_MOV
:
3821 tcg_gen_movi_tl(cpu_gpr_d
[15], const16
);
3824 tcg_gen_ori_tl(cpu_gpr_d
[15], cpu_gpr_d
[15], const16
);
3826 case OPC1_16_SC_ST_A
:
3827 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3829 case OPC1_16_SC_ST_W
:
3830 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[10], const16
* 4, MO_LESL
);
3832 case OPC1_16_SC_SUB_A
:
3833 tcg_gen_subi_tl(cpu_gpr_a
[10], cpu_gpr_a
[10], const16
);
3836 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3840 static void decode_slr_opc(DisasContext
*ctx
, int op1
)
3844 r1
= MASK_OP_SLR_D(ctx
->opcode
);
3845 r2
= MASK_OP_SLR_S2(ctx
->opcode
);
3849 case OPC1_16_SLR_LD_A
:
3850 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3852 case OPC1_16_SLR_LD_A_POSTINC
:
3853 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3854 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3856 case OPC1_16_SLR_LD_BU
:
3857 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3859 case OPC1_16_SLR_LD_BU_POSTINC
:
3860 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_UB
);
3861 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 1);
3863 case OPC1_16_SLR_LD_H
:
3864 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3866 case OPC1_16_SLR_LD_H_POSTINC
:
3867 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESW
);
3868 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 2);
3870 case OPC1_16_SLR_LD_W
:
3871 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3873 case OPC1_16_SLR_LD_W_POSTINC
:
3874 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
, MO_LESL
);
3875 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], 4);
3878 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3882 static void decode_sro_opc(DisasContext
*ctx
, int op1
)
3887 r2
= MASK_OP_SRO_S2(ctx
->opcode
);
3888 address
= MASK_OP_SRO_OFF4(ctx
->opcode
);
3892 case OPC1_16_SRO_LD_A
:
3893 gen_offset_ld(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3895 case OPC1_16_SRO_LD_BU
:
3896 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3898 case OPC1_16_SRO_LD_H
:
3899 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_LESW
);
3901 case OPC1_16_SRO_LD_W
:
3902 gen_offset_ld(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3904 case OPC1_16_SRO_ST_A
:
3905 gen_offset_st(ctx
, cpu_gpr_a
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3907 case OPC1_16_SRO_ST_B
:
3908 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
, MO_UB
);
3910 case OPC1_16_SRO_ST_H
:
3911 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 2, MO_LESW
);
3913 case OPC1_16_SRO_ST_W
:
3914 gen_offset_st(ctx
, cpu_gpr_d
[15], cpu_gpr_a
[r2
], address
* 4, MO_LESL
);
3917 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3921 static void decode_sr_system(CPUTriCoreState
*env
, DisasContext
*ctx
)
3924 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3927 case OPC2_16_SR_NOP
:
3929 case OPC2_16_SR_RET
:
3930 gen_compute_branch(ctx
, op2
, 0, 0, 0, 0);
3932 case OPC2_16_SR_RFE
:
3933 gen_helper_rfe(cpu_env
);
3935 ctx
->bstate
= BS_BRANCH
;
3937 case OPC2_16_SR_DEBUG
:
3938 /* raise EXCP_DEBUG */
3940 case OPC2_16_SR_FRET
:
3944 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3948 static void decode_sr_accu(CPUTriCoreState
*env
, DisasContext
*ctx
)
3954 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
3955 op2
= MASK_OP_SR_OP2(ctx
->opcode
);
3958 case OPC2_16_SR_RSUB
:
3959 /* overflow only if r1 = -0x80000000 */
3960 temp
= tcg_const_i32(-0x80000000);
3962 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r1
], temp
);
3963 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
3965 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
3967 tcg_gen_neg_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3969 tcg_gen_add_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
3970 tcg_gen_xor_tl(cpu_PSW_AV
, cpu_gpr_d
[r1
], cpu_PSW_AV
);
3972 tcg_gen_or_tl(cpu_PSW_SAV
, cpu_PSW_SAV
, cpu_PSW_AV
);
3973 tcg_temp_free(temp
);
3975 case OPC2_16_SR_SAT_B
:
3976 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7f, -0x80);
3978 case OPC2_16_SR_SAT_BU
:
3979 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xff);
3981 case OPC2_16_SR_SAT_H
:
3982 gen_saturate(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
3984 case OPC2_16_SR_SAT_HU
:
3985 gen_saturate_u(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 0xffff);
3988 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
3992 static void decode_16Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
4000 op1
= MASK_OP_MAJOR(ctx
->opcode
);
4002 /* handle ADDSC.A opcode only being 6 bit long */
4003 if (unlikely((op1
& 0x3f) == OPC1_16_SRRS_ADDSC_A
)) {
4004 op1
= OPC1_16_SRRS_ADDSC_A
;
4008 case OPC1_16_SRC_ADD
:
4009 case OPC1_16_SRC_ADD_A15
:
4010 case OPC1_16_SRC_ADD_15A
:
4011 case OPC1_16_SRC_ADD_A
:
4012 case OPC1_16_SRC_CADD
:
4013 case OPC1_16_SRC_CADDN
:
4014 case OPC1_16_SRC_CMOV
:
4015 case OPC1_16_SRC_CMOVN
:
4016 case OPC1_16_SRC_EQ
:
4017 case OPC1_16_SRC_LT
:
4018 case OPC1_16_SRC_MOV
:
4019 case OPC1_16_SRC_MOV_A
:
4020 case OPC1_16_SRC_MOV_E
:
4021 case OPC1_16_SRC_SH
:
4022 case OPC1_16_SRC_SHA
:
4023 decode_src_opc(env
, ctx
, op1
);
4026 case OPC1_16_SRR_ADD
:
4027 case OPC1_16_SRR_ADD_A15
:
4028 case OPC1_16_SRR_ADD_15A
:
4029 case OPC1_16_SRR_ADD_A
:
4030 case OPC1_16_SRR_ADDS
:
4031 case OPC1_16_SRR_AND
:
4032 case OPC1_16_SRR_CMOV
:
4033 case OPC1_16_SRR_CMOVN
:
4034 case OPC1_16_SRR_EQ
:
4035 case OPC1_16_SRR_LT
:
4036 case OPC1_16_SRR_MOV
:
4037 case OPC1_16_SRR_MOV_A
:
4038 case OPC1_16_SRR_MOV_AA
:
4039 case OPC1_16_SRR_MOV_D
:
4040 case OPC1_16_SRR_MUL
:
4041 case OPC1_16_SRR_OR
:
4042 case OPC1_16_SRR_SUB
:
4043 case OPC1_16_SRR_SUB_A15B
:
4044 case OPC1_16_SRR_SUB_15AB
:
4045 case OPC1_16_SRR_SUBS
:
4046 case OPC1_16_SRR_XOR
:
4047 decode_srr_opc(ctx
, op1
);
4050 case OPC1_16_SSR_ST_A
:
4051 case OPC1_16_SSR_ST_A_POSTINC
:
4052 case OPC1_16_SSR_ST_B
:
4053 case OPC1_16_SSR_ST_B_POSTINC
:
4054 case OPC1_16_SSR_ST_H
:
4055 case OPC1_16_SSR_ST_H_POSTINC
:
4056 case OPC1_16_SSR_ST_W
:
4057 case OPC1_16_SSR_ST_W_POSTINC
:
4058 decode_ssr_opc(ctx
, op1
);
4061 case OPC1_16_SRRS_ADDSC_A
:
4062 r2
= MASK_OP_SRRS_S2(ctx
->opcode
);
4063 r1
= MASK_OP_SRRS_S1D(ctx
->opcode
);
4064 const16
= MASK_OP_SRRS_N(ctx
->opcode
);
4065 temp
= tcg_temp_new();
4066 tcg_gen_shli_tl(temp
, cpu_gpr_d
[15], const16
);
4067 tcg_gen_add_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], temp
);
4068 tcg_temp_free(temp
);
4071 case OPC1_16_SLRO_LD_A
:
4072 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4073 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4074 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4076 case OPC1_16_SLRO_LD_BU
:
4077 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4078 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4079 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
4081 case OPC1_16_SLRO_LD_H
:
4082 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4083 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4084 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
4086 case OPC1_16_SLRO_LD_W
:
4087 r1
= MASK_OP_SLRO_D(ctx
->opcode
);
4088 const16
= MASK_OP_SLRO_OFF4(ctx
->opcode
);
4089 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4092 case OPC1_16_SB_CALL
:
4094 case OPC1_16_SB_JNZ
:
4096 address
= MASK_OP_SB_DISP8_SEXT(ctx
->opcode
);
4097 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
4100 case OPC1_16_SBC_JEQ
:
4101 case OPC1_16_SBC_JNE
:
4102 address
= MASK_OP_SBC_DISP4(ctx
->opcode
);
4103 const16
= MASK_OP_SBC_CONST4_SEXT(ctx
->opcode
);
4104 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4106 case OPC1_16_SBC_JEQ2
:
4107 case OPC1_16_SBC_JNE2
:
4108 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
4109 address
= MASK_OP_SBC_DISP4(ctx
->opcode
);
4110 const16
= MASK_OP_SBC_CONST4_SEXT(ctx
->opcode
);
4111 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4113 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4117 case OPC1_16_SBRN_JNZ_T
:
4118 case OPC1_16_SBRN_JZ_T
:
4119 address
= MASK_OP_SBRN_DISP4(ctx
->opcode
);
4120 const16
= MASK_OP_SBRN_N(ctx
->opcode
);
4121 gen_compute_branch(ctx
, op1
, 0, 0, const16
, address
);
4124 case OPC1_16_SBR_JEQ
:
4125 case OPC1_16_SBR_JGEZ
:
4126 case OPC1_16_SBR_JGTZ
:
4127 case OPC1_16_SBR_JLEZ
:
4128 case OPC1_16_SBR_JLTZ
:
4129 case OPC1_16_SBR_JNE
:
4130 case OPC1_16_SBR_JNZ
:
4131 case OPC1_16_SBR_JNZ_A
:
4132 case OPC1_16_SBR_JZ
:
4133 case OPC1_16_SBR_JZ_A
:
4134 case OPC1_16_SBR_LOOP
:
4135 r1
= MASK_OP_SBR_S2(ctx
->opcode
);
4136 address
= MASK_OP_SBR_DISP4(ctx
->opcode
);
4137 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
4140 case OPC1_16_SC_AND
:
4141 case OPC1_16_SC_BISR
:
4142 case OPC1_16_SC_LD_A
:
4143 case OPC1_16_SC_LD_W
:
4144 case OPC1_16_SC_MOV
:
4146 case OPC1_16_SC_ST_A
:
4147 case OPC1_16_SC_ST_W
:
4148 case OPC1_16_SC_SUB_A
:
4149 decode_sc_opc(ctx
, op1
);
4152 case OPC1_16_SLR_LD_A
:
4153 case OPC1_16_SLR_LD_A_POSTINC
:
4154 case OPC1_16_SLR_LD_BU
:
4155 case OPC1_16_SLR_LD_BU_POSTINC
:
4156 case OPC1_16_SLR_LD_H
:
4157 case OPC1_16_SLR_LD_H_POSTINC
:
4158 case OPC1_16_SLR_LD_W
:
4159 case OPC1_16_SLR_LD_W_POSTINC
:
4160 decode_slr_opc(ctx
, op1
);
4163 case OPC1_16_SRO_LD_A
:
4164 case OPC1_16_SRO_LD_BU
:
4165 case OPC1_16_SRO_LD_H
:
4166 case OPC1_16_SRO_LD_W
:
4167 case OPC1_16_SRO_ST_A
:
4168 case OPC1_16_SRO_ST_B
:
4169 case OPC1_16_SRO_ST_H
:
4170 case OPC1_16_SRO_ST_W
:
4171 decode_sro_opc(ctx
, op1
);
4174 case OPC1_16_SSRO_ST_A
:
4175 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4176 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4177 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4179 case OPC1_16_SSRO_ST_B
:
4180 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4181 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4182 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
, MO_UB
);
4184 case OPC1_16_SSRO_ST_H
:
4185 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4186 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4187 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 2, MO_LESW
);
4189 case OPC1_16_SSRO_ST_W
:
4190 r1
= MASK_OP_SSRO_S1(ctx
->opcode
);
4191 const16
= MASK_OP_SSRO_OFF4(ctx
->opcode
);
4192 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[15], const16
* 4, MO_LESL
);
4195 case OPCM_16_SR_SYSTEM
:
4196 decode_sr_system(env
, ctx
);
4198 case OPCM_16_SR_ACCU
:
4199 decode_sr_accu(env
, ctx
);
4202 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
4203 gen_compute_branch(ctx
, op1
, r1
, 0, 0, 0);
4205 case OPC1_16_SR_NOT
:
4206 r1
= MASK_OP_SR_S1D(ctx
->opcode
);
4207 tcg_gen_not_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
]);
4210 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4215 * 32 bit instructions
4219 static void decode_abs_ldw(CPUTriCoreState
*env
, DisasContext
*ctx
)
4226 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4227 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4228 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4230 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4233 case OPC2_32_ABS_LD_A
:
4234 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4236 case OPC2_32_ABS_LD_D
:
4238 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4240 case OPC2_32_ABS_LD_DA
:
4242 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4244 case OPC2_32_ABS_LD_W
:
4245 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4248 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4251 tcg_temp_free(temp
);
4254 static void decode_abs_ldb(CPUTriCoreState
*env
, DisasContext
*ctx
)
4261 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4262 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4263 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4265 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4268 case OPC2_32_ABS_LD_B
:
4269 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_SB
);
4271 case OPC2_32_ABS_LD_BU
:
4272 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
4274 case OPC2_32_ABS_LD_H
:
4275 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESW
);
4277 case OPC2_32_ABS_LD_HU
:
4278 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
4281 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4284 tcg_temp_free(temp
);
4287 static void decode_abs_ldst_swap(CPUTriCoreState
*env
, DisasContext
*ctx
)
4294 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4295 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4296 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4298 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4301 case OPC2_32_ABS_LDMST
:
4302 gen_ldmst(ctx
, r1
, temp
);
4304 case OPC2_32_ABS_SWAP_W
:
4305 gen_swap(ctx
, r1
, temp
);
4308 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4311 tcg_temp_free(temp
);
4314 static void decode_abs_ldst_context(CPUTriCoreState
*env
, DisasContext
*ctx
)
4319 off18
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4320 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4323 case OPC2_32_ABS_LDLCX
:
4324 gen_helper_1arg(ldlcx
, EA_ABS_FORMAT(off18
));
4326 case OPC2_32_ABS_LDUCX
:
4327 gen_helper_1arg(lducx
, EA_ABS_FORMAT(off18
));
4329 case OPC2_32_ABS_STLCX
:
4330 gen_helper_1arg(stlcx
, EA_ABS_FORMAT(off18
));
4332 case OPC2_32_ABS_STUCX
:
4333 gen_helper_1arg(stucx
, EA_ABS_FORMAT(off18
));
4336 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4340 static void decode_abs_store(CPUTriCoreState
*env
, DisasContext
*ctx
)
4347 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4348 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4349 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4351 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4354 case OPC2_32_ABS_ST_A
:
4355 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4357 case OPC2_32_ABS_ST_D
:
4359 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4361 case OPC2_32_ABS_ST_DA
:
4363 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4365 case OPC2_32_ABS_ST_W
:
4366 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LESL
);
4369 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4371 tcg_temp_free(temp
);
4374 static void decode_abs_storeb_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
4381 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
4382 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
4383 op2
= MASK_OP_ABS_OP2(ctx
->opcode
);
4385 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
4388 case OPC2_32_ABS_ST_B
:
4389 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_UB
);
4391 case OPC2_32_ABS_ST_H
:
4392 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
4395 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4397 tcg_temp_free(temp
);
4402 static void decode_bit_andacc(CPUTriCoreState
*env
, DisasContext
*ctx
)
4408 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4409 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4410 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4411 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4412 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4413 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4417 case OPC2_32_BIT_AND_AND_T
:
4418 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4419 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_and_tl
);
4421 case OPC2_32_BIT_AND_ANDN_T
:
4422 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4423 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_and_tl
);
4425 case OPC2_32_BIT_AND_NOR_T
:
4426 if (TCG_TARGET_HAS_andc_i32
) {
4427 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4428 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_andc_tl
);
4430 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4431 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_and_tl
);
4434 case OPC2_32_BIT_AND_OR_T
:
4435 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4436 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_and_tl
);
4439 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4443 static void decode_bit_logical_t(CPUTriCoreState
*env
, DisasContext
*ctx
)
4448 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4449 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4450 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4451 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4452 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4453 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4456 case OPC2_32_BIT_AND_T
:
4457 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4458 pos1
, pos2
, &tcg_gen_and_tl
);
4460 case OPC2_32_BIT_ANDN_T
:
4461 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4462 pos1
, pos2
, &tcg_gen_andc_tl
);
4464 case OPC2_32_BIT_NOR_T
:
4465 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4466 pos1
, pos2
, &tcg_gen_nor_tl
);
4468 case OPC2_32_BIT_OR_T
:
4469 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4470 pos1
, pos2
, &tcg_gen_or_tl
);
4473 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4477 static void decode_bit_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
4483 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4484 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4485 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4486 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4487 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4488 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4490 temp
= tcg_temp_new();
4492 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r2
], pos2
);
4493 if (op2
== OPC2_32_BIT_INSN_T
) {
4494 tcg_gen_not_tl(temp
, temp
);
4496 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp
, pos1
, 1);
4497 tcg_temp_free(temp
);
4500 static void decode_bit_logical_t2(CPUTriCoreState
*env
, DisasContext
*ctx
)
4507 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4508 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4509 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4510 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4511 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4512 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4515 case OPC2_32_BIT_NAND_T
:
4516 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4517 pos1
, pos2
, &tcg_gen_nand_tl
);
4519 case OPC2_32_BIT_ORN_T
:
4520 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4521 pos1
, pos2
, &tcg_gen_orc_tl
);
4523 case OPC2_32_BIT_XNOR_T
:
4524 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4525 pos1
, pos2
, &tcg_gen_eqv_tl
);
4527 case OPC2_32_BIT_XOR_T
:
4528 gen_bit_1op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4529 pos1
, pos2
, &tcg_gen_xor_tl
);
4532 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4536 static void decode_bit_orand(CPUTriCoreState
*env
, DisasContext
*ctx
)
4543 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4544 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4545 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4546 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4547 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4548 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4551 case OPC2_32_BIT_OR_AND_T
:
4552 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4553 pos1
, pos2
, &tcg_gen_and_tl
, &tcg_gen_or_tl
);
4555 case OPC2_32_BIT_OR_ANDN_T
:
4556 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4557 pos1
, pos2
, &tcg_gen_andc_tl
, &tcg_gen_or_tl
);
4559 case OPC2_32_BIT_OR_NOR_T
:
4560 if (TCG_TARGET_HAS_orc_i32
) {
4561 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4562 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_orc_tl
);
4564 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4565 pos1
, pos2
, &tcg_gen_nor_tl
, &tcg_gen_or_tl
);
4568 case OPC2_32_BIT_OR_OR_T
:
4569 gen_bit_2op(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4570 pos1
, pos2
, &tcg_gen_or_tl
, &tcg_gen_or_tl
);
4573 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4577 static void decode_bit_sh_logic1(CPUTriCoreState
*env
, DisasContext
*ctx
)
4584 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4585 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4586 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4587 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4588 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4589 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4591 temp
= tcg_temp_new();
4594 case OPC2_32_BIT_SH_AND_T
:
4595 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4596 pos1
, pos2
, &tcg_gen_and_tl
);
4598 case OPC2_32_BIT_SH_ANDN_T
:
4599 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4600 pos1
, pos2
, &tcg_gen_andc_tl
);
4602 case OPC2_32_BIT_SH_NOR_T
:
4603 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4604 pos1
, pos2
, &tcg_gen_nor_tl
);
4606 case OPC2_32_BIT_SH_OR_T
:
4607 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4608 pos1
, pos2
, &tcg_gen_or_tl
);
4611 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4613 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
4614 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
4615 tcg_temp_free(temp
);
4618 static void decode_bit_sh_logic2(CPUTriCoreState
*env
, DisasContext
*ctx
)
4625 op2
= MASK_OP_BIT_OP2(ctx
->opcode
);
4626 r1
= MASK_OP_BIT_S1(ctx
->opcode
);
4627 r2
= MASK_OP_BIT_S2(ctx
->opcode
);
4628 r3
= MASK_OP_BIT_D(ctx
->opcode
);
4629 pos1
= MASK_OP_BIT_POS1(ctx
->opcode
);
4630 pos2
= MASK_OP_BIT_POS2(ctx
->opcode
);
4632 temp
= tcg_temp_new();
4635 case OPC2_32_BIT_SH_NAND_T
:
4636 gen_bit_1op(temp
, cpu_gpr_d
[r1
] , cpu_gpr_d
[r2
] ,
4637 pos1
, pos2
, &tcg_gen_nand_tl
);
4639 case OPC2_32_BIT_SH_ORN_T
:
4640 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4641 pos1
, pos2
, &tcg_gen_orc_tl
);
4643 case OPC2_32_BIT_SH_XNOR_T
:
4644 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4645 pos1
, pos2
, &tcg_gen_eqv_tl
);
4647 case OPC2_32_BIT_SH_XOR_T
:
4648 gen_bit_1op(temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
4649 pos1
, pos2
, &tcg_gen_xor_tl
);
4652 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4654 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 1);
4655 tcg_gen_add_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
4656 tcg_temp_free(temp
);
4662 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState
*env
,
4670 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4671 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4672 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4673 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4676 case OPC2_32_BO_CACHEA_WI_SHORTOFF
:
4677 case OPC2_32_BO_CACHEA_W_SHORTOFF
:
4678 case OPC2_32_BO_CACHEA_I_SHORTOFF
:
4679 /* instruction to access the cache */
4681 case OPC2_32_BO_CACHEA_WI_POSTINC
:
4682 case OPC2_32_BO_CACHEA_W_POSTINC
:
4683 case OPC2_32_BO_CACHEA_I_POSTINC
:
4684 /* instruction to access the cache, but we still need to handle
4685 the addressing mode */
4686 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4688 case OPC2_32_BO_CACHEA_WI_PREINC
:
4689 case OPC2_32_BO_CACHEA_W_PREINC
:
4690 case OPC2_32_BO_CACHEA_I_PREINC
:
4691 /* instruction to access the cache, but we still need to handle
4692 the addressing mode */
4693 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4695 case OPC2_32_BO_CACHEI_WI_SHORTOFF
:
4696 case OPC2_32_BO_CACHEI_W_SHORTOFF
:
4697 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
4698 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4701 case OPC2_32_BO_CACHEI_W_POSTINC
:
4702 case OPC2_32_BO_CACHEI_WI_POSTINC
:
4703 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
4704 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4706 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4709 case OPC2_32_BO_CACHEI_W_PREINC
:
4710 case OPC2_32_BO_CACHEI_WI_PREINC
:
4711 if (tricore_feature(env
, TRICORE_FEATURE_131
)) {
4712 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4714 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4717 case OPC2_32_BO_ST_A_SHORTOFF
:
4718 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
4720 case OPC2_32_BO_ST_A_POSTINC
:
4721 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4723 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4725 case OPC2_32_BO_ST_A_PREINC
:
4726 gen_st_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESL
);
4728 case OPC2_32_BO_ST_B_SHORTOFF
:
4729 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4731 case OPC2_32_BO_ST_B_POSTINC
:
4732 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4734 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4736 case OPC2_32_BO_ST_B_PREINC
:
4737 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4739 case OPC2_32_BO_ST_D_SHORTOFF
:
4741 gen_offset_st_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
4744 case OPC2_32_BO_ST_D_POSTINC
:
4746 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
4747 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4749 case OPC2_32_BO_ST_D_PREINC
:
4751 temp
= tcg_temp_new();
4752 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4753 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4754 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4755 tcg_temp_free(temp
);
4757 case OPC2_32_BO_ST_DA_SHORTOFF
:
4759 gen_offset_st_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
4762 case OPC2_32_BO_ST_DA_POSTINC
:
4764 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
4765 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4767 case OPC2_32_BO_ST_DA_PREINC
:
4769 temp
= tcg_temp_new();
4770 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4771 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
4772 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4773 tcg_temp_free(temp
);
4775 case OPC2_32_BO_ST_H_SHORTOFF
:
4776 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4778 case OPC2_32_BO_ST_H_POSTINC
:
4779 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4781 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4783 case OPC2_32_BO_ST_H_PREINC
:
4784 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4786 case OPC2_32_BO_ST_Q_SHORTOFF
:
4787 temp
= tcg_temp_new();
4788 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4789 gen_offset_st(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4790 tcg_temp_free(temp
);
4792 case OPC2_32_BO_ST_Q_POSTINC
:
4793 temp
= tcg_temp_new();
4794 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4795 tcg_gen_qemu_st_tl(temp
, cpu_gpr_a
[r2
], ctx
->mem_idx
,
4797 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4798 tcg_temp_free(temp
);
4800 case OPC2_32_BO_ST_Q_PREINC
:
4801 temp
= tcg_temp_new();
4802 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4803 gen_st_preincr(ctx
, temp
, cpu_gpr_a
[r2
], off10
, MO_LEUW
);
4804 tcg_temp_free(temp
);
4806 case OPC2_32_BO_ST_W_SHORTOFF
:
4807 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4809 case OPC2_32_BO_ST_W_POSTINC
:
4810 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4812 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4814 case OPC2_32_BO_ST_W_PREINC
:
4815 gen_st_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4818 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4822 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState
*env
,
4828 TCGv temp
, temp2
, temp3
;
4830 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4831 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4832 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4833 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4835 temp
= tcg_temp_new();
4836 temp2
= tcg_temp_new();
4837 temp3
= tcg_const_i32(off10
);
4839 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
4840 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4843 case OPC2_32_BO_CACHEA_WI_BR
:
4844 case OPC2_32_BO_CACHEA_W_BR
:
4845 case OPC2_32_BO_CACHEA_I_BR
:
4846 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4848 case OPC2_32_BO_CACHEA_WI_CIRC
:
4849 case OPC2_32_BO_CACHEA_W_CIRC
:
4850 case OPC2_32_BO_CACHEA_I_CIRC
:
4851 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4853 case OPC2_32_BO_ST_A_BR
:
4854 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4855 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4857 case OPC2_32_BO_ST_A_CIRC
:
4858 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4859 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4861 case OPC2_32_BO_ST_B_BR
:
4862 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4863 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4865 case OPC2_32_BO_ST_B_CIRC
:
4866 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
4867 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4869 case OPC2_32_BO_ST_D_BR
:
4871 gen_st_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
4872 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4874 case OPC2_32_BO_ST_D_CIRC
:
4876 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4877 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4878 tcg_gen_addi_tl(temp
, temp
, 4);
4879 tcg_gen_rem_tl(temp
, temp
, temp2
);
4880 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4881 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4882 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4884 case OPC2_32_BO_ST_DA_BR
:
4886 gen_st_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
4887 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4889 case OPC2_32_BO_ST_DA_CIRC
:
4891 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4892 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
4893 tcg_gen_addi_tl(temp
, temp
, 4);
4894 tcg_gen_rem_tl(temp
, temp
, temp2
);
4895 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
4896 tcg_gen_qemu_st_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
4897 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4899 case OPC2_32_BO_ST_H_BR
:
4900 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4901 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4903 case OPC2_32_BO_ST_H_CIRC
:
4904 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
4905 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4907 case OPC2_32_BO_ST_Q_BR
:
4908 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4909 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
4910 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4912 case OPC2_32_BO_ST_Q_CIRC
:
4913 tcg_gen_shri_tl(temp
, cpu_gpr_d
[r1
], 16);
4914 tcg_gen_qemu_st_tl(temp
, temp2
, ctx
->mem_idx
, MO_LEUW
);
4915 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4917 case OPC2_32_BO_ST_W_BR
:
4918 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4919 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
4921 case OPC2_32_BO_ST_W_CIRC
:
4922 tcg_gen_qemu_st_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
4923 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
4926 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
4928 tcg_temp_free(temp
);
4929 tcg_temp_free(temp2
);
4930 tcg_temp_free(temp3
);
4933 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState
*env
,
4941 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
4942 r2
= MASK_OP_BO_S2(ctx
->opcode
);
4943 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
4944 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
4947 case OPC2_32_BO_LD_A_SHORTOFF
:
4948 gen_offset_ld(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4950 case OPC2_32_BO_LD_A_POSTINC
:
4951 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4953 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4955 case OPC2_32_BO_LD_A_PREINC
:
4956 gen_ld_preincr(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
4958 case OPC2_32_BO_LD_B_SHORTOFF
:
4959 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4961 case OPC2_32_BO_LD_B_POSTINC
:
4962 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4964 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4966 case OPC2_32_BO_LD_B_PREINC
:
4967 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4969 case OPC2_32_BO_LD_BU_SHORTOFF
:
4970 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_UB
);
4972 case OPC2_32_BO_LD_BU_POSTINC
:
4973 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
4975 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4977 case OPC2_32_BO_LD_BU_PREINC
:
4978 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_SB
);
4980 case OPC2_32_BO_LD_D_SHORTOFF
:
4982 gen_offset_ld_2regs(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
],
4985 case OPC2_32_BO_LD_D_POSTINC
:
4987 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
);
4988 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
4990 case OPC2_32_BO_LD_D_PREINC
:
4992 temp
= tcg_temp_new();
4993 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
4994 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp
, ctx
);
4995 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
4996 tcg_temp_free(temp
);
4998 case OPC2_32_BO_LD_DA_SHORTOFF
:
5000 gen_offset_ld_2regs(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
],
5003 case OPC2_32_BO_LD_DA_POSTINC
:
5005 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], ctx
);
5006 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5008 case OPC2_32_BO_LD_DA_PREINC
:
5010 temp
= tcg_temp_new();
5011 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5012 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp
, ctx
);
5013 tcg_gen_mov_tl(cpu_gpr_a
[r2
], temp
);
5014 tcg_temp_free(temp
);
5016 case OPC2_32_BO_LD_H_SHORTOFF
:
5017 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
5019 case OPC2_32_BO_LD_H_POSTINC
:
5020 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5022 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5024 case OPC2_32_BO_LD_H_PREINC
:
5025 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LESW
);
5027 case OPC2_32_BO_LD_HU_SHORTOFF
:
5028 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5030 case OPC2_32_BO_LD_HU_POSTINC
:
5031 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5033 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5035 case OPC2_32_BO_LD_HU_PREINC
:
5036 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5038 case OPC2_32_BO_LD_Q_SHORTOFF
:
5039 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5040 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5042 case OPC2_32_BO_LD_Q_POSTINC
:
5043 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5045 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5046 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5048 case OPC2_32_BO_LD_Q_PREINC
:
5049 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUW
);
5050 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5052 case OPC2_32_BO_LD_W_SHORTOFF
:
5053 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
5055 case OPC2_32_BO_LD_W_POSTINC
:
5056 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], ctx
->mem_idx
,
5058 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5060 case OPC2_32_BO_LD_W_PREINC
:
5061 gen_ld_preincr(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], off10
, MO_LEUL
);
5064 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5068 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState
*env
,
5075 TCGv temp
, temp2
, temp3
;
5077 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5078 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5079 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5080 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5082 temp
= tcg_temp_new();
5083 temp2
= tcg_temp_new();
5084 temp3
= tcg_const_i32(off10
);
5086 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
5087 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5091 case OPC2_32_BO_LD_A_BR
:
5092 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5093 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5095 case OPC2_32_BO_LD_A_CIRC
:
5096 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5097 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5099 case OPC2_32_BO_LD_B_BR
:
5100 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
5101 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5103 case OPC2_32_BO_LD_B_CIRC
:
5104 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_SB
);
5105 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5107 case OPC2_32_BO_LD_BU_BR
:
5108 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
5109 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5111 case OPC2_32_BO_LD_BU_CIRC
:
5112 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_UB
);
5113 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5115 case OPC2_32_BO_LD_D_BR
:
5117 gen_ld_2regs_64(cpu_gpr_d
[r1
+1], cpu_gpr_d
[r1
], temp2
, ctx
);
5118 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5120 case OPC2_32_BO_LD_D_CIRC
:
5122 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5123 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
5124 tcg_gen_addi_tl(temp
, temp
, 4);
5125 tcg_gen_rem_tl(temp
, temp
, temp2
);
5126 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5127 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
5128 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5130 case OPC2_32_BO_LD_DA_BR
:
5132 gen_ld_2regs_64(cpu_gpr_a
[r1
+1], cpu_gpr_a
[r1
], temp2
, ctx
);
5133 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5135 case OPC2_32_BO_LD_DA_CIRC
:
5137 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5138 tcg_gen_shri_tl(temp2
, cpu_gpr_a
[r2
+1], 16);
5139 tcg_gen_addi_tl(temp
, temp
, 4);
5140 tcg_gen_rem_tl(temp
, temp
, temp2
);
5141 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5142 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
+1], temp2
, ctx
->mem_idx
, MO_LEUL
);
5143 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5145 case OPC2_32_BO_LD_H_BR
:
5146 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
5147 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5149 case OPC2_32_BO_LD_H_CIRC
:
5150 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LESW
);
5151 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5153 case OPC2_32_BO_LD_HU_BR
:
5154 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5155 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5157 case OPC2_32_BO_LD_HU_CIRC
:
5158 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5159 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5161 case OPC2_32_BO_LD_Q_BR
:
5162 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5163 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5164 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5166 case OPC2_32_BO_LD_Q_CIRC
:
5167 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUW
);
5168 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
5169 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5171 case OPC2_32_BO_LD_W_BR
:
5172 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5173 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5175 case OPC2_32_BO_LD_W_CIRC
:
5176 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp2
, ctx
->mem_idx
, MO_LEUL
);
5177 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5180 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5182 tcg_temp_free(temp
);
5183 tcg_temp_free(temp2
);
5184 tcg_temp_free(temp3
);
5187 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState
*env
,
5196 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5197 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5198 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5199 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5202 temp
= tcg_temp_new();
5203 temp2
= tcg_temp_new();
5206 case OPC2_32_BO_LDLCX_SHORTOFF
:
5207 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5208 gen_helper_ldlcx(cpu_env
, temp
);
5210 case OPC2_32_BO_LDMST_SHORTOFF
:
5211 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5212 gen_ldmst(ctx
, r1
, temp
);
5214 case OPC2_32_BO_LDMST_POSTINC
:
5215 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
5216 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5218 case OPC2_32_BO_LDMST_PREINC
:
5219 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5220 gen_ldmst(ctx
, r1
, cpu_gpr_a
[r2
]);
5222 case OPC2_32_BO_LDUCX_SHORTOFF
:
5223 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5224 gen_helper_lducx(cpu_env
, temp
);
5226 case OPC2_32_BO_LEA_SHORTOFF
:
5227 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], off10
);
5229 case OPC2_32_BO_STLCX_SHORTOFF
:
5230 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5231 gen_helper_stlcx(cpu_env
, temp
);
5233 case OPC2_32_BO_STUCX_SHORTOFF
:
5234 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5235 gen_helper_stucx(cpu_env
, temp
);
5237 case OPC2_32_BO_SWAP_W_SHORTOFF
:
5238 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5239 gen_swap(ctx
, r1
, temp
);
5241 case OPC2_32_BO_SWAP_W_POSTINC
:
5242 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
5243 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5245 case OPC2_32_BO_SWAP_W_PREINC
:
5246 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5247 gen_swap(ctx
, r1
, cpu_gpr_a
[r2
]);
5249 case OPC2_32_BO_CMPSWAP_W_SHORTOFF
:
5250 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5251 gen_cmpswap(ctx
, r1
, temp
);
5253 case OPC2_32_BO_CMPSWAP_W_POSTINC
:
5254 gen_cmpswap(ctx
, r1
, cpu_gpr_a
[r2
]);
5255 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5257 case OPC2_32_BO_CMPSWAP_W_PREINC
:
5258 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5259 gen_cmpswap(ctx
, r1
, cpu_gpr_a
[r2
]);
5261 case OPC2_32_BO_SWAPMSK_W_SHORTOFF
:
5262 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], off10
);
5263 gen_swapmsk(ctx
, r1
, temp
);
5265 case OPC2_32_BO_SWAPMSK_W_POSTINC
:
5266 gen_swapmsk(ctx
, r1
, cpu_gpr_a
[r2
]);
5267 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5269 case OPC2_32_BO_SWAPMSK_W_PREINC
:
5270 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r2
], off10
);
5271 gen_swapmsk(ctx
, r1
, cpu_gpr_a
[r2
]);
5274 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5276 tcg_temp_free(temp
);
5277 tcg_temp_free(temp2
);
5280 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState
*env
,
5287 TCGv temp
, temp2
, temp3
;
5289 r1
= MASK_OP_BO_S1D(ctx
->opcode
);
5290 r2
= MASK_OP_BO_S2(ctx
->opcode
);
5291 off10
= MASK_OP_BO_OFF10_SEXT(ctx
->opcode
);
5292 op2
= MASK_OP_BO_OP2(ctx
->opcode
);
5294 temp
= tcg_temp_new();
5295 temp2
= tcg_temp_new();
5296 temp3
= tcg_const_i32(off10
);
5298 tcg_gen_ext16u_tl(temp
, cpu_gpr_a
[r2
+1]);
5299 tcg_gen_add_tl(temp2
, cpu_gpr_a
[r2
], temp
);
5302 case OPC2_32_BO_LDMST_BR
:
5303 gen_ldmst(ctx
, r1
, temp2
);
5304 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5306 case OPC2_32_BO_LDMST_CIRC
:
5307 gen_ldmst(ctx
, r1
, temp2
);
5308 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5310 case OPC2_32_BO_SWAP_W_BR
:
5311 gen_swap(ctx
, r1
, temp2
);
5312 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5314 case OPC2_32_BO_SWAP_W_CIRC
:
5315 gen_swap(ctx
, r1
, temp2
);
5316 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5318 case OPC2_32_BO_CMPSWAP_W_BR
:
5319 gen_cmpswap(ctx
, r1
, temp2
);
5320 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5322 case OPC2_32_BO_CMPSWAP_W_CIRC
:
5323 gen_cmpswap(ctx
, r1
, temp2
);
5324 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5326 case OPC2_32_BO_SWAPMSK_W_BR
:
5327 gen_swapmsk(ctx
, r1
, temp2
);
5328 gen_helper_br_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1]);
5330 case OPC2_32_BO_SWAPMSK_W_CIRC
:
5331 gen_swapmsk(ctx
, r1
, temp2
);
5332 gen_helper_circ_update(cpu_gpr_a
[r2
+1], cpu_gpr_a
[r2
+1], temp3
);
5335 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5338 tcg_temp_free(temp
);
5339 tcg_temp_free(temp2
);
5340 tcg_temp_free(temp3
);
5343 static void decode_bol_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int32_t op1
)
5349 r1
= MASK_OP_BOL_S1D(ctx
->opcode
);
5350 r2
= MASK_OP_BOL_S2(ctx
->opcode
);
5351 address
= MASK_OP_BOL_OFF16_SEXT(ctx
->opcode
);
5354 case OPC1_32_BOL_LD_A_LONGOFF
:
5355 temp
= tcg_temp_new();
5356 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
5357 tcg_gen_qemu_ld_tl(cpu_gpr_a
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
5358 tcg_temp_free(temp
);
5360 case OPC1_32_BOL_LD_W_LONGOFF
:
5361 temp
= tcg_temp_new();
5362 tcg_gen_addi_tl(temp
, cpu_gpr_a
[r2
], address
);
5363 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUL
);
5364 tcg_temp_free(temp
);
5366 case OPC1_32_BOL_LEA_LONGOFF
:
5367 tcg_gen_addi_tl(cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
);
5369 case OPC1_32_BOL_ST_A_LONGOFF
:
5370 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5371 gen_offset_st(ctx
, cpu_gpr_a
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
5373 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5376 case OPC1_32_BOL_ST_W_LONGOFF
:
5377 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUL
);
5379 case OPC1_32_BOL_LD_B_LONGOFF
:
5380 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5381 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
5383 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5386 case OPC1_32_BOL_LD_BU_LONGOFF
:
5387 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5388 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_UB
);
5390 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5393 case OPC1_32_BOL_LD_H_LONGOFF
:
5394 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5395 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
5397 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5400 case OPC1_32_BOL_LD_HU_LONGOFF
:
5401 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5402 gen_offset_ld(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LEUW
);
5404 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5407 case OPC1_32_BOL_ST_B_LONGOFF
:
5408 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5409 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_SB
);
5411 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5414 case OPC1_32_BOL_ST_H_LONGOFF
:
5415 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
5416 gen_offset_st(ctx
, cpu_gpr_d
[r1
], cpu_gpr_a
[r2
], address
, MO_LESW
);
5418 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5422 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5427 static void decode_rc_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
5434 r2
= MASK_OP_RC_D(ctx
->opcode
);
5435 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5436 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5437 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5439 temp
= tcg_temp_new();
5442 case OPC2_32_RC_AND
:
5443 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5445 case OPC2_32_RC_ANDN
:
5446 tcg_gen_andi_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
5448 case OPC2_32_RC_NAND
:
5449 tcg_gen_movi_tl(temp
, const9
);
5450 tcg_gen_nand_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
5452 case OPC2_32_RC_NOR
:
5453 tcg_gen_movi_tl(temp
, const9
);
5454 tcg_gen_nor_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
);
5457 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5459 case OPC2_32_RC_ORN
:
5460 tcg_gen_ori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], ~const9
);
5463 const9
= sextract32(const9
, 0, 6);
5464 gen_shi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5466 case OPC2_32_RC_SH_H
:
5467 const9
= sextract32(const9
, 0, 5);
5468 gen_sh_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5470 case OPC2_32_RC_SHA
:
5471 const9
= sextract32(const9
, 0, 6);
5472 gen_shaci(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5474 case OPC2_32_RC_SHA_H
:
5475 const9
= sextract32(const9
, 0, 5);
5476 gen_sha_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5478 case OPC2_32_RC_SHAS
:
5479 gen_shasi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5481 case OPC2_32_RC_XNOR
:
5482 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5483 tcg_gen_not_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
]);
5485 case OPC2_32_RC_XOR
:
5486 tcg_gen_xori_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5489 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5491 tcg_temp_free(temp
);
5494 static void decode_rc_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
5502 r2
= MASK_OP_RC_D(ctx
->opcode
);
5503 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5504 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
5506 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5508 temp
= tcg_temp_new();
5511 case OPC2_32_RC_ABSDIF
:
5512 gen_absdifi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5514 case OPC2_32_RC_ABSDIFS
:
5515 gen_absdifsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5517 case OPC2_32_RC_ADD
:
5518 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5520 case OPC2_32_RC_ADDC
:
5521 gen_addci_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5523 case OPC2_32_RC_ADDS
:
5524 gen_addsi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5526 case OPC2_32_RC_ADDS_U
:
5527 gen_addsui(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5529 case OPC2_32_RC_ADDX
:
5530 gen_addi_CC(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5532 case OPC2_32_RC_AND_EQ
:
5533 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5534 const9
, &tcg_gen_and_tl
);
5536 case OPC2_32_RC_AND_GE
:
5537 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5538 const9
, &tcg_gen_and_tl
);
5540 case OPC2_32_RC_AND_GE_U
:
5541 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5542 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5543 const9
, &tcg_gen_and_tl
);
5545 case OPC2_32_RC_AND_LT
:
5546 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5547 const9
, &tcg_gen_and_tl
);
5549 case OPC2_32_RC_AND_LT_U
:
5550 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5551 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5552 const9
, &tcg_gen_and_tl
);
5554 case OPC2_32_RC_AND_NE
:
5555 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5556 const9
, &tcg_gen_and_tl
);
5559 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5561 case OPC2_32_RC_EQANY_B
:
5562 gen_eqany_bi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5564 case OPC2_32_RC_EQANY_H
:
5565 gen_eqany_hi(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5568 tcg_gen_setcondi_tl(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5570 case OPC2_32_RC_GE_U
:
5571 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5572 tcg_gen_setcondi_tl(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5575 tcg_gen_setcondi_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5577 case OPC2_32_RC_LT_U
:
5578 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5579 tcg_gen_setcondi_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5581 case OPC2_32_RC_MAX
:
5582 tcg_gen_movi_tl(temp
, const9
);
5583 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5584 cpu_gpr_d
[r1
], temp
);
5586 case OPC2_32_RC_MAX_U
:
5587 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
5588 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5589 cpu_gpr_d
[r1
], temp
);
5591 case OPC2_32_RC_MIN
:
5592 tcg_gen_movi_tl(temp
, const9
);
5593 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5594 cpu_gpr_d
[r1
], temp
);
5596 case OPC2_32_RC_MIN_U
:
5597 tcg_gen_movi_tl(temp
, MASK_OP_RC_CONST9(ctx
->opcode
));
5598 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
,
5599 cpu_gpr_d
[r1
], temp
);
5602 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5604 case OPC2_32_RC_OR_EQ
:
5605 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5606 const9
, &tcg_gen_or_tl
);
5608 case OPC2_32_RC_OR_GE
:
5609 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5610 const9
, &tcg_gen_or_tl
);
5612 case OPC2_32_RC_OR_GE_U
:
5613 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5614 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5615 const9
, &tcg_gen_or_tl
);
5617 case OPC2_32_RC_OR_LT
:
5618 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5619 const9
, &tcg_gen_or_tl
);
5621 case OPC2_32_RC_OR_LT_U
:
5622 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5623 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5624 const9
, &tcg_gen_or_tl
);
5626 case OPC2_32_RC_OR_NE
:
5627 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5628 const9
, &tcg_gen_or_tl
);
5630 case OPC2_32_RC_RSUB
:
5631 tcg_gen_movi_tl(temp
, const9
);
5632 gen_sub_d(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5634 case OPC2_32_RC_RSUBS
:
5635 tcg_gen_movi_tl(temp
, const9
);
5636 gen_subs(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5638 case OPC2_32_RC_RSUBS_U
:
5639 tcg_gen_movi_tl(temp
, const9
);
5640 gen_subsu(cpu_gpr_d
[r2
], temp
, cpu_gpr_d
[r1
]);
5642 case OPC2_32_RC_SH_EQ
:
5643 gen_sh_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5645 case OPC2_32_RC_SH_GE
:
5646 gen_sh_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5648 case OPC2_32_RC_SH_GE_U
:
5649 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5650 gen_sh_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5652 case OPC2_32_RC_SH_LT
:
5653 gen_sh_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5655 case OPC2_32_RC_SH_LT_U
:
5656 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5657 gen_sh_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5659 case OPC2_32_RC_SH_NE
:
5660 gen_sh_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5662 case OPC2_32_RC_XOR_EQ
:
5663 gen_accumulating_condi(TCG_COND_EQ
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5664 const9
, &tcg_gen_xor_tl
);
5666 case OPC2_32_RC_XOR_GE
:
5667 gen_accumulating_condi(TCG_COND_GE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5668 const9
, &tcg_gen_xor_tl
);
5670 case OPC2_32_RC_XOR_GE_U
:
5671 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5672 gen_accumulating_condi(TCG_COND_GEU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5673 const9
, &tcg_gen_xor_tl
);
5675 case OPC2_32_RC_XOR_LT
:
5676 gen_accumulating_condi(TCG_COND_LT
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5677 const9
, &tcg_gen_xor_tl
);
5679 case OPC2_32_RC_XOR_LT_U
:
5680 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5681 gen_accumulating_condi(TCG_COND_LTU
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5682 const9
, &tcg_gen_xor_tl
);
5684 case OPC2_32_RC_XOR_NE
:
5685 gen_accumulating_condi(TCG_COND_NE
, cpu_gpr_d
[r2
], cpu_gpr_d
[r1
],
5686 const9
, &tcg_gen_xor_tl
);
5689 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5691 tcg_temp_free(temp
);
5694 static void decode_rc_serviceroutine(CPUTriCoreState
*env
, DisasContext
*ctx
)
5699 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5700 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5703 case OPC2_32_RC_BISR
:
5704 gen_helper_1arg(bisr
, const9
);
5706 case OPC2_32_RC_SYSCALL
:
5707 /* TODO: Add exception generation */
5710 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5714 static void decode_rc_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
5720 r2
= MASK_OP_RC_D(ctx
->opcode
);
5721 r1
= MASK_OP_RC_S1(ctx
->opcode
);
5722 const9
= MASK_OP_RC_CONST9_SEXT(ctx
->opcode
);
5724 op2
= MASK_OP_RC_OP2(ctx
->opcode
);
5727 case OPC2_32_RC_MUL_32
:
5728 gen_muli_i32s(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5730 case OPC2_32_RC_MUL_64
:
5732 gen_muli_i64s(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
5734 case OPC2_32_RC_MULS_32
:
5735 gen_mulsi_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5737 case OPC2_32_RC_MUL_U_64
:
5738 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5740 gen_muli_i64u(cpu_gpr_d
[r2
], cpu_gpr_d
[r2
+1], cpu_gpr_d
[r1
], const9
);
5742 case OPC2_32_RC_MULS_U_32
:
5743 const9
= MASK_OP_RC_CONST9(ctx
->opcode
);
5744 gen_mulsui_i32(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const9
);
5747 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5752 static void decode_rcpw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
5756 int32_t pos
, width
, const4
;
5760 op2
= MASK_OP_RCPW_OP2(ctx
->opcode
);
5761 r1
= MASK_OP_RCPW_S1(ctx
->opcode
);
5762 r2
= MASK_OP_RCPW_D(ctx
->opcode
);
5763 const4
= MASK_OP_RCPW_CONST4(ctx
->opcode
);
5764 width
= MASK_OP_RCPW_WIDTH(ctx
->opcode
);
5765 pos
= MASK_OP_RCPW_POS(ctx
->opcode
);
5768 case OPC2_32_RCPW_IMASK
:
5770 /* if pos + width > 31 undefined result */
5771 if (pos
+ width
<= 31) {
5772 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], ((1u << width
) - 1) << pos
);
5773 tcg_gen_movi_tl(cpu_gpr_d
[r2
], (const4
<< pos
));
5776 case OPC2_32_RCPW_INSERT
:
5777 /* if pos + width > 32 undefined result */
5778 if (pos
+ width
<= 32) {
5779 temp
= tcg_const_i32(const4
);
5780 tcg_gen_deposit_tl(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, pos
, width
);
5781 tcg_temp_free(temp
);
5785 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5791 static void decode_rcrw_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
5795 int32_t width
, const4
;
5797 TCGv temp
, temp2
, temp3
;
5799 op2
= MASK_OP_RCRW_OP2(ctx
->opcode
);
5800 r1
= MASK_OP_RCRW_S1(ctx
->opcode
);
5801 r3
= MASK_OP_RCRW_S3(ctx
->opcode
);
5802 r4
= MASK_OP_RCRW_D(ctx
->opcode
);
5803 width
= MASK_OP_RCRW_WIDTH(ctx
->opcode
);
5804 const4
= MASK_OP_RCRW_CONST4(ctx
->opcode
);
5806 temp
= tcg_temp_new();
5807 temp2
= tcg_temp_new();
5810 case OPC2_32_RCRW_IMASK
:
5811 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r4
], 0x1f);
5812 tcg_gen_movi_tl(temp2
, (1 << width
) - 1);
5813 tcg_gen_shl_tl(cpu_gpr_d
[r3
+ 1], temp2
, temp
);
5814 tcg_gen_movi_tl(temp2
, const4
);
5815 tcg_gen_shl_tl(cpu_gpr_d
[r3
], temp2
, temp
);
5817 case OPC2_32_RCRW_INSERT
:
5818 temp3
= tcg_temp_new();
5820 tcg_gen_movi_tl(temp
, width
);
5821 tcg_gen_movi_tl(temp2
, const4
);
5822 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r4
], 0x1f);
5823 gen_insert(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], temp2
, temp
, temp3
);
5825 tcg_temp_free(temp3
);
5828 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5830 tcg_temp_free(temp
);
5831 tcg_temp_free(temp2
);
5836 static void decode_rcr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
5844 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5845 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5846 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5847 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5848 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5851 case OPC2_32_RCR_CADD
:
5852 gen_condi_add(TCG_COND_NE
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
5855 case OPC2_32_RCR_CADDN
:
5856 gen_condi_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], const9
, cpu_gpr_d
[r3
],
5859 case OPC2_32_RCR_SEL
:
5860 temp
= tcg_const_i32(0);
5861 temp2
= tcg_const_i32(const9
);
5862 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5863 cpu_gpr_d
[r1
], temp2
);
5864 tcg_temp_free(temp
);
5865 tcg_temp_free(temp2
);
5867 case OPC2_32_RCR_SELN
:
5868 temp
= tcg_const_i32(0);
5869 temp2
= tcg_const_i32(const9
);
5870 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
5871 cpu_gpr_d
[r1
], temp2
);
5872 tcg_temp_free(temp
);
5873 tcg_temp_free(temp2
);
5876 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5880 static void decode_rcr_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
5887 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5888 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5889 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5890 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5891 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5894 case OPC2_32_RCR_MADD_32
:
5895 gen_maddi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5897 case OPC2_32_RCR_MADD_64
:
5900 gen_maddi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5901 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5903 case OPC2_32_RCR_MADDS_32
:
5904 gen_maddsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5906 case OPC2_32_RCR_MADDS_64
:
5909 gen_maddsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5910 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5912 case OPC2_32_RCR_MADD_U_64
:
5915 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5916 gen_maddui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5917 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5919 case OPC2_32_RCR_MADDS_U_32
:
5920 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5921 gen_maddsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5923 case OPC2_32_RCR_MADDS_U_64
:
5926 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5927 gen_maddsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5928 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5931 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5935 static void decode_rcr_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
5942 op2
= MASK_OP_RCR_OP2(ctx
->opcode
);
5943 r1
= MASK_OP_RCR_S1(ctx
->opcode
);
5944 const9
= MASK_OP_RCR_CONST9_SEXT(ctx
->opcode
);
5945 r3
= MASK_OP_RCR_S3(ctx
->opcode
);
5946 r4
= MASK_OP_RCR_D(ctx
->opcode
);
5949 case OPC2_32_RCR_MSUB_32
:
5950 gen_msubi32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5952 case OPC2_32_RCR_MSUB_64
:
5955 gen_msubi64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5956 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5958 case OPC2_32_RCR_MSUBS_32
:
5959 gen_msubsi_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5961 case OPC2_32_RCR_MSUBS_64
:
5964 gen_msubsi_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5965 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5967 case OPC2_32_RCR_MSUB_U_64
:
5970 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5971 gen_msubui64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5972 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5974 case OPC2_32_RCR_MSUBS_U_32
:
5975 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5976 gen_msubsui_32(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
], const9
);
5978 case OPC2_32_RCR_MSUBS_U_64
:
5981 const9
= MASK_OP_RCR_CONST9(ctx
->opcode
);
5982 gen_msubsui_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
5983 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], const9
);
5986 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
5992 static void decode_rlc_opc(CPUTriCoreState
*env
, DisasContext
*ctx
,
5998 const16
= MASK_OP_RLC_CONST16_SEXT(ctx
->opcode
);
5999 r1
= MASK_OP_RLC_S1(ctx
->opcode
);
6000 r2
= MASK_OP_RLC_D(ctx
->opcode
);
6003 case OPC1_32_RLC_ADDI
:
6004 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
);
6006 case OPC1_32_RLC_ADDIH
:
6007 gen_addi_d(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], const16
<< 16);
6009 case OPC1_32_RLC_ADDIH_A
:
6010 tcg_gen_addi_tl(cpu_gpr_a
[r2
], cpu_gpr_a
[r1
], const16
<< 16);
6012 case OPC1_32_RLC_MFCR
:
6013 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6014 gen_mfcr(env
, cpu_gpr_d
[r2
], const16
);
6016 case OPC1_32_RLC_MOV
:
6017 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6019 case OPC1_32_RLC_MOV_64
:
6020 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6022 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6023 tcg_gen_movi_tl(cpu_gpr_d
[r2
+1], const16
>> 15);
6025 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6028 case OPC1_32_RLC_MOV_U
:
6029 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6030 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
);
6032 case OPC1_32_RLC_MOV_H
:
6033 tcg_gen_movi_tl(cpu_gpr_d
[r2
], const16
<< 16);
6035 case OPC1_32_RLC_MOVH_A
:
6036 tcg_gen_movi_tl(cpu_gpr_a
[r2
], const16
<< 16);
6038 case OPC1_32_RLC_MTCR
:
6039 const16
= MASK_OP_RLC_CONST16(ctx
->opcode
);
6040 gen_mtcr(env
, ctx
, cpu_gpr_d
[r1
], const16
);
6043 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6048 static void decode_rr_accumulator(CPUTriCoreState
*env
, DisasContext
*ctx
)
6055 r3
= MASK_OP_RR_D(ctx
->opcode
);
6056 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6057 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6058 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6061 case OPC2_32_RR_ABS
:
6062 gen_abs(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6064 case OPC2_32_RR_ABS_B
:
6065 gen_helper_abs_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6067 case OPC2_32_RR_ABS_H
:
6068 gen_helper_abs_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6070 case OPC2_32_RR_ABSDIF
:
6071 gen_absdif(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6073 case OPC2_32_RR_ABSDIF_B
:
6074 gen_helper_absdif_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6077 case OPC2_32_RR_ABSDIF_H
:
6078 gen_helper_absdif_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6081 case OPC2_32_RR_ABSDIFS
:
6082 gen_helper_absdif_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6085 case OPC2_32_RR_ABSDIFS_H
:
6086 gen_helper_absdif_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6089 case OPC2_32_RR_ABSS
:
6090 gen_helper_abs_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6092 case OPC2_32_RR_ABSS_H
:
6093 gen_helper_abs_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r2
]);
6095 case OPC2_32_RR_ADD
:
6096 gen_add_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6098 case OPC2_32_RR_ADD_B
:
6099 gen_helper_add_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6101 case OPC2_32_RR_ADD_H
:
6102 gen_helper_add_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6104 case OPC2_32_RR_ADDC
:
6105 gen_addc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6107 case OPC2_32_RR_ADDS
:
6108 gen_adds(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6110 case OPC2_32_RR_ADDS_H
:
6111 gen_helper_add_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6114 case OPC2_32_RR_ADDS_HU
:
6115 gen_helper_add_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6118 case OPC2_32_RR_ADDS_U
:
6119 gen_helper_add_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6122 case OPC2_32_RR_ADDX
:
6123 gen_add_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6125 case OPC2_32_RR_AND_EQ
:
6126 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6127 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6129 case OPC2_32_RR_AND_GE
:
6130 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6131 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6133 case OPC2_32_RR_AND_GE_U
:
6134 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6135 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6137 case OPC2_32_RR_AND_LT
:
6138 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6139 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6141 case OPC2_32_RR_AND_LT_U
:
6142 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6143 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6145 case OPC2_32_RR_AND_NE
:
6146 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6147 cpu_gpr_d
[r2
], &tcg_gen_and_tl
);
6150 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6153 case OPC2_32_RR_EQ_B
:
6154 gen_helper_eq_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6156 case OPC2_32_RR_EQ_H
:
6157 gen_helper_eq_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6159 case OPC2_32_RR_EQ_W
:
6160 gen_cond_w(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6162 case OPC2_32_RR_EQANY_B
:
6163 gen_helper_eqany_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6165 case OPC2_32_RR_EQANY_H
:
6166 gen_helper_eqany_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6169 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6172 case OPC2_32_RR_GE_U
:
6173 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6177 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6180 case OPC2_32_RR_LT_U
:
6181 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6184 case OPC2_32_RR_LT_B
:
6185 gen_helper_lt_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6187 case OPC2_32_RR_LT_BU
:
6188 gen_helper_lt_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6190 case OPC2_32_RR_LT_H
:
6191 gen_helper_lt_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6193 case OPC2_32_RR_LT_HU
:
6194 gen_helper_lt_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6196 case OPC2_32_RR_LT_W
:
6197 gen_cond_w(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6199 case OPC2_32_RR_LT_WU
:
6200 gen_cond_w(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6202 case OPC2_32_RR_MAX
:
6203 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6204 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6206 case OPC2_32_RR_MAX_U
:
6207 tcg_gen_movcond_tl(TCG_COND_GTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6208 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6210 case OPC2_32_RR_MAX_B
:
6211 gen_helper_max_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6213 case OPC2_32_RR_MAX_BU
:
6214 gen_helper_max_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6216 case OPC2_32_RR_MAX_H
:
6217 gen_helper_max_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6219 case OPC2_32_RR_MAX_HU
:
6220 gen_helper_max_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6222 case OPC2_32_RR_MIN
:
6223 tcg_gen_movcond_tl(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6224 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6226 case OPC2_32_RR_MIN_U
:
6227 tcg_gen_movcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6228 cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6230 case OPC2_32_RR_MIN_B
:
6231 gen_helper_min_b(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6233 case OPC2_32_RR_MIN_BU
:
6234 gen_helper_min_bu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6236 case OPC2_32_RR_MIN_H
:
6237 gen_helper_min_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6239 case OPC2_32_RR_MIN_HU
:
6240 gen_helper_min_hu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6242 case OPC2_32_RR_MOV
:
6243 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6245 case OPC2_32_RR_MOV_64
:
6246 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6247 temp
= tcg_temp_new();
6250 tcg_gen_mov_tl(temp
, cpu_gpr_d
[r1
]);
6251 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
6252 tcg_gen_mov_tl(cpu_gpr_d
[r3
+ 1], temp
);
6254 tcg_temp_free(temp
);
6256 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6260 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6263 case OPC2_32_RR_OR_EQ
:
6264 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6265 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6267 case OPC2_32_RR_OR_GE
:
6268 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6269 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6271 case OPC2_32_RR_OR_GE_U
:
6272 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6273 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6275 case OPC2_32_RR_OR_LT
:
6276 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6277 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6279 case OPC2_32_RR_OR_LT_U
:
6280 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6281 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6283 case OPC2_32_RR_OR_NE
:
6284 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6285 cpu_gpr_d
[r2
], &tcg_gen_or_tl
);
6287 case OPC2_32_RR_SAT_B
:
6288 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7f, -0x80);
6290 case OPC2_32_RR_SAT_BU
:
6291 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xff);
6293 case OPC2_32_RR_SAT_H
:
6294 gen_saturate(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0x7fff, -0x8000);
6296 case OPC2_32_RR_SAT_HU
:
6297 gen_saturate_u(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 0xffff);
6299 case OPC2_32_RR_SH_EQ
:
6300 gen_sh_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6303 case OPC2_32_RR_SH_GE
:
6304 gen_sh_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6307 case OPC2_32_RR_SH_GE_U
:
6308 gen_sh_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6311 case OPC2_32_RR_SH_LT
:
6312 gen_sh_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6315 case OPC2_32_RR_SH_LT_U
:
6316 gen_sh_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6319 case OPC2_32_RR_SH_NE
:
6320 gen_sh_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6323 case OPC2_32_RR_SUB
:
6324 gen_sub_d(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6326 case OPC2_32_RR_SUB_B
:
6327 gen_helper_sub_b(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6329 case OPC2_32_RR_SUB_H
:
6330 gen_helper_sub_h(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6332 case OPC2_32_RR_SUBC
:
6333 gen_subc_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6335 case OPC2_32_RR_SUBS
:
6336 gen_subs(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6338 case OPC2_32_RR_SUBS_U
:
6339 gen_subsu(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6341 case OPC2_32_RR_SUBS_H
:
6342 gen_helper_sub_h_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6345 case OPC2_32_RR_SUBS_HU
:
6346 gen_helper_sub_h_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6349 case OPC2_32_RR_SUBX
:
6350 gen_sub_CC(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6352 case OPC2_32_RR_XOR_EQ
:
6353 gen_accumulating_cond(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6354 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6356 case OPC2_32_RR_XOR_GE
:
6357 gen_accumulating_cond(TCG_COND_GE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6358 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6360 case OPC2_32_RR_XOR_GE_U
:
6361 gen_accumulating_cond(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6362 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6364 case OPC2_32_RR_XOR_LT
:
6365 gen_accumulating_cond(TCG_COND_LT
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6366 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6368 case OPC2_32_RR_XOR_LT_U
:
6369 gen_accumulating_cond(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6370 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6372 case OPC2_32_RR_XOR_NE
:
6373 gen_accumulating_cond(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
6374 cpu_gpr_d
[r2
], &tcg_gen_xor_tl
);
6377 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6381 static void decode_rr_logical_shift(CPUTriCoreState
*env
, DisasContext
*ctx
)
6387 r3
= MASK_OP_RR_D(ctx
->opcode
);
6388 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6389 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6391 temp
= tcg_temp_new();
6392 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6395 case OPC2_32_RR_AND
:
6396 tcg_gen_and_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6398 case OPC2_32_RR_ANDN
:
6399 tcg_gen_andc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6401 case OPC2_32_RR_CLO
:
6402 tcg_gen_not_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6403 tcg_gen_clzi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], TARGET_LONG_BITS
);
6405 case OPC2_32_RR_CLO_H
:
6406 gen_helper_clo_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6408 case OPC2_32_RR_CLS
:
6409 tcg_gen_clrsb_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6411 case OPC2_32_RR_CLS_H
:
6412 gen_helper_cls_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6414 case OPC2_32_RR_CLZ
:
6415 tcg_gen_clzi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], TARGET_LONG_BITS
);
6417 case OPC2_32_RR_CLZ_H
:
6418 gen_helper_clz_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6420 case OPC2_32_RR_NAND
:
6421 tcg_gen_nand_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6423 case OPC2_32_RR_NOR
:
6424 tcg_gen_nor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6427 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6429 case OPC2_32_RR_ORN
:
6430 tcg_gen_orc_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6433 gen_helper_sh(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6435 case OPC2_32_RR_SH_H
:
6436 gen_helper_sh_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6438 case OPC2_32_RR_SHA
:
6439 gen_helper_sha(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6441 case OPC2_32_RR_SHA_H
:
6442 gen_helper_sha_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6444 case OPC2_32_RR_SHAS
:
6445 gen_shas(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6447 case OPC2_32_RR_XNOR
:
6448 tcg_gen_eqv_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6450 case OPC2_32_RR_XOR
:
6451 tcg_gen_xor_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6454 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6456 tcg_temp_free(temp
);
6459 static void decode_rr_address(CPUTriCoreState
*env
, DisasContext
*ctx
)
6465 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6466 r3
= MASK_OP_RR_D(ctx
->opcode
);
6467 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6468 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6469 n
= MASK_OP_RR_N(ctx
->opcode
);
6472 case OPC2_32_RR_ADD_A
:
6473 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
6475 case OPC2_32_RR_ADDSC_A
:
6476 temp
= tcg_temp_new();
6477 tcg_gen_shli_tl(temp
, cpu_gpr_d
[r1
], n
);
6478 tcg_gen_add_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
], temp
);
6479 tcg_temp_free(temp
);
6481 case OPC2_32_RR_ADDSC_AT
:
6482 temp
= tcg_temp_new();
6483 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 3);
6484 tcg_gen_add_tl(temp
, cpu_gpr_a
[r2
], temp
);
6485 tcg_gen_andi_tl(cpu_gpr_a
[r3
], temp
, 0xFFFFFFFC);
6486 tcg_temp_free(temp
);
6488 case OPC2_32_RR_EQ_A
:
6489 tcg_gen_setcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6492 case OPC2_32_RR_EQZ
:
6493 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
6495 case OPC2_32_RR_GE_A
:
6496 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6499 case OPC2_32_RR_LT_A
:
6500 tcg_gen_setcond_tl(TCG_COND_LTU
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6503 case OPC2_32_RR_MOV_A
:
6504 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_d
[r2
]);
6506 case OPC2_32_RR_MOV_AA
:
6507 tcg_gen_mov_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r2
]);
6509 case OPC2_32_RR_MOV_D
:
6510 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_a
[r2
]);
6512 case OPC2_32_RR_NE_A
:
6513 tcg_gen_setcond_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
],
6516 case OPC2_32_RR_NEZ_A
:
6517 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_gpr_d
[r3
], cpu_gpr_a
[r1
], 0);
6519 case OPC2_32_RR_SUB_A
:
6520 tcg_gen_sub_tl(cpu_gpr_a
[r3
], cpu_gpr_a
[r1
], cpu_gpr_a
[r2
]);
6523 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6527 static void decode_rr_idirect(CPUTriCoreState
*env
, DisasContext
*ctx
)
6532 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6533 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6537 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6539 case OPC2_32_RR_JLI
:
6540 tcg_gen_movi_tl(cpu_gpr_a
[11], ctx
->next_pc
);
6541 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6543 case OPC2_32_RR_CALLI
:
6544 gen_helper_1arg(call
, ctx
->next_pc
);
6545 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6547 case OPC2_32_RR_FCALLI
:
6548 gen_fcall_save_ctx(ctx
);
6549 tcg_gen_andi_tl(cpu_PC
, cpu_gpr_a
[r1
], ~0x1);
6552 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6555 ctx
->bstate
= BS_BRANCH
;
6558 static void decode_rr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
6563 TCGv temp
, temp2
, temp3
;
6565 op2
= MASK_OP_RR_OP2(ctx
->opcode
);
6566 r3
= MASK_OP_RR_D(ctx
->opcode
);
6567 r2
= MASK_OP_RR_S2(ctx
->opcode
);
6568 r1
= MASK_OP_RR_S1(ctx
->opcode
);
6571 case OPC2_32_RR_BMERGE
:
6572 gen_helper_bmerge(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6574 case OPC2_32_RR_BSPLIT
:
6576 gen_bsplit(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
6578 case OPC2_32_RR_DVINIT_B
:
6580 gen_dvinit_b(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6583 case OPC2_32_RR_DVINIT_BU
:
6584 temp
= tcg_temp_new();
6585 temp2
= tcg_temp_new();
6586 temp3
= tcg_temp_new();
6588 tcg_gen_shri_tl(temp3
, cpu_gpr_d
[r1
], 8);
6590 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6591 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
6592 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6593 tcg_gen_neg_tl(temp
, temp3
);
6594 /* use cpu_PSW_AV to compare against 0 */
6595 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, temp3
, cpu_PSW_AV
,
6597 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
6598 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
6599 temp2
, cpu_gpr_d
[r2
]);
6600 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
6602 /* overflow = (D[b] == 0) */
6603 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6605 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6607 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6609 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 24);
6610 tcg_gen_mov_tl(cpu_gpr_d
[r3
+1], temp3
);
6612 tcg_temp_free(temp
);
6613 tcg_temp_free(temp2
);
6614 tcg_temp_free(temp3
);
6616 case OPC2_32_RR_DVINIT_H
:
6618 gen_dvinit_h(env
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6621 case OPC2_32_RR_DVINIT_HU
:
6622 temp
= tcg_temp_new();
6623 temp2
= tcg_temp_new();
6624 temp3
= tcg_temp_new();
6626 tcg_gen_shri_tl(temp3
, cpu_gpr_d
[r1
], 16);
6628 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6629 if (!tricore_feature(env
, TRICORE_FEATURE_131
)) {
6630 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6631 tcg_gen_neg_tl(temp
, temp3
);
6632 /* use cpu_PSW_AV to compare against 0 */
6633 tcg_gen_movcond_tl(TCG_COND_LT
, temp
, temp3
, cpu_PSW_AV
,
6635 tcg_gen_neg_tl(temp2
, cpu_gpr_d
[r2
]);
6636 tcg_gen_movcond_tl(TCG_COND_LT
, temp2
, cpu_gpr_d
[r2
], cpu_PSW_AV
,
6637 temp2
, cpu_gpr_d
[r2
]);
6638 tcg_gen_setcond_tl(TCG_COND_GE
, cpu_PSW_V
, temp
, temp2
);
6640 /* overflow = (D[b] == 0) */
6641 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6643 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6645 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6647 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 16);
6648 tcg_gen_mov_tl(cpu_gpr_d
[r3
+1], temp3
);
6649 tcg_temp_free(temp
);
6650 tcg_temp_free(temp2
);
6651 tcg_temp_free(temp3
);
6653 case OPC2_32_RR_DVINIT
:
6654 temp
= tcg_temp_new();
6655 temp2
= tcg_temp_new();
6657 /* overflow = ((D[b] == 0) ||
6658 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6659 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp
, cpu_gpr_d
[r2
], 0xffffffff);
6660 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r1
], 0x80000000);
6661 tcg_gen_and_tl(temp
, temp
, temp2
);
6662 tcg_gen_setcondi_tl(TCG_COND_EQ
, temp2
, cpu_gpr_d
[r2
], 0);
6663 tcg_gen_or_tl(cpu_PSW_V
, temp
, temp2
);
6664 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6666 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6668 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6670 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6671 /* sign extend to high reg */
6672 tcg_gen_sari_tl(cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], 31);
6673 tcg_temp_free(temp
);
6674 tcg_temp_free(temp2
);
6676 case OPC2_32_RR_DVINIT_U
:
6677 /* overflow = (D[b] == 0) */
6678 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_PSW_V
, cpu_gpr_d
[r2
], 0);
6679 tcg_gen_shli_tl(cpu_PSW_V
, cpu_PSW_V
, 31);
6681 tcg_gen_or_tl(cpu_PSW_SV
, cpu_PSW_SV
, cpu_PSW_V
);
6683 tcg_gen_movi_tl(cpu_PSW_AV
, 0);
6685 tcg_gen_mov_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6686 /* zero extend to high reg*/
6687 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], 0);
6689 case OPC2_32_RR_PARITY
:
6690 gen_helper_parity(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6692 case OPC2_32_RR_UNPACK
:
6694 gen_unpack(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
6696 case OPC2_32_RR_CRC32
:
6697 if (tricore_feature(env
, TRICORE_FEATURE_161
)) {
6698 gen_helper_crc32(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6700 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6703 case OPC2_32_RR_DIV
:
6704 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6705 GEN_HELPER_RR(divide
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6708 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6711 case OPC2_32_RR_DIV_U
:
6712 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
6713 GEN_HELPER_RR(divide_u
, cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
6714 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6716 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6719 case OPC2_32_RR_MUL_F
:
6720 gen_helper_fmul(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6722 case OPC2_32_RR_DIV_F
:
6723 gen_helper_fdiv(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6725 case OPC2_32_RR_CMP_F
:
6726 gen_helper_fcmp(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6728 case OPC2_32_RR_FTOI
:
6729 gen_helper_ftoi(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6731 case OPC2_32_RR_ITOF
:
6732 gen_helper_itof(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6734 case OPC2_32_RR_FTOUZ
:
6735 gen_helper_ftouz(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
]);
6737 case OPC2_32_RR_UPDFL
:
6738 gen_helper_updfl(cpu_env
, cpu_gpr_d
[r1
]);
6741 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6746 static void decode_rr1_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
6754 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
6755 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
6756 r3
= MASK_OP_RR1_D(ctx
->opcode
);
6757 n
= tcg_const_i32(MASK_OP_RR1_N(ctx
->opcode
));
6758 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
6761 case OPC2_32_RR1_MUL_H_32_LL
:
6762 temp64
= tcg_temp_new_i64();
6764 GEN_HELPER_LL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6765 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6766 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6767 tcg_temp_free_i64(temp64
);
6769 case OPC2_32_RR1_MUL_H_32_LU
:
6770 temp64
= tcg_temp_new_i64();
6772 GEN_HELPER_LU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6773 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6774 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6775 tcg_temp_free_i64(temp64
);
6777 case OPC2_32_RR1_MUL_H_32_UL
:
6778 temp64
= tcg_temp_new_i64();
6780 GEN_HELPER_UL(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6781 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6782 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6783 tcg_temp_free_i64(temp64
);
6785 case OPC2_32_RR1_MUL_H_32_UU
:
6786 temp64
= tcg_temp_new_i64();
6788 GEN_HELPER_UU(mul_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6789 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6790 gen_calc_usb_mul_h(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1]);
6791 tcg_temp_free_i64(temp64
);
6793 case OPC2_32_RR1_MULM_H_64_LL
:
6794 temp64
= tcg_temp_new_i64();
6796 GEN_HELPER_LL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6797 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6799 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6801 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6802 tcg_temp_free_i64(temp64
);
6804 case OPC2_32_RR1_MULM_H_64_LU
:
6805 temp64
= tcg_temp_new_i64();
6807 GEN_HELPER_LU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6808 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6810 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6812 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6813 tcg_temp_free_i64(temp64
);
6815 case OPC2_32_RR1_MULM_H_64_UL
:
6816 temp64
= tcg_temp_new_i64();
6818 GEN_HELPER_UL(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6819 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6821 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6823 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6824 tcg_temp_free_i64(temp64
);
6826 case OPC2_32_RR1_MULM_H_64_UU
:
6827 temp64
= tcg_temp_new_i64();
6829 GEN_HELPER_UU(mulm_h
, temp64
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6830 tcg_gen_extr_i64_i32(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], temp64
);
6832 tcg_gen_movi_tl(cpu_PSW_V
, 0);
6834 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
6835 tcg_temp_free_i64(temp64
);
6838 case OPC2_32_RR1_MULR_H_16_LL
:
6839 GEN_HELPER_LL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6840 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6842 case OPC2_32_RR1_MULR_H_16_LU
:
6843 GEN_HELPER_LU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6844 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6846 case OPC2_32_RR1_MULR_H_16_UL
:
6847 GEN_HELPER_UL(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6848 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6850 case OPC2_32_RR1_MULR_H_16_UU
:
6851 GEN_HELPER_UU(mulr_h
, cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
);
6852 gen_calc_usb_mulr_h(cpu_gpr_d
[r3
]);
6855 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6860 static void decode_rr1_mulq(CPUTriCoreState
*env
, DisasContext
*ctx
)
6868 r1
= MASK_OP_RR1_S1(ctx
->opcode
);
6869 r2
= MASK_OP_RR1_S2(ctx
->opcode
);
6870 r3
= MASK_OP_RR1_D(ctx
->opcode
);
6871 n
= MASK_OP_RR1_N(ctx
->opcode
);
6872 op2
= MASK_OP_RR1_OP2(ctx
->opcode
);
6874 temp
= tcg_temp_new();
6875 temp2
= tcg_temp_new();
6878 case OPC2_32_RR1_MUL_Q_32
:
6879 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 32);
6881 case OPC2_32_RR1_MUL_Q_64
:
6883 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
6886 case OPC2_32_RR1_MUL_Q_32_L
:
6887 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6888 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
6890 case OPC2_32_RR1_MUL_Q_64_L
:
6892 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
6893 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
6895 case OPC2_32_RR1_MUL_Q_32_U
:
6896 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6897 gen_mul_q(cpu_gpr_d
[r3
], temp
, cpu_gpr_d
[r1
], temp
, n
, 16);
6899 case OPC2_32_RR1_MUL_Q_64_U
:
6901 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
6902 gen_mul_q(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
, n
, 0);
6904 case OPC2_32_RR1_MUL_Q_32_LL
:
6905 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6906 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6907 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6909 case OPC2_32_RR1_MUL_Q_32_UU
:
6910 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6911 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6912 gen_mul_q_16(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6914 case OPC2_32_RR1_MULR_Q_32_L
:
6915 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
6916 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
6917 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6919 case OPC2_32_RR1_MULR_Q_32_U
:
6920 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
6921 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
6922 gen_mulr_q(cpu_gpr_d
[r3
], temp
, temp2
, n
);
6925 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6927 tcg_temp_free(temp
);
6928 tcg_temp_free(temp2
);
6932 static void decode_rr2_mul(CPUTriCoreState
*env
, DisasContext
*ctx
)
6937 op2
= MASK_OP_RR2_OP2(ctx
->opcode
);
6938 r1
= MASK_OP_RR2_S1(ctx
->opcode
);
6939 r2
= MASK_OP_RR2_S2(ctx
->opcode
);
6940 r3
= MASK_OP_RR2_D(ctx
->opcode
);
6942 case OPC2_32_RR2_MUL_32
:
6943 gen_mul_i32s(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
6945 case OPC2_32_RR2_MUL_64
:
6947 gen_mul_i64s(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6950 case OPC2_32_RR2_MULS_32
:
6951 gen_helper_mul_ssov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6954 case OPC2_32_RR2_MUL_U_64
:
6956 gen_mul_i64u(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
],
6959 case OPC2_32_RR2_MULS_U_32
:
6960 gen_helper_mul_suov(cpu_gpr_d
[r3
], cpu_env
, cpu_gpr_d
[r1
],
6964 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
6969 static void decode_rrpw_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
6975 op2
= MASK_OP_RRPW_OP2(ctx
->opcode
);
6976 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
6977 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
6978 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
6979 pos
= MASK_OP_RRPW_POS(ctx
->opcode
);
6980 width
= MASK_OP_RRPW_WIDTH(ctx
->opcode
);
6983 case OPC2_32_RRPW_EXTR
:
6984 if (pos
+ width
<= 31) {
6985 /* optimize special cases */
6986 if ((pos
== 0) && (width
== 8)) {
6987 tcg_gen_ext8s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6988 } else if ((pos
== 0) && (width
== 16)) {
6989 tcg_gen_ext16s_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
]);
6991 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], 32 - pos
- width
);
6992 tcg_gen_sari_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], 32 - width
);
6996 case OPC2_32_RRPW_EXTR_U
:
6998 tcg_gen_movi_tl(cpu_gpr_d
[r3
], 0);
7000 tcg_gen_shri_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], pos
);
7001 tcg_gen_andi_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], ~0u >> (32-width
));
7004 case OPC2_32_RRPW_IMASK
:
7006 if (pos
+ width
<= 31) {
7007 tcg_gen_movi_tl(cpu_gpr_d
[r3
+1], ((1u << width
) - 1) << pos
);
7008 tcg_gen_shli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], pos
);
7011 case OPC2_32_RRPW_INSERT
:
7012 if (pos
+ width
<= 31) {
7013 tcg_gen_deposit_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7018 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7023 static void decode_rrr_cond_select(CPUTriCoreState
*env
, DisasContext
*ctx
)
7029 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
7030 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
7031 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
7032 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
7033 r4
= MASK_OP_RRR_D(ctx
->opcode
);
7036 case OPC2_32_RRR_CADD
:
7037 gen_cond_add(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7038 cpu_gpr_d
[r4
], cpu_gpr_d
[r3
]);
7040 case OPC2_32_RRR_CADDN
:
7041 gen_cond_add(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7044 case OPC2_32_RRR_CSUB
:
7045 gen_cond_sub(TCG_COND_NE
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7048 case OPC2_32_RRR_CSUBN
:
7049 gen_cond_sub(TCG_COND_EQ
, cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], cpu_gpr_d
[r4
],
7052 case OPC2_32_RRR_SEL
:
7053 temp
= tcg_const_i32(0);
7054 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
7055 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
7056 tcg_temp_free(temp
);
7058 case OPC2_32_RRR_SELN
:
7059 temp
= tcg_const_i32(0);
7060 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
,
7061 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
]);
7062 tcg_temp_free(temp
);
7065 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7069 static void decode_rrr_divide(CPUTriCoreState
*env
, DisasContext
*ctx
)
7075 op2
= MASK_OP_RRR_OP2(ctx
->opcode
);
7076 r1
= MASK_OP_RRR_S1(ctx
->opcode
);
7077 r2
= MASK_OP_RRR_S2(ctx
->opcode
);
7078 r3
= MASK_OP_RRR_S3(ctx
->opcode
);
7079 r4
= MASK_OP_RRR_D(ctx
->opcode
);
7082 case OPC2_32_RRR_DVADJ
:
7085 GEN_HELPER_RRR(dvadj
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7086 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7088 case OPC2_32_RRR_DVSTEP
:
7091 GEN_HELPER_RRR(dvstep
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7092 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7094 case OPC2_32_RRR_DVSTEP_U
:
7097 GEN_HELPER_RRR(dvstep_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7098 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7100 case OPC2_32_RRR_IXMAX
:
7103 GEN_HELPER_RRR(ixmax
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7104 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7106 case OPC2_32_RRR_IXMAX_U
:
7109 GEN_HELPER_RRR(ixmax_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7110 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7112 case OPC2_32_RRR_IXMIN
:
7115 GEN_HELPER_RRR(ixmin
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7116 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7118 case OPC2_32_RRR_IXMIN_U
:
7121 GEN_HELPER_RRR(ixmin_u
, cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7122 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7124 case OPC2_32_RRR_PACK
:
7126 gen_helper_pack(cpu_gpr_d
[r4
], cpu_PSW_C
, cpu_gpr_d
[r3
],
7127 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
]);
7129 case OPC2_32_RRR_ADD_F
:
7130 gen_helper_fadd(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r3
]);
7132 case OPC2_32_RRR_SUB_F
:
7133 gen_helper_fsub(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
], cpu_gpr_d
[r3
]);
7135 case OPC2_32_RRR_MADD_F
:
7136 gen_helper_fmadd(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7137 cpu_gpr_d
[r2
], cpu_gpr_d
[r3
]);
7139 case OPC2_32_RRR_MSUB_F
:
7140 gen_helper_fmsub(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7141 cpu_gpr_d
[r2
], cpu_gpr_d
[r3
]);
7144 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7149 static void decode_rrr2_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
7152 uint32_t r1
, r2
, r3
, r4
;
7154 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
7155 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
7156 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
7157 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
7158 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
7160 case OPC2_32_RRR2_MADD_32
:
7161 gen_madd32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
7164 case OPC2_32_RRR2_MADD_64
:
7167 gen_madd64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7168 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7170 case OPC2_32_RRR2_MADDS_32
:
7171 gen_helper_madd32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7172 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7174 case OPC2_32_RRR2_MADDS_64
:
7177 gen_madds_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7178 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7180 case OPC2_32_RRR2_MADD_U_64
:
7183 gen_maddu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7184 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7186 case OPC2_32_RRR2_MADDS_U_32
:
7187 gen_helper_madd32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7188 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7190 case OPC2_32_RRR2_MADDS_U_64
:
7193 gen_maddsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7194 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7197 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7201 static void decode_rrr2_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
7204 uint32_t r1
, r2
, r3
, r4
;
7206 op2
= MASK_OP_RRR2_OP2(ctx
->opcode
);
7207 r1
= MASK_OP_RRR2_S1(ctx
->opcode
);
7208 r2
= MASK_OP_RRR2_S2(ctx
->opcode
);
7209 r3
= MASK_OP_RRR2_S3(ctx
->opcode
);
7210 r4
= MASK_OP_RRR2_D(ctx
->opcode
);
7213 case OPC2_32_RRR2_MSUB_32
:
7214 gen_msub32_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r3
],
7217 case OPC2_32_RRR2_MSUB_64
:
7220 gen_msub64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7221 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7223 case OPC2_32_RRR2_MSUBS_32
:
7224 gen_helper_msub32_ssov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7225 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7227 case OPC2_32_RRR2_MSUBS_64
:
7230 gen_msubs_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7231 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7233 case OPC2_32_RRR2_MSUB_U_64
:
7234 gen_msubu64_d(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7235 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7237 case OPC2_32_RRR2_MSUBS_U_32
:
7238 gen_helper_msub32_suov(cpu_gpr_d
[r4
], cpu_env
, cpu_gpr_d
[r1
],
7239 cpu_gpr_d
[r3
], cpu_gpr_d
[r2
]);
7241 case OPC2_32_RRR2_MSUBS_U_64
:
7244 gen_msubsu_64(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r1
],
7245 cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1], cpu_gpr_d
[r2
]);
7248 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7253 static void decode_rrr1_madd(CPUTriCoreState
*env
, DisasContext
*ctx
)
7256 uint32_t r1
, r2
, r3
, r4
, n
;
7258 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7259 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7260 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7261 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7262 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7263 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7266 case OPC2_32_RRR1_MADD_H_LL
:
7269 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7270 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7272 case OPC2_32_RRR1_MADD_H_LU
:
7275 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7276 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7278 case OPC2_32_RRR1_MADD_H_UL
:
7281 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7282 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7284 case OPC2_32_RRR1_MADD_H_UU
:
7287 gen_madd_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7288 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7290 case OPC2_32_RRR1_MADDS_H_LL
:
7293 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7294 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7296 case OPC2_32_RRR1_MADDS_H_LU
:
7299 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7300 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7302 case OPC2_32_RRR1_MADDS_H_UL
:
7305 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7306 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7308 case OPC2_32_RRR1_MADDS_H_UU
:
7311 gen_madds_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7312 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7314 case OPC2_32_RRR1_MADDM_H_LL
:
7317 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7318 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7320 case OPC2_32_RRR1_MADDM_H_LU
:
7323 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7324 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7326 case OPC2_32_RRR1_MADDM_H_UL
:
7329 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7330 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7332 case OPC2_32_RRR1_MADDM_H_UU
:
7335 gen_maddm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7336 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7338 case OPC2_32_RRR1_MADDMS_H_LL
:
7341 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7342 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7344 case OPC2_32_RRR1_MADDMS_H_LU
:
7347 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7348 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7350 case OPC2_32_RRR1_MADDMS_H_UL
:
7353 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7354 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7356 case OPC2_32_RRR1_MADDMS_H_UU
:
7359 gen_maddms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7360 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7362 case OPC2_32_RRR1_MADDR_H_LL
:
7363 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7364 cpu_gpr_d
[r2
], n
, MODE_LL
);
7366 case OPC2_32_RRR1_MADDR_H_LU
:
7367 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7368 cpu_gpr_d
[r2
], n
, MODE_LU
);
7370 case OPC2_32_RRR1_MADDR_H_UL
:
7371 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7372 cpu_gpr_d
[r2
], n
, MODE_UL
);
7374 case OPC2_32_RRR1_MADDR_H_UU
:
7375 gen_maddr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7376 cpu_gpr_d
[r2
], n
, MODE_UU
);
7378 case OPC2_32_RRR1_MADDRS_H_LL
:
7379 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7380 cpu_gpr_d
[r2
], n
, MODE_LL
);
7382 case OPC2_32_RRR1_MADDRS_H_LU
:
7383 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7384 cpu_gpr_d
[r2
], n
, MODE_LU
);
7386 case OPC2_32_RRR1_MADDRS_H_UL
:
7387 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7388 cpu_gpr_d
[r2
], n
, MODE_UL
);
7390 case OPC2_32_RRR1_MADDRS_H_UU
:
7391 gen_maddr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7392 cpu_gpr_d
[r2
], n
, MODE_UU
);
7395 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7399 static void decode_rrr1_maddq_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7402 uint32_t r1
, r2
, r3
, r4
, n
;
7405 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7406 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7407 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7408 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7409 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7410 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7412 temp
= tcg_const_i32(n
);
7413 temp2
= tcg_temp_new();
7416 case OPC2_32_RRR1_MADD_Q_32
:
7417 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7418 cpu_gpr_d
[r2
], n
, 32, env
);
7420 case OPC2_32_RRR1_MADD_Q_64
:
7423 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7424 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7427 case OPC2_32_RRR1_MADD_Q_32_L
:
7428 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7429 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7432 case OPC2_32_RRR1_MADD_Q_64_L
:
7435 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7436 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7437 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7440 case OPC2_32_RRR1_MADD_Q_32_U
:
7441 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7442 gen_madd32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7445 case OPC2_32_RRR1_MADD_Q_64_U
:
7448 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7449 gen_madd64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7450 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7453 case OPC2_32_RRR1_MADD_Q_32_LL
:
7454 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7455 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7456 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7458 case OPC2_32_RRR1_MADD_Q_64_LL
:
7461 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7462 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7463 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7464 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7466 case OPC2_32_RRR1_MADD_Q_32_UU
:
7467 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7468 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7469 gen_m16add32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7471 case OPC2_32_RRR1_MADD_Q_64_UU
:
7474 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7475 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7476 gen_m16add64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7477 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7479 case OPC2_32_RRR1_MADDS_Q_32
:
7480 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7481 cpu_gpr_d
[r2
], n
, 32);
7483 case OPC2_32_RRR1_MADDS_Q_64
:
7486 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7487 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7490 case OPC2_32_RRR1_MADDS_Q_32_L
:
7491 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7492 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7495 case OPC2_32_RRR1_MADDS_Q_64_L
:
7498 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7499 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7500 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7503 case OPC2_32_RRR1_MADDS_Q_32_U
:
7504 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7505 gen_madds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7508 case OPC2_32_RRR1_MADDS_Q_64_U
:
7511 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7512 gen_madds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7513 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7516 case OPC2_32_RRR1_MADDS_Q_32_LL
:
7517 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7518 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7519 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7521 case OPC2_32_RRR1_MADDS_Q_64_LL
:
7524 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7525 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7526 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7527 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7529 case OPC2_32_RRR1_MADDS_Q_32_UU
:
7530 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7531 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7532 gen_m16adds32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7534 case OPC2_32_RRR1_MADDS_Q_64_UU
:
7537 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7538 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7539 gen_m16adds64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7540 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7542 case OPC2_32_RRR1_MADDR_H_64_UL
:
7544 gen_maddr64_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
7545 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
7547 case OPC2_32_RRR1_MADDRS_H_64_UL
:
7549 gen_maddr64s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
7550 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
7552 case OPC2_32_RRR1_MADDR_Q_32_LL
:
7553 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7554 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7555 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7557 case OPC2_32_RRR1_MADDR_Q_32_UU
:
7558 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7559 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7560 gen_maddr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7562 case OPC2_32_RRR1_MADDRS_Q_32_LL
:
7563 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7564 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7565 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7567 case OPC2_32_RRR1_MADDRS_Q_32_UU
:
7568 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7569 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7570 gen_maddrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7573 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7575 tcg_temp_free(temp
);
7576 tcg_temp_free(temp2
);
7579 static void decode_rrr1_maddsu_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7582 uint32_t r1
, r2
, r3
, r4
, n
;
7584 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7585 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7586 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7587 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7588 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7589 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7592 case OPC2_32_RRR1_MADDSU_H_32_LL
:
7595 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7596 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7598 case OPC2_32_RRR1_MADDSU_H_32_LU
:
7601 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7602 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7604 case OPC2_32_RRR1_MADDSU_H_32_UL
:
7607 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7608 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7610 case OPC2_32_RRR1_MADDSU_H_32_UU
:
7613 gen_maddsu_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7614 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7616 case OPC2_32_RRR1_MADDSUS_H_32_LL
:
7619 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7620 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7623 case OPC2_32_RRR1_MADDSUS_H_32_LU
:
7626 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7627 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7630 case OPC2_32_RRR1_MADDSUS_H_32_UL
:
7633 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7634 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7637 case OPC2_32_RRR1_MADDSUS_H_32_UU
:
7640 gen_maddsus_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7641 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7644 case OPC2_32_RRR1_MADDSUM_H_64_LL
:
7647 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7648 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7651 case OPC2_32_RRR1_MADDSUM_H_64_LU
:
7654 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7655 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7658 case OPC2_32_RRR1_MADDSUM_H_64_UL
:
7661 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7662 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7665 case OPC2_32_RRR1_MADDSUM_H_64_UU
:
7668 gen_maddsum_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7669 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7672 case OPC2_32_RRR1_MADDSUMS_H_64_LL
:
7675 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7676 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7679 case OPC2_32_RRR1_MADDSUMS_H_64_LU
:
7682 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7683 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7686 case OPC2_32_RRR1_MADDSUMS_H_64_UL
:
7689 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7690 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7693 case OPC2_32_RRR1_MADDSUMS_H_64_UU
:
7696 gen_maddsums_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7697 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7700 case OPC2_32_RRR1_MADDSUR_H_16_LL
:
7701 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7702 cpu_gpr_d
[r2
], n
, MODE_LL
);
7704 case OPC2_32_RRR1_MADDSUR_H_16_LU
:
7705 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7706 cpu_gpr_d
[r2
], n
, MODE_LU
);
7708 case OPC2_32_RRR1_MADDSUR_H_16_UL
:
7709 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7710 cpu_gpr_d
[r2
], n
, MODE_UL
);
7712 case OPC2_32_RRR1_MADDSUR_H_16_UU
:
7713 gen_maddsur32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7714 cpu_gpr_d
[r2
], n
, MODE_UU
);
7716 case OPC2_32_RRR1_MADDSURS_H_16_LL
:
7717 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7718 cpu_gpr_d
[r2
], n
, MODE_LL
);
7720 case OPC2_32_RRR1_MADDSURS_H_16_LU
:
7721 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7722 cpu_gpr_d
[r2
], n
, MODE_LU
);
7724 case OPC2_32_RRR1_MADDSURS_H_16_UL
:
7725 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7726 cpu_gpr_d
[r2
], n
, MODE_UL
);
7728 case OPC2_32_RRR1_MADDSURS_H_16_UU
:
7729 gen_maddsur32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7730 cpu_gpr_d
[r2
], n
, MODE_UU
);
7733 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7737 static void decode_rrr1_msub(CPUTriCoreState
*env
, DisasContext
*ctx
)
7740 uint32_t r1
, r2
, r3
, r4
, n
;
7742 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7743 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7744 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7745 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7746 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7747 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7750 case OPC2_32_RRR1_MSUB_H_LL
:
7753 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7754 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7756 case OPC2_32_RRR1_MSUB_H_LU
:
7759 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7760 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7762 case OPC2_32_RRR1_MSUB_H_UL
:
7765 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7766 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7768 case OPC2_32_RRR1_MSUB_H_UU
:
7771 gen_msub_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7772 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7774 case OPC2_32_RRR1_MSUBS_H_LL
:
7777 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7778 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7780 case OPC2_32_RRR1_MSUBS_H_LU
:
7783 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7784 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7786 case OPC2_32_RRR1_MSUBS_H_UL
:
7789 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7790 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7792 case OPC2_32_RRR1_MSUBS_H_UU
:
7795 gen_msubs_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7796 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7798 case OPC2_32_RRR1_MSUBM_H_LL
:
7801 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7802 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7804 case OPC2_32_RRR1_MSUBM_H_LU
:
7807 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7808 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7810 case OPC2_32_RRR1_MSUBM_H_UL
:
7813 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7814 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7816 case OPC2_32_RRR1_MSUBM_H_UU
:
7819 gen_msubm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7820 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7822 case OPC2_32_RRR1_MSUBMS_H_LL
:
7825 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7826 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
7828 case OPC2_32_RRR1_MSUBMS_H_LU
:
7831 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7832 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
7834 case OPC2_32_RRR1_MSUBMS_H_UL
:
7837 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7838 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
7840 case OPC2_32_RRR1_MSUBMS_H_UU
:
7843 gen_msubms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7844 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
7846 case OPC2_32_RRR1_MSUBR_H_LL
:
7847 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7848 cpu_gpr_d
[r2
], n
, MODE_LL
);
7850 case OPC2_32_RRR1_MSUBR_H_LU
:
7851 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7852 cpu_gpr_d
[r2
], n
, MODE_LU
);
7854 case OPC2_32_RRR1_MSUBR_H_UL
:
7855 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7856 cpu_gpr_d
[r2
], n
, MODE_UL
);
7858 case OPC2_32_RRR1_MSUBR_H_UU
:
7859 gen_msubr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7860 cpu_gpr_d
[r2
], n
, MODE_UU
);
7862 case OPC2_32_RRR1_MSUBRS_H_LL
:
7863 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7864 cpu_gpr_d
[r2
], n
, MODE_LL
);
7866 case OPC2_32_RRR1_MSUBRS_H_LU
:
7867 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7868 cpu_gpr_d
[r2
], n
, MODE_LU
);
7870 case OPC2_32_RRR1_MSUBRS_H_UL
:
7871 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7872 cpu_gpr_d
[r2
], n
, MODE_UL
);
7874 case OPC2_32_RRR1_MSUBRS_H_UU
:
7875 gen_msubr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7876 cpu_gpr_d
[r2
], n
, MODE_UU
);
7879 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
7883 static void decode_rrr1_msubq_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
7886 uint32_t r1
, r2
, r3
, r4
, n
;
7889 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
7890 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
7891 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
7892 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
7893 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
7894 n
= MASK_OP_RRR1_N(ctx
->opcode
);
7896 temp
= tcg_const_i32(n
);
7897 temp2
= tcg_temp_new();
7900 case OPC2_32_RRR1_MSUB_Q_32
:
7901 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7902 cpu_gpr_d
[r2
], n
, 32, env
);
7904 case OPC2_32_RRR1_MSUB_Q_64
:
7907 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7908 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7911 case OPC2_32_RRR1_MSUB_Q_32_L
:
7912 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7913 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7916 case OPC2_32_RRR1_MSUB_Q_64_L
:
7919 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7920 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7921 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7924 case OPC2_32_RRR1_MSUB_Q_32_U
:
7925 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7926 gen_msub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7929 case OPC2_32_RRR1_MSUB_Q_64_U
:
7932 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7933 gen_msub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7934 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7937 case OPC2_32_RRR1_MSUB_Q_32_LL
:
7938 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7939 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7940 gen_m16sub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7942 case OPC2_32_RRR1_MSUB_Q_64_LL
:
7945 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
7946 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
7947 gen_m16sub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7948 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7950 case OPC2_32_RRR1_MSUB_Q_32_UU
:
7951 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7952 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7953 gen_m16sub32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
7955 case OPC2_32_RRR1_MSUB_Q_64_UU
:
7958 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
7959 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
7960 gen_m16sub64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7961 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
7963 case OPC2_32_RRR1_MSUBS_Q_32
:
7964 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7965 cpu_gpr_d
[r2
], n
, 32);
7967 case OPC2_32_RRR1_MSUBS_Q_64
:
7970 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7971 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
7974 case OPC2_32_RRR1_MSUBS_Q_32_L
:
7975 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7976 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7979 case OPC2_32_RRR1_MSUBS_Q_64_L
:
7982 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r2
]);
7983 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7984 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
7987 case OPC2_32_RRR1_MSUBS_Q_32_U
:
7988 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7989 gen_msubs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
7992 case OPC2_32_RRR1_MSUBS_Q_64_U
:
7995 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r2
], 16);
7996 gen_msubs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
7997 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], temp
,
8000 case OPC2_32_RRR1_MSUBS_Q_32_LL
:
8001 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8002 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8003 gen_m16subs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8005 case OPC2_32_RRR1_MSUBS_Q_64_LL
:
8008 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8009 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8010 gen_m16subs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8011 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
8013 case OPC2_32_RRR1_MSUBS_Q_32_UU
:
8014 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8015 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8016 gen_m16subs32_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8018 case OPC2_32_RRR1_MSUBS_Q_64_UU
:
8021 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8022 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8023 gen_m16subs64_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8024 cpu_gpr_d
[r3
+1], temp
, temp2
, n
);
8026 case OPC2_32_RRR1_MSUBR_H_64_UL
:
8028 gen_msubr64_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
8029 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
8031 case OPC2_32_RRR1_MSUBRS_H_64_UL
:
8033 gen_msubr64s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r3
+1],
8034 cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, 2);
8036 case OPC2_32_RRR1_MSUBR_Q_32_LL
:
8037 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8038 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8039 gen_msubr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8041 case OPC2_32_RRR1_MSUBR_Q_32_UU
:
8042 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8043 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8044 gen_msubr_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8046 case OPC2_32_RRR1_MSUBRS_Q_32_LL
:
8047 tcg_gen_ext16s_tl(temp
, cpu_gpr_d
[r1
]);
8048 tcg_gen_ext16s_tl(temp2
, cpu_gpr_d
[r2
]);
8049 gen_msubrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8051 case OPC2_32_RRR1_MSUBRS_Q_32_UU
:
8052 tcg_gen_sari_tl(temp
, cpu_gpr_d
[r1
], 16);
8053 tcg_gen_sari_tl(temp2
, cpu_gpr_d
[r2
], 16);
8054 gen_msubrs_q(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], temp
, temp2
, n
);
8057 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8059 tcg_temp_free(temp
);
8060 tcg_temp_free(temp2
);
8063 static void decode_rrr1_msubad_h(CPUTriCoreState
*env
, DisasContext
*ctx
)
8066 uint32_t r1
, r2
, r3
, r4
, n
;
8068 op2
= MASK_OP_RRR1_OP2(ctx
->opcode
);
8069 r1
= MASK_OP_RRR1_S1(ctx
->opcode
);
8070 r2
= MASK_OP_RRR1_S2(ctx
->opcode
);
8071 r3
= MASK_OP_RRR1_S3(ctx
->opcode
);
8072 r4
= MASK_OP_RRR1_D(ctx
->opcode
);
8073 n
= MASK_OP_RRR1_N(ctx
->opcode
);
8076 case OPC2_32_RRR1_MSUBAD_H_32_LL
:
8079 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8080 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LL
);
8082 case OPC2_32_RRR1_MSUBAD_H_32_LU
:
8085 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8086 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_LU
);
8088 case OPC2_32_RRR1_MSUBAD_H_32_UL
:
8091 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8092 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UL
);
8094 case OPC2_32_RRR1_MSUBAD_H_32_UU
:
8097 gen_msubad_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8098 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], n
, MODE_UU
);
8100 case OPC2_32_RRR1_MSUBADS_H_32_LL
:
8103 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8104 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8107 case OPC2_32_RRR1_MSUBADS_H_32_LU
:
8110 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8111 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8114 case OPC2_32_RRR1_MSUBADS_H_32_UL
:
8117 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8118 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8121 case OPC2_32_RRR1_MSUBADS_H_32_UU
:
8124 gen_msubads_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8125 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8128 case OPC2_32_RRR1_MSUBADM_H_64_LL
:
8131 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8132 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8135 case OPC2_32_RRR1_MSUBADM_H_64_LU
:
8138 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8139 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8142 case OPC2_32_RRR1_MSUBADM_H_64_UL
:
8145 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8146 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8149 case OPC2_32_RRR1_MSUBADM_H_64_UU
:
8152 gen_msubadm_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8153 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8156 case OPC2_32_RRR1_MSUBADMS_H_64_LL
:
8159 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8160 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8163 case OPC2_32_RRR1_MSUBADMS_H_64_LU
:
8166 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8167 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8170 case OPC2_32_RRR1_MSUBADMS_H_64_UL
:
8173 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8174 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8177 case OPC2_32_RRR1_MSUBADMS_H_64_UU
:
8180 gen_msubadms_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
+1], cpu_gpr_d
[r3
],
8181 cpu_gpr_d
[r3
+1], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
],
8184 case OPC2_32_RRR1_MSUBADR_H_16_LL
:
8185 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8186 cpu_gpr_d
[r2
], n
, MODE_LL
);
8188 case OPC2_32_RRR1_MSUBADR_H_16_LU
:
8189 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8190 cpu_gpr_d
[r2
], n
, MODE_LU
);
8192 case OPC2_32_RRR1_MSUBADR_H_16_UL
:
8193 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8194 cpu_gpr_d
[r2
], n
, MODE_UL
);
8196 case OPC2_32_RRR1_MSUBADR_H_16_UU
:
8197 gen_msubadr32_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8198 cpu_gpr_d
[r2
], n
, MODE_UU
);
8200 case OPC2_32_RRR1_MSUBADRS_H_16_LL
:
8201 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8202 cpu_gpr_d
[r2
], n
, MODE_LL
);
8204 case OPC2_32_RRR1_MSUBADRS_H_16_LU
:
8205 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8206 cpu_gpr_d
[r2
], n
, MODE_LU
);
8208 case OPC2_32_RRR1_MSUBADRS_H_16_UL
:
8209 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8210 cpu_gpr_d
[r2
], n
, MODE_UL
);
8212 case OPC2_32_RRR1_MSUBADRS_H_16_UU
:
8213 gen_msubadr32s_h(cpu_gpr_d
[r4
], cpu_gpr_d
[r3
], cpu_gpr_d
[r1
],
8214 cpu_gpr_d
[r2
], n
, MODE_UU
);
8217 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8222 static void decode_rrrr_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
8226 TCGv tmp_width
, tmp_pos
;
8228 r1
= MASK_OP_RRRR_S1(ctx
->opcode
);
8229 r2
= MASK_OP_RRRR_S2(ctx
->opcode
);
8230 r3
= MASK_OP_RRRR_S3(ctx
->opcode
);
8231 r4
= MASK_OP_RRRR_D(ctx
->opcode
);
8232 op2
= MASK_OP_RRRR_OP2(ctx
->opcode
);
8234 tmp_pos
= tcg_temp_new();
8235 tmp_width
= tcg_temp_new();
8238 case OPC2_32_RRRR_DEXTR
:
8239 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8241 tcg_gen_rotl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], tmp_pos
);
8243 tcg_gen_shl_tl(tmp_width
, cpu_gpr_d
[r1
], tmp_pos
);
8244 tcg_gen_subfi_tl(tmp_pos
, 32, tmp_pos
);
8245 tcg_gen_shr_tl(tmp_pos
, cpu_gpr_d
[r2
], tmp_pos
);
8246 tcg_gen_or_tl(cpu_gpr_d
[r4
], tmp_width
, tmp_pos
);
8249 case OPC2_32_RRRR_EXTR
:
8250 case OPC2_32_RRRR_EXTR_U
:
8252 tcg_gen_andi_tl(tmp_width
, cpu_gpr_d
[r3
+1], 0x1f);
8253 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8254 tcg_gen_add_tl(tmp_pos
, tmp_pos
, tmp_width
);
8255 tcg_gen_subfi_tl(tmp_pos
, 32, tmp_pos
);
8256 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], tmp_pos
);
8257 tcg_gen_subfi_tl(tmp_width
, 32, tmp_width
);
8258 if (op2
== OPC2_32_RRRR_EXTR
) {
8259 tcg_gen_sar_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], tmp_width
);
8261 tcg_gen_shr_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], tmp_width
);
8264 case OPC2_32_RRRR_INSERT
:
8266 tcg_gen_andi_tl(tmp_width
, cpu_gpr_d
[r3
+1], 0x1f);
8267 tcg_gen_andi_tl(tmp_pos
, cpu_gpr_d
[r3
], 0x1f);
8268 gen_insert(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], tmp_width
,
8272 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8274 tcg_temp_free(tmp_pos
);
8275 tcg_temp_free(tmp_width
);
8279 static void decode_rrrw_extract_insert(CPUTriCoreState
*env
, DisasContext
*ctx
)
8287 op2
= MASK_OP_RRRW_OP2(ctx
->opcode
);
8288 r1
= MASK_OP_RRRW_S1(ctx
->opcode
);
8289 r2
= MASK_OP_RRRW_S2(ctx
->opcode
);
8290 r3
= MASK_OP_RRRW_S3(ctx
->opcode
);
8291 r4
= MASK_OP_RRRW_D(ctx
->opcode
);
8292 width
= MASK_OP_RRRW_WIDTH(ctx
->opcode
);
8294 temp
= tcg_temp_new();
8297 case OPC2_32_RRRW_EXTR
:
8298 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8299 tcg_gen_addi_tl(temp
, temp
, width
);
8300 tcg_gen_subfi_tl(temp
, 32, temp
);
8301 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], temp
);
8302 tcg_gen_sari_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], 32 - width
);
8304 case OPC2_32_RRRW_EXTR_U
:
8306 tcg_gen_movi_tl(cpu_gpr_d
[r4
], 0);
8308 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8309 tcg_gen_shr_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], temp
);
8310 tcg_gen_andi_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r4
], ~0u >> (32-width
));
8313 case OPC2_32_RRRW_IMASK
:
8314 temp2
= tcg_temp_new();
8316 tcg_gen_andi_tl(temp
, cpu_gpr_d
[r3
], 0x1f);
8317 tcg_gen_movi_tl(temp2
, (1 << width
) - 1);
8318 tcg_gen_shl_tl(temp2
, temp2
, temp
);
8319 tcg_gen_shl_tl(cpu_gpr_d
[r4
], cpu_gpr_d
[r2
], temp
);
8320 tcg_gen_mov_tl(cpu_gpr_d
[r4
+1], temp2
);
8322 tcg_temp_free(temp2
);
8324 case OPC2_32_RRRW_INSERT
:
8325 temp2
= tcg_temp_new();
8327 tcg_gen_movi_tl(temp
, width
);
8328 tcg_gen_andi_tl(temp2
, cpu_gpr_d
[r3
], 0x1f);
8329 gen_insert(cpu_gpr_d
[r4
], cpu_gpr_d
[r1
], cpu_gpr_d
[r2
], temp
, temp2
);
8331 tcg_temp_free(temp2
);
8334 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8336 tcg_temp_free(temp
);
8340 static void decode_sys_interrupts(CPUTriCoreState
*env
, DisasContext
*ctx
)
8347 op2
= MASK_OP_SYS_OP2(ctx
->opcode
);
8348 r1
= MASK_OP_SYS_S1D(ctx
->opcode
);
8351 case OPC2_32_SYS_DEBUG
:
8352 /* raise EXCP_DEBUG */
8354 case OPC2_32_SYS_DISABLE
:
8355 tcg_gen_andi_tl(cpu_ICR
, cpu_ICR
, ~MASK_ICR_IE
);
8357 case OPC2_32_SYS_DSYNC
:
8359 case OPC2_32_SYS_ENABLE
:
8360 tcg_gen_ori_tl(cpu_ICR
, cpu_ICR
, MASK_ICR_IE
);
8362 case OPC2_32_SYS_ISYNC
:
8364 case OPC2_32_SYS_NOP
:
8366 case OPC2_32_SYS_RET
:
8367 gen_compute_branch(ctx
, op2
, 0, 0, 0, 0);
8369 case OPC2_32_SYS_FRET
:
8372 case OPC2_32_SYS_RFE
:
8373 gen_helper_rfe(cpu_env
);
8375 ctx
->bstate
= BS_BRANCH
;
8377 case OPC2_32_SYS_RFM
:
8378 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
) {
8379 tmp
= tcg_temp_new();
8380 l1
= gen_new_label();
8382 tcg_gen_ld32u_tl(tmp
, cpu_env
, offsetof(CPUTriCoreState
, DBGSR
));
8383 tcg_gen_andi_tl(tmp
, tmp
, MASK_DBGSR_DE
);
8384 tcg_gen_brcondi_tl(TCG_COND_NE
, tmp
, 1, l1
);
8385 gen_helper_rfm(cpu_env
);
8388 ctx
->bstate
= BS_BRANCH
;
8391 /* generate privilege trap */
8394 case OPC2_32_SYS_RSLCX
:
8395 gen_helper_rslcx(cpu_env
);
8397 case OPC2_32_SYS_SVLCX
:
8398 gen_helper_svlcx(cpu_env
);
8400 case OPC2_32_SYS_RESTORE
:
8401 if (tricore_feature(env
, TRICORE_FEATURE_16
)) {
8402 if ((ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_SM
||
8403 (ctx
->hflags
& TRICORE_HFLAG_KUU
) == TRICORE_HFLAG_UM1
) {
8404 tcg_gen_deposit_tl(cpu_ICR
, cpu_ICR
, cpu_gpr_d
[r1
], 8, 1);
8405 } /* else raise privilege trap */
8407 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8410 case OPC2_32_SYS_TRAPSV
:
8411 l1
= gen_new_label();
8412 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_PSW_SV
, 0, l1
);
8413 generate_trap(ctx
, TRAPC_ASSERT
, TIN5_SOVF
);
8416 case OPC2_32_SYS_TRAPV
:
8417 l1
= gen_new_label();
8418 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_PSW_V
, 0, l1
);
8419 generate_trap(ctx
, TRAPC_ASSERT
, TIN5_OVF
);
8423 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8427 static void decode_32Bit_opc(CPUTriCoreState
*env
, DisasContext
*ctx
)
8431 int32_t address
, const16
;
8434 TCGv temp
, temp2
, temp3
;
8436 op1
= MASK_OP_MAJOR(ctx
->opcode
);
8438 /* handle JNZ.T opcode only being 7 bit long */
8439 if (unlikely((op1
& 0x7f) == OPCM_32_BRN_JTT
)) {
8440 op1
= OPCM_32_BRN_JTT
;
8445 case OPCM_32_ABS_LDW
:
8446 decode_abs_ldw(env
, ctx
);
8448 case OPCM_32_ABS_LDB
:
8449 decode_abs_ldb(env
, ctx
);
8451 case OPCM_32_ABS_LDMST_SWAP
:
8452 decode_abs_ldst_swap(env
, ctx
);
8454 case OPCM_32_ABS_LDST_CONTEXT
:
8455 decode_abs_ldst_context(env
, ctx
);
8457 case OPCM_32_ABS_STORE
:
8458 decode_abs_store(env
, ctx
);
8460 case OPCM_32_ABS_STOREB_H
:
8461 decode_abs_storeb_h(env
, ctx
);
8463 case OPC1_32_ABS_STOREQ
:
8464 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8465 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8466 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8467 temp2
= tcg_temp_new();
8469 tcg_gen_shri_tl(temp2
, cpu_gpr_d
[r1
], 16);
8470 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_LEUW
);
8472 tcg_temp_free(temp2
);
8473 tcg_temp_free(temp
);
8475 case OPC1_32_ABS_LD_Q
:
8476 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8477 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8478 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8480 tcg_gen_qemu_ld_tl(cpu_gpr_d
[r1
], temp
, ctx
->mem_idx
, MO_LEUW
);
8481 tcg_gen_shli_tl(cpu_gpr_d
[r1
], cpu_gpr_d
[r1
], 16);
8483 tcg_temp_free(temp
);
8485 case OPC1_32_ABS_LEA
:
8486 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8487 r1
= MASK_OP_ABS_S1D(ctx
->opcode
);
8488 tcg_gen_movi_tl(cpu_gpr_a
[r1
], EA_ABS_FORMAT(address
));
8491 case OPC1_32_ABSB_ST_T
:
8492 address
= MASK_OP_ABS_OFF18(ctx
->opcode
);
8493 b
= MASK_OP_ABSB_B(ctx
->opcode
);
8494 bpos
= MASK_OP_ABSB_BPOS(ctx
->opcode
);
8496 temp
= tcg_const_i32(EA_ABS_FORMAT(address
));
8497 temp2
= tcg_temp_new();
8499 tcg_gen_qemu_ld_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
8500 tcg_gen_andi_tl(temp2
, temp2
, ~(0x1u
<< bpos
));
8501 tcg_gen_ori_tl(temp2
, temp2
, (b
<< bpos
));
8502 tcg_gen_qemu_st_tl(temp2
, temp
, ctx
->mem_idx
, MO_UB
);
8504 tcg_temp_free(temp
);
8505 tcg_temp_free(temp2
);
8508 case OPC1_32_B_CALL
:
8509 case OPC1_32_B_CALLA
:
8510 case OPC1_32_B_FCALL
:
8511 case OPC1_32_B_FCALLA
:
8516 address
= MASK_OP_B_DISP24_SEXT(ctx
->opcode
);
8517 gen_compute_branch(ctx
, op1
, 0, 0, 0, address
);
8520 case OPCM_32_BIT_ANDACC
:
8521 decode_bit_andacc(env
, ctx
);
8523 case OPCM_32_BIT_LOGICAL_T1
:
8524 decode_bit_logical_t(env
, ctx
);
8526 case OPCM_32_BIT_INSERT
:
8527 decode_bit_insert(env
, ctx
);
8529 case OPCM_32_BIT_LOGICAL_T2
:
8530 decode_bit_logical_t2(env
, ctx
);
8532 case OPCM_32_BIT_ORAND
:
8533 decode_bit_orand(env
, ctx
);
8535 case OPCM_32_BIT_SH_LOGIC1
:
8536 decode_bit_sh_logic1(env
, ctx
);
8538 case OPCM_32_BIT_SH_LOGIC2
:
8539 decode_bit_sh_logic2(env
, ctx
);
8542 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE
:
8543 decode_bo_addrmode_post_pre_base(env
, ctx
);
8545 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR
:
8546 decode_bo_addrmode_bitreverse_circular(env
, ctx
);
8548 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE
:
8549 decode_bo_addrmode_ld_post_pre_base(env
, ctx
);
8551 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR
:
8552 decode_bo_addrmode_ld_bitreverse_circular(env
, ctx
);
8554 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE
:
8555 decode_bo_addrmode_stctx_post_pre_base(env
, ctx
);
8557 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR
:
8558 decode_bo_addrmode_ldmst_bitreverse_circular(env
, ctx
);
8561 case OPC1_32_BOL_LD_A_LONGOFF
:
8562 case OPC1_32_BOL_LD_W_LONGOFF
:
8563 case OPC1_32_BOL_LEA_LONGOFF
:
8564 case OPC1_32_BOL_ST_W_LONGOFF
:
8565 case OPC1_32_BOL_ST_A_LONGOFF
:
8566 case OPC1_32_BOL_LD_B_LONGOFF
:
8567 case OPC1_32_BOL_LD_BU_LONGOFF
:
8568 case OPC1_32_BOL_LD_H_LONGOFF
:
8569 case OPC1_32_BOL_LD_HU_LONGOFF
:
8570 case OPC1_32_BOL_ST_B_LONGOFF
:
8571 case OPC1_32_BOL_ST_H_LONGOFF
:
8572 decode_bol_opc(env
, ctx
, op1
);
8575 case OPCM_32_BRC_EQ_NEQ
:
8576 case OPCM_32_BRC_GE
:
8577 case OPCM_32_BRC_JLT
:
8578 case OPCM_32_BRC_JNE
:
8579 const4
= MASK_OP_BRC_CONST4_SEXT(ctx
->opcode
);
8580 address
= MASK_OP_BRC_DISP15_SEXT(ctx
->opcode
);
8581 r1
= MASK_OP_BRC_S1(ctx
->opcode
);
8582 gen_compute_branch(ctx
, op1
, r1
, 0, const4
, address
);
8585 case OPCM_32_BRN_JTT
:
8586 address
= MASK_OP_BRN_DISP15_SEXT(ctx
->opcode
);
8587 r1
= MASK_OP_BRN_S1(ctx
->opcode
);
8588 gen_compute_branch(ctx
, op1
, r1
, 0, 0, address
);
8591 case OPCM_32_BRR_EQ_NEQ
:
8592 case OPCM_32_BRR_ADDR_EQ_NEQ
:
8593 case OPCM_32_BRR_GE
:
8594 case OPCM_32_BRR_JLT
:
8595 case OPCM_32_BRR_JNE
:
8596 case OPCM_32_BRR_JNZ
:
8597 case OPCM_32_BRR_LOOP
:
8598 address
= MASK_OP_BRR_DISP15_SEXT(ctx
->opcode
);
8599 r2
= MASK_OP_BRR_S2(ctx
->opcode
);
8600 r1
= MASK_OP_BRR_S1(ctx
->opcode
);
8601 gen_compute_branch(ctx
, op1
, r1
, r2
, 0, address
);
8604 case OPCM_32_RC_LOGICAL_SHIFT
:
8605 decode_rc_logical_shift(env
, ctx
);
8607 case OPCM_32_RC_ACCUMULATOR
:
8608 decode_rc_accumulator(env
, ctx
);
8610 case OPCM_32_RC_SERVICEROUTINE
:
8611 decode_rc_serviceroutine(env
, ctx
);
8613 case OPCM_32_RC_MUL
:
8614 decode_rc_mul(env
, ctx
);
8617 case OPCM_32_RCPW_MASK_INSERT
:
8618 decode_rcpw_insert(env
, ctx
);
8621 case OPC1_32_RCRR_INSERT
:
8622 r1
= MASK_OP_RCRR_S1(ctx
->opcode
);
8623 r2
= MASK_OP_RCRR_S3(ctx
->opcode
);
8624 r3
= MASK_OP_RCRR_D(ctx
->opcode
);
8625 const16
= MASK_OP_RCRR_CONST4(ctx
->opcode
);
8626 temp
= tcg_const_i32(const16
);
8627 temp2
= tcg_temp_new(); /* width*/
8628 temp3
= tcg_temp_new(); /* pos */
8632 tcg_gen_andi_tl(temp2
, cpu_gpr_d
[r3
+1], 0x1f);
8633 tcg_gen_andi_tl(temp3
, cpu_gpr_d
[r3
], 0x1f);
8635 gen_insert(cpu_gpr_d
[r2
], cpu_gpr_d
[r1
], temp
, temp2
, temp3
);
8637 tcg_temp_free(temp
);
8638 tcg_temp_free(temp2
);
8639 tcg_temp_free(temp3
);
8642 case OPCM_32_RCRW_MASK_INSERT
:
8643 decode_rcrw_insert(env
, ctx
);
8646 case OPCM_32_RCR_COND_SELECT
:
8647 decode_rcr_cond_select(env
, ctx
);
8649 case OPCM_32_RCR_MADD
:
8650 decode_rcr_madd(env
, ctx
);
8652 case OPCM_32_RCR_MSUB
:
8653 decode_rcr_msub(env
, ctx
);
8656 case OPC1_32_RLC_ADDI
:
8657 case OPC1_32_RLC_ADDIH
:
8658 case OPC1_32_RLC_ADDIH_A
:
8659 case OPC1_32_RLC_MFCR
:
8660 case OPC1_32_RLC_MOV
:
8661 case OPC1_32_RLC_MOV_64
:
8662 case OPC1_32_RLC_MOV_U
:
8663 case OPC1_32_RLC_MOV_H
:
8664 case OPC1_32_RLC_MOVH_A
:
8665 case OPC1_32_RLC_MTCR
:
8666 decode_rlc_opc(env
, ctx
, op1
);
8669 case OPCM_32_RR_ACCUMULATOR
:
8670 decode_rr_accumulator(env
, ctx
);
8672 case OPCM_32_RR_LOGICAL_SHIFT
:
8673 decode_rr_logical_shift(env
, ctx
);
8675 case OPCM_32_RR_ADDRESS
:
8676 decode_rr_address(env
, ctx
);
8678 case OPCM_32_RR_IDIRECT
:
8679 decode_rr_idirect(env
, ctx
);
8681 case OPCM_32_RR_DIVIDE
:
8682 decode_rr_divide(env
, ctx
);
8685 case OPCM_32_RR1_MUL
:
8686 decode_rr1_mul(env
, ctx
);
8688 case OPCM_32_RR1_MULQ
:
8689 decode_rr1_mulq(env
, ctx
);
8692 case OPCM_32_RR2_MUL
:
8693 decode_rr2_mul(env
, ctx
);
8696 case OPCM_32_RRPW_EXTRACT_INSERT
:
8697 decode_rrpw_extract_insert(env
, ctx
);
8699 case OPC1_32_RRPW_DEXTR
:
8700 r1
= MASK_OP_RRPW_S1(ctx
->opcode
);
8701 r2
= MASK_OP_RRPW_S2(ctx
->opcode
);
8702 r3
= MASK_OP_RRPW_D(ctx
->opcode
);
8703 const16
= MASK_OP_RRPW_POS(ctx
->opcode
);
8705 tcg_gen_rotli_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r1
], const16
);
8707 temp
= tcg_temp_new();
8708 tcg_gen_shli_tl(temp
, cpu_gpr_d
[r1
], const16
);
8709 tcg_gen_shri_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r2
], 32 - const16
);
8710 tcg_gen_or_tl(cpu_gpr_d
[r3
], cpu_gpr_d
[r3
], temp
);
8711 tcg_temp_free(temp
);
8715 case OPCM_32_RRR_COND_SELECT
:
8716 decode_rrr_cond_select(env
, ctx
);
8718 case OPCM_32_RRR_DIVIDE
:
8719 decode_rrr_divide(env
, ctx
);
8722 case OPCM_32_RRR2_MADD
:
8723 decode_rrr2_madd(env
, ctx
);
8725 case OPCM_32_RRR2_MSUB
:
8726 decode_rrr2_msub(env
, ctx
);
8729 case OPCM_32_RRR1_MADD
:
8730 decode_rrr1_madd(env
, ctx
);
8732 case OPCM_32_RRR1_MADDQ_H
:
8733 decode_rrr1_maddq_h(env
, ctx
);
8735 case OPCM_32_RRR1_MADDSU_H
:
8736 decode_rrr1_maddsu_h(env
, ctx
);
8738 case OPCM_32_RRR1_MSUB_H
:
8739 decode_rrr1_msub(env
, ctx
);
8741 case OPCM_32_RRR1_MSUB_Q
:
8742 decode_rrr1_msubq_h(env
, ctx
);
8744 case OPCM_32_RRR1_MSUBAD_H
:
8745 decode_rrr1_msubad_h(env
, ctx
);
8748 case OPCM_32_RRRR_EXTRACT_INSERT
:
8749 decode_rrrr_extract_insert(env
, ctx
);
8752 case OPCM_32_RRRW_EXTRACT_INSERT
:
8753 decode_rrrw_extract_insert(env
, ctx
);
8756 case OPCM_32_SYS_INTERRUPTS
:
8757 decode_sys_interrupts(env
, ctx
);
8759 case OPC1_32_SYS_RSTV
:
8760 tcg_gen_movi_tl(cpu_PSW_V
, 0);
8761 tcg_gen_mov_tl(cpu_PSW_SV
, cpu_PSW_V
);
8762 tcg_gen_mov_tl(cpu_PSW_AV
, cpu_PSW_V
);
8763 tcg_gen_mov_tl(cpu_PSW_SAV
, cpu_PSW_V
);
8766 generate_trap(ctx
, TRAPC_INSN_ERR
, TIN2_IOPC
);
8770 static void decode_opc(CPUTriCoreState
*env
, DisasContext
*ctx
, int *is_branch
)
8772 /* 16-Bit Instruction */
8773 if ((ctx
->opcode
& 0x1) == 0) {
8774 ctx
->next_pc
= ctx
->pc
+ 2;
8775 decode_16Bit_opc(env
, ctx
);
8776 /* 32-Bit Instruction */
8778 ctx
->next_pc
= ctx
->pc
+ 4;
8779 decode_32Bit_opc(env
, ctx
);
8783 void gen_intermediate_code(CPUState
*cs
, struct TranslationBlock
*tb
)
8785 CPUTriCoreState
*env
= cs
->env_ptr
;
8787 target_ulong pc_start
;
8788 int num_insns
, max_insns
;
8791 max_insns
= tb_cflags(tb
) & CF_COUNT_MASK
;
8792 if (max_insns
== 0) {
8793 max_insns
= CF_COUNT_MASK
;
8798 if (max_insns
> TCG_MAX_INSNS
) {
8799 max_insns
= TCG_MAX_INSNS
;
8806 ctx
.singlestep_enabled
= cs
->singlestep_enabled
;
8807 ctx
.bstate
= BS_NONE
;
8808 ctx
.mem_idx
= cpu_mmu_index(env
, false);
8810 tcg_clear_temp_count();
8812 while (ctx
.bstate
== BS_NONE
) {
8813 tcg_gen_insn_start(ctx
.pc
);
8816 ctx
.opcode
= cpu_ldl_code(env
, ctx
.pc
);
8817 decode_opc(env
, &ctx
, 0);
8819 if (num_insns
>= max_insns
|| tcg_op_buf_full()) {
8820 gen_save_pc(ctx
.next_pc
);
8824 ctx
.pc
= ctx
.next_pc
;
8827 gen_tb_end(tb
, num_insns
);
8828 tb
->size
= ctx
.pc
- pc_start
;
8829 tb
->icount
= num_insns
;
8831 if (tcg_check_temp_count()) {
8832 printf("LEAK at %08x\n", env
->PC
);
8836 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)
8837 && qemu_log_in_addr_range(pc_start
)) {
8839 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8840 log_target_disas(cs
, pc_start
, ctx
.pc
- pc_start
);
8848 restore_state_to_opc(CPUTriCoreState
*env
, TranslationBlock
*tb
,
8859 void cpu_state_reset(CPUTriCoreState
*env
)
8861 /* Reset Regs to Default Value */
8866 static void tricore_tcg_init_csfr(void)
8868 cpu_PCXI
= tcg_global_mem_new(cpu_env
,
8869 offsetof(CPUTriCoreState
, PCXI
), "PCXI");
8870 cpu_PSW
= tcg_global_mem_new(cpu_env
,
8871 offsetof(CPUTriCoreState
, PSW
), "PSW");
8872 cpu_PC
= tcg_global_mem_new(cpu_env
,
8873 offsetof(CPUTriCoreState
, PC
), "PC");
8874 cpu_ICR
= tcg_global_mem_new(cpu_env
,
8875 offsetof(CPUTriCoreState
, ICR
), "ICR");
8878 void tricore_tcg_init(void)
8883 for (i
= 0 ; i
< 16 ; i
++) {
8884 cpu_gpr_a
[i
] = tcg_global_mem_new(cpu_env
,
8885 offsetof(CPUTriCoreState
, gpr_a
[i
]),
8888 for (i
= 0 ; i
< 16 ; i
++) {
8889 cpu_gpr_d
[i
] = tcg_global_mem_new(cpu_env
,
8890 offsetof(CPUTriCoreState
, gpr_d
[i
]),
8893 tricore_tcg_init_csfr();
8894 /* init PSW flag cache */
8895 cpu_PSW_C
= tcg_global_mem_new(cpu_env
,
8896 offsetof(CPUTriCoreState
, PSW_USB_C
),
8898 cpu_PSW_V
= tcg_global_mem_new(cpu_env
,
8899 offsetof(CPUTriCoreState
, PSW_USB_V
),
8901 cpu_PSW_SV
= tcg_global_mem_new(cpu_env
,
8902 offsetof(CPUTriCoreState
, PSW_USB_SV
),
8904 cpu_PSW_AV
= tcg_global_mem_new(cpu_env
,
8905 offsetof(CPUTriCoreState
, PSW_USB_AV
),
8907 cpu_PSW_SAV
= tcg_global_mem_new(cpu_env
,
8908 offsetof(CPUTriCoreState
, PSW_USB_SAV
),