4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
26 #define TARGET_LONG_BITS 32
30 #define SH_CPU_SH7750 (1 << 0)
31 #define SH_CPU_SH7750S (1 << 1)
32 #define SH_CPU_SH7750R (1 << 2)
33 #define SH_CPU_SH7751 (1 << 3)
34 #define SH_CPU_SH7751R (1 << 4)
35 #define SH_CPU_SH7785 (1 << 5)
36 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
37 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
39 #define CPUArchState struct CPUSH4State
41 #include "exec/cpu-defs.h"
43 #include "fpu/softfloat.h"
45 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */
47 #define TARGET_PHYS_ADDR_SPACE_BITS 32
48 #ifdef CONFIG_USER_ONLY
49 # define TARGET_VIRT_ADDR_SPACE_BITS 31
51 # define TARGET_VIRT_ADDR_SPACE_BITS 32
67 #define FPSCR_MASK (0x003fffff)
68 #define FPSCR_FR (1 << 21)
69 #define FPSCR_SZ (1 << 20)
70 #define FPSCR_PR (1 << 19)
71 #define FPSCR_DN (1 << 18)
72 #define FPSCR_CAUSE_MASK (0x3f << 12)
73 #define FPSCR_CAUSE_SHIFT (12)
74 #define FPSCR_CAUSE_E (1 << 17)
75 #define FPSCR_CAUSE_V (1 << 16)
76 #define FPSCR_CAUSE_Z (1 << 15)
77 #define FPSCR_CAUSE_O (1 << 14)
78 #define FPSCR_CAUSE_U (1 << 13)
79 #define FPSCR_CAUSE_I (1 << 12)
80 #define FPSCR_ENABLE_MASK (0x1f << 7)
81 #define FPSCR_ENABLE_SHIFT (7)
82 #define FPSCR_ENABLE_V (1 << 11)
83 #define FPSCR_ENABLE_Z (1 << 10)
84 #define FPSCR_ENABLE_O (1 << 9)
85 #define FPSCR_ENABLE_U (1 << 8)
86 #define FPSCR_ENABLE_I (1 << 7)
87 #define FPSCR_FLAG_MASK (0x1f << 2)
88 #define FPSCR_FLAG_SHIFT (2)
89 #define FPSCR_FLAG_V (1 << 6)
90 #define FPSCR_FLAG_Z (1 << 5)
91 #define FPSCR_FLAG_O (1 << 4)
92 #define FPSCR_FLAG_U (1 << 3)
93 #define FPSCR_FLAG_I (1 << 2)
94 #define FPSCR_RM_MASK (0x03 << 0)
95 #define FPSCR_RM_NEAREST (0 << 0)
96 #define FPSCR_RM_ZERO (1 << 0)
98 #define DELAY_SLOT_MASK 0x7
99 #define DELAY_SLOT (1 << 0)
100 #define DELAY_SLOT_CONDITIONAL (1 << 1)
101 #define DELAY_SLOT_RTE (1 << 2)
103 #define TB_FLAG_PENDING_MOVCA (1 << 3)
106 #ifdef CONFIG_USER_ONLY
107 #define GUSA_EXCLUSIVE (1 << 12)
108 #define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
110 /* Provide dummy versions of the above to allow tests against tbflags
111 to be elided while avoiding ifdefs. */
112 #define GUSA_EXCLUSIVE 0
116 #define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
118 typedef struct tlb_t
{
119 uint32_t vpn
; /* virtual page number */
120 uint32_t ppn
; /* physical page number */
121 uint32_t size
; /* mapped page size in bytes */
122 uint8_t asid
; /* address space identifier */
123 uint8_t v
:1; /* validity */
124 uint8_t sz
:2; /* page size */
125 uint8_t sh
:1; /* share status */
126 uint8_t c
:1; /* cacheability */
127 uint8_t pr
:2; /* protection key */
128 uint8_t d
:1; /* dirty */
129 uint8_t wt
:1; /* write through */
130 uint8_t sa
:3; /* space attribute (PCMCIA) */
131 uint8_t tc
:1; /* timing control */
137 #define NB_MMU_MODES 2
138 #define TARGET_INSN_START_EXTRA_WORDS 1
142 SH_FEATURE_BCR3_AND_BCR4
= 2,
145 typedef struct memory_content
{
148 struct memory_content
*next
;
151 typedef struct CPUSH4State
{
152 uint32_t flags
; /* general execution flags */
153 uint32_t gregs
[24]; /* general registers */
154 float32 fregs
[32]; /* floating point registers */
155 uint32_t sr
; /* status register (with T split out) */
156 uint32_t sr_m
; /* M bit of status register */
157 uint32_t sr_q
; /* Q bit of status register */
158 uint32_t sr_t
; /* T bit of status register */
159 uint32_t ssr
; /* saved status register */
160 uint32_t spc
; /* saved program counter */
161 uint32_t gbr
; /* global base register */
162 uint32_t vbr
; /* vector base register */
163 uint32_t sgr
; /* saved global register 15 */
164 uint32_t dbr
; /* debug base register */
165 uint32_t pc
; /* program counter */
166 uint32_t delayed_pc
; /* target of delayed branch */
167 uint32_t delayed_cond
; /* condition of delayed branch */
168 uint32_t mach
; /* multiply and accumulate high */
169 uint32_t macl
; /* multiply and accumulate low */
170 uint32_t pr
; /* procedure register */
171 uint32_t fpscr
; /* floating point status/control register */
172 uint32_t fpul
; /* floating point communication register */
174 /* float point status register */
175 float_status fp_status
;
177 /* Those belong to the specific unit (SH7750) but are handled here */
178 uint32_t mmucr
; /* MMU control register */
179 uint32_t pteh
; /* page table entry high register */
180 uint32_t ptel
; /* page table entry low register */
181 uint32_t ptea
; /* page table entry assistance register */
182 uint32_t ttb
; /* tranlation table base register */
183 uint32_t tea
; /* TLB exception address register */
184 uint32_t tra
; /* TRAPA exception register */
185 uint32_t expevt
; /* exception event register */
186 uint32_t intevt
; /* interrupt event register */
188 tlb_t itlb
[ITLB_SIZE
]; /* instruction translation table */
189 tlb_t utlb
[UTLB_SIZE
]; /* unified translation table */
191 /* LDST = LOCK_ADDR != -1. */
195 /* Fields up to this point are cleared by a CPU reset */
196 struct {} end_reset_fields
;
200 /* Fields from here on are preserved over CPU reset. */
201 int id
; /* CPU model */
203 /* The features that we should emulate. See sh_features above. */
207 int in_sleep
; /* SR_BL ignored during sleep */
208 memory_content
*movcal_backup
;
209 memory_content
**movcal_backup_tail
;
226 static inline SuperHCPU
*sh_env_get_cpu(CPUSH4State
*env
)
228 return container_of(env
, SuperHCPU
, env
);
231 #define ENV_GET_CPU(e) CPU(sh_env_get_cpu(e))
233 #define ENV_OFFSET offsetof(SuperHCPU, env)
235 void superh_cpu_do_interrupt(CPUState
*cpu
);
236 bool superh_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
237 void superh_cpu_dump_state(CPUState
*cpu
, FILE *f
,
238 fprintf_function cpu_fprintf
, int flags
);
239 hwaddr
superh_cpu_get_phys_page_debug(CPUState
*cpu
, vaddr addr
);
240 int superh_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
241 int superh_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
242 void superh_cpu_do_unaligned_access(CPUState
*cpu
, vaddr addr
,
243 MMUAccessType access_type
,
244 int mmu_idx
, uintptr_t retaddr
);
246 void sh4_translate_init(void);
247 int cpu_sh4_signal_handler(int host_signum
, void *pinfo
,
249 int superh_cpu_handle_mmu_fault(CPUState
*cpu
, vaddr address
, int rw
,
252 void sh4_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
253 #if !defined(CONFIG_USER_ONLY)
254 void cpu_sh4_invalidate_tlb(CPUSH4State
*s
);
255 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State
*s
,
257 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State
*s
, hwaddr addr
,
259 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State
*s
,
261 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State
*s
, hwaddr addr
,
263 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State
*s
,
265 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, hwaddr addr
,
267 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State
*s
,
269 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State
*s
, hwaddr addr
,
273 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
);
275 void cpu_load_tlb(CPUSH4State
* env
);
277 #define cpu_init(cpu_model) cpu_generic_init(TYPE_SUPERH_CPU, cpu_model)
279 #define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU
280 #define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX
282 #define cpu_signal_handler cpu_sh4_signal_handler
283 #define cpu_list sh4_cpu_list
285 /* MMU modes definitions */
286 #define MMU_MODE0_SUFFIX _kernel
287 #define MMU_MODE1_SUFFIX _user
288 #define MMU_USER_IDX 1
289 static inline int cpu_mmu_index (CPUSH4State
*env
, bool ifetch
)
291 /* The instruction in a RTE delay slot is fetched in privileged
292 mode, but executed in user mode. */
293 if (ifetch
&& (env
->flags
& DELAY_SLOT_RTE
)) {
296 return (env
->sr
& (1u << SR_MD
)) == 0 ? 1 : 0;
300 #include "exec/cpu-all.h"
302 /* Memory access type */
308 /* Type of instruction */
313 /* MMU control register */
314 #define MMUCR 0x1F000010
315 #define MMUCR_AT (1<<0)
316 #define MMUCR_TI (1<<2)
317 #define MMUCR_SV (1<<8)
318 #define MMUCR_URC_BITS (6)
319 #define MMUCR_URC_OFFSET (10)
320 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS)
321 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET)
322 static inline int cpu_mmucr_urc (uint32_t mmucr
)
324 return ((mmucr
& MMUCR_URC_MASK
) >> MMUCR_URC_OFFSET
);
327 /* PTEH : Page Translation Entry High register */
328 #define PTEH_ASID_BITS (8)
329 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS)
330 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1)
331 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
332 #define PTEH_VPN_BITS (22)
333 #define PTEH_VPN_OFFSET (10)
334 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS)
335 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET)
336 static inline int cpu_pteh_vpn (uint32_t pteh
)
338 return ((pteh
& PTEH_VPN_MASK
) >> PTEH_VPN_OFFSET
);
341 /* PTEL : Page Translation Entry Low register */
342 #define PTEL_V (1 << 8)
343 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8)
344 #define PTEL_C (1 << 3)
345 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3)
346 #define PTEL_D (1 << 2)
347 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2)
348 #define PTEL_SH (1 << 1)
349 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1)
350 #define PTEL_WT (1 << 0)
351 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
353 #define PTEL_SZ_HIGH_OFFSET (7)
354 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET)
355 #define PTEL_SZ_LOW_OFFSET (4)
356 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET)
357 static inline int cpu_ptel_sz (uint32_t ptel
)
360 sz
= (ptel
& PTEL_SZ_HIGH
) >> PTEL_SZ_HIGH_OFFSET
;
362 sz
|= (ptel
& PTEL_SZ_LOW
) >> PTEL_SZ_LOW_OFFSET
;
366 #define PTEL_PPN_BITS (19)
367 #define PTEL_PPN_OFFSET (10)
368 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS)
369 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET)
370 static inline int cpu_ptel_ppn (uint32_t ptel
)
372 return ((ptel
& PTEL_PPN_MASK
) >> PTEL_PPN_OFFSET
);
375 #define PTEL_PR_BITS (2)
376 #define PTEL_PR_OFFSET (5)
377 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS)
378 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET)
379 static inline int cpu_ptel_pr (uint32_t ptel
)
381 return ((ptel
& PTEL_PR_MASK
) >> PTEL_PR_OFFSET
);
384 /* PTEA : Page Translation Entry Assistance register */
385 #define PTEA_SA_BITS (3)
386 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS)
387 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1)
388 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
389 #define PTEA_TC (1 << 3)
390 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3)
392 static inline target_ulong
cpu_read_sr(CPUSH4State
*env
)
394 return env
->sr
| (env
->sr_m
<< SR_M
) |
395 (env
->sr_q
<< SR_Q
) |
399 static inline void cpu_write_sr(CPUSH4State
*env
, target_ulong sr
)
401 env
->sr_m
= (sr
>> SR_M
) & 1;
402 env
->sr_q
= (sr
>> SR_Q
) & 1;
403 env
->sr_t
= (sr
>> SR_T
) & 1;
404 env
->sr
= sr
& ~((1u << SR_M
) | (1u << SR_Q
) | (1u << SR_T
));
407 static inline void cpu_get_tb_cpu_state(CPUSH4State
*env
, target_ulong
*pc
,
408 target_ulong
*cs_base
, uint32_t *flags
)
411 /* For a gUSA region, notice the end of the region. */
412 *cs_base
= env
->flags
& GUSA_MASK
? env
->gregs
[0] : 0;
413 *flags
= env
->flags
/* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
414 | (env
->fpscr
& (FPSCR_FR
| FPSCR_SZ
| FPSCR_PR
)) /* Bits 19-21 */
415 | (env
->sr
& ((1u << SR_MD
) | (1u << SR_RB
))) /* Bits 29-30 */
416 | (env
->sr
& (1u << SR_FD
)) /* Bit 15 */
417 | (env
->movcal_backup
? TB_FLAG_PENDING_MOVCA
: 0); /* Bit 3 */
420 #endif /* SH4_CPU_H */