target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27
  28 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     AVRCPU *cpu = AVR_CPU(cs);
  31
  32     cpu->env.pc_w = value / 2; /* internally PC points to words */
  33 }
  34
  35 static vaddr avr_cpu_get_pc(CPUState *cs)
  36 {
  37     AVRCPU *cpu = AVR_CPU(cs);
  38
  39     return cpu->env.pc_w * 2;
  40 }
  41
  42 static bool avr_cpu_has_work(CPUState *cs)
  43 {
  44     AVRCPU *cpu = AVR_CPU(cs);
  45     CPUAVRState *env = &cpu->env;
  46
  47     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  48             && cpu_interrupts_enabled(env);
  49 }
  50
  51 static void avr_cpu_synchronize_from_tb(CPUState *cs,
  52                                         const TranslationBlock *tb)
  53 {
  54     AVRCPU *cpu = AVR_CPU(cs);
  55     CPUAVRState *env = &cpu->env;
  56
  57     env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
  58 }
  59
  60 static void avr_restore_state_to_opc(CPUState *cs,
  61                                      const TranslationBlock *tb,
  62                                      const uint64_t *data)
  63 {
  64     AVRCPU *cpu = AVR_CPU(cs);
  65     CPUAVRState *env = &cpu->env;
  66
  67     env->pc_w = data[0];
  68 }
  69
  70 static void avr_cpu_reset_hold(Object *obj)
  71 {
  72     CPUState *cs = CPU(obj);
  73     AVRCPU *cpu = AVR_CPU(cs);
  74     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  75     CPUAVRState *env = &cpu->env;
  76
  77     if (mcc->parent_phases.hold) {
  78         mcc->parent_phases.hold(obj);
  79     }
  80
  81     env->pc_w = 0;
  82     env->sregI = 1;
  83     env->sregC = 0;
  84     env->sregZ = 0;
  85     env->sregN = 0;
  86     env->sregV = 0;
  87     env->sregS = 0;
  88     env->sregH = 0;
  89     env->sregT = 0;
  90
  91     env->rampD = 0;
  92     env->rampX = 0;
  93     env->rampY = 0;
  94     env->rampZ = 0;
  95     env->eind = 0;
  96     env->sp = 0;
  97
  98     env->skip = 0;
  99
 100     memset(env->r, 0, sizeof(env->r));
 101 }
 102
 103 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 104 {
 105     info->mach = bfd_arch_avr;
 106     info->print_insn = avr_print_insn;
 107 }
 108
 109 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
 110 {
 111     CPUState *cs = CPU(dev);
 112     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
 113     Error *local_err = NULL;
 114
 115     cpu_exec_realizefn(cs, &local_err);
 116     if (local_err != NULL) {
 117         error_propagate(errp, local_err);
 118         return;
 119     }
 120     qemu_init_vcpu(cs);
 121     cpu_reset(cs);
 122
 123     mcc->parent_realize(dev, errp);
 124 }
 125
 126 static void avr_cpu_set_int(void *opaque, int irq, int level)
 127 {
 128     AVRCPU *cpu = opaque;
 129     CPUAVRState *env = &cpu->env;
 130     CPUState *cs = CPU(cpu);
 131     uint64_t mask = (1ull << irq);
 132
 133     if (level) {
 134         env->intsrc |= mask;
 135         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 136     } else {
 137         env->intsrc &= ~mask;
 138         if (env->intsrc == 0) {
 139             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 140         }
 141     }
 142 }
 143
 144 static void avr_cpu_initfn(Object *obj)
 145 {
 146     AVRCPU *cpu = AVR_CPU(obj);
 147
 148     cpu_set_cpustate_pointers(cpu);
 149
 150     /* Set the number of interrupts supported by the CPU. */
 151     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 152                       sizeof(cpu->env.intsrc) * 8);
 153 }
 154
 155 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 156 {
 157     ObjectClass *oc;
 158
 159     oc = object_class_by_name(cpu_model);
 160     if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
 161         object_class_is_abstract(oc)) {
 162         oc = NULL;
 163     }
 164     return oc;
 165 }
 166
 167 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 168 {
 169     AVRCPU *cpu = AVR_CPU(cs);
 170     CPUAVRState *env = &cpu->env;
 171     int i;
 172
 173     qemu_fprintf(f, "\n");
 174     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
 175     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 176     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 177     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 178     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 179     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 180     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 181     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 182     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 183     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 184     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 185                  env->sregI ? 'I' : '-',
 186                  env->sregT ? 'T' : '-',
 187                  env->sregH ? 'H' : '-',
 188                  env->sregS ? 'S' : '-',
 189                  env->sregV ? 'V' : '-',
 190                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 191                  env->sregZ ? 'Z' : '-',
 192                  env->sregC ? 'I' : '-');
 193     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 194
 195     qemu_fprintf(f, "\n");
 196     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 197         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 198
 199         if ((i % 8) == 7) {
 200             qemu_fprintf(f, "\n");
 201         }
 202     }
 203     qemu_fprintf(f, "\n");
 204 }
 205
 206 #include "hw/core/sysemu-cpu-ops.h"
 207
 208 static const struct SysemuCPUOps avr_sysemu_ops = {
 209     .get_phys_page_debug = avr_cpu_get_phys_page_debug,
 210 };
 211
 212 #include "hw/core/tcg-cpu-ops.h"
 213
 214 static const struct TCGCPUOps avr_tcg_ops = {
 215     .initialize = avr_cpu_tcg_init,
 216     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
 217     .restore_state_to_opc = avr_restore_state_to_opc,
 218     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
 219     .tlb_fill = avr_cpu_tlb_fill,
 220     .do_interrupt = avr_cpu_do_interrupt,
 221 };
 222
 223 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 224 {
 225     DeviceClass *dc = DEVICE_CLASS(oc);
 226     CPUClass *cc = CPU_CLASS(oc);
 227     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 228     ResettableClass *rc = RESETTABLE_CLASS(oc);
 229
 230     device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
 231
 232     resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
 233                                        &mcc->parent_phases);
 234
 235     cc->class_by_name = avr_cpu_class_by_name;
 236
 237     cc->has_work = avr_cpu_has_work;
 238     cc->dump_state = avr_cpu_dump_state;
 239     cc->set_pc = avr_cpu_set_pc;
 240     cc->get_pc = avr_cpu_get_pc;
 241     dc->vmsd = &vms_avr_cpu;
 242     cc->sysemu_ops = &avr_sysemu_ops;
 243     cc->disas_set_info = avr_cpu_disas_set_info;
 244     cc->gdb_read_register = avr_cpu_gdb_read_register;
 245     cc->gdb_write_register = avr_cpu_gdb_write_register;
 246     cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
 247     cc->gdb_num_core_regs = 35;
 248     cc->gdb_core_xml_file = "avr-cpu.xml";
 249     cc->tcg_ops = &avr_tcg_ops;
 250 }
 251
 252 /*
 253  * Setting features of AVR core type avr5
 254  * --------------------------------------
 255  *
 256  * This type of AVR core is present in the following AVR MCUs:
 257  *
 258  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
 259  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
 260  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
 261  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
 262  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
 263  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
 264  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
 265  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
 266  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
 267  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
 268  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
 269  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
 270  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
 271  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
 272  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
 273  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
 274  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
 275  */
 276 static void avr_avr5_initfn(Object *obj)
 277 {
 278     AVRCPU *cpu = AVR_CPU(obj);
 279     CPUAVRState *env = &cpu->env;
 280
 281     set_avr_feature(env, AVR_FEATURE_LPM);
 282     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 283     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 284     set_avr_feature(env, AVR_FEATURE_SRAM);
 285     set_avr_feature(env, AVR_FEATURE_BREAK);
 286
 287     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 288     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 289     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 290     set_avr_feature(env, AVR_FEATURE_LPMX);
 291     set_avr_feature(env, AVR_FEATURE_MOVW);
 292     set_avr_feature(env, AVR_FEATURE_MUL);
 293 }
 294
 295 /*
 296  * Setting features of AVR core type avr51
 297  * --------------------------------------
 298  *
 299  * This type of AVR core is present in the following AVR MCUs:
 300  *
 301  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
 302  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
 303  * at90usb1287
 304  */
 305 static void avr_avr51_initfn(Object *obj)
 306 {
 307     AVRCPU *cpu = AVR_CPU(obj);
 308     CPUAVRState *env = &cpu->env;
 309
 310     set_avr_feature(env, AVR_FEATURE_LPM);
 311     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 312     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 313     set_avr_feature(env, AVR_FEATURE_SRAM);
 314     set_avr_feature(env, AVR_FEATURE_BREAK);
 315
 316     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 317     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 318     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 319     set_avr_feature(env, AVR_FEATURE_ELPMX);
 320     set_avr_feature(env, AVR_FEATURE_ELPM);
 321     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 322     set_avr_feature(env, AVR_FEATURE_LPMX);
 323     set_avr_feature(env, AVR_FEATURE_MOVW);
 324     set_avr_feature(env, AVR_FEATURE_MUL);
 325 }
 326
 327 /*
 328  * Setting features of AVR core type avr6
 329  * --------------------------------------
 330  *
 331  * This type of AVR core is present in the following AVR MCUs:
 332  *
 333  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
 334  */
 335 static void avr_avr6_initfn(Object *obj)
 336 {
 337     AVRCPU *cpu = AVR_CPU(obj);
 338     CPUAVRState *env = &cpu->env;
 339
 340     set_avr_feature(env, AVR_FEATURE_LPM);
 341     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 342     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 343     set_avr_feature(env, AVR_FEATURE_SRAM);
 344     set_avr_feature(env, AVR_FEATURE_BREAK);
 345
 346     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
 347     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 348     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 349     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
 350     set_avr_feature(env, AVR_FEATURE_ELPMX);
 351     set_avr_feature(env, AVR_FEATURE_ELPM);
 352     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 353     set_avr_feature(env, AVR_FEATURE_LPMX);
 354     set_avr_feature(env, AVR_FEATURE_MOVW);
 355     set_avr_feature(env, AVR_FEATURE_MUL);
 356 }
 357
 358 typedef struct AVRCPUInfo {
 359     const char *name;
 360     void (*initfn)(Object *obj);
 361 } AVRCPUInfo;
 362
 363
 364 static void avr_cpu_list_entry(gpointer data, gpointer user_data)
 365 {
 366     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 367
 368     qemu_printf("%s\n", typename);
 369 }
 370
 371 void avr_cpu_list(void)
 372 {
 373     GSList *list;
 374     list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
 375     g_slist_foreach(list, avr_cpu_list_entry, NULL);
 376     g_slist_free(list);
 377 }
 378
 379 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
 380     { \
 381         .parent = TYPE_AVR_CPU, \
 382         .instance_init = initfn, \
 383         .name = AVR_CPU_TYPE_NAME(model), \
 384     }
 385
 386 static const TypeInfo avr_cpu_type_info[] = {
 387     {
 388         .name = TYPE_AVR_CPU,
 389         .parent = TYPE_CPU,
 390         .instance_size = sizeof(AVRCPU),
 391         .instance_init = avr_cpu_initfn,
 392         .class_size = sizeof(AVRCPUClass),
 393         .class_init = avr_cpu_class_init,
 394         .abstract = true,
 395     },
 396     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
 397     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
 398     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
 399 };
 400
 401 DEFINE_TYPES(avr_cpu_type_info)