2 * s390 PCI instructions
4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
15 #include "qemu-common.h"
17 #include "s390-pci-inst.h"
18 #include "s390-pci-bus.h"
19 #include "exec/memory-internal.h"
20 #include "qemu/error-report.h"
21 #include "sysemu/hw_accel.h"
23 #ifndef DEBUG_S390PCI_INST
24 #define DEBUG_S390PCI_INST 0
27 #define DPRINTF(fmt, ...) \
29 if (DEBUG_S390PCI_INST) { \
30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
34 static void s390_set_status_code(CPUS390XState
*env
,
35 uint8_t r
, uint64_t status_code
)
37 env
->regs
[r
] &= ~0xff000000ULL
;
38 env
->regs
[r
] |= (status_code
& 0xff) << 24;
41 static int list_pci(ClpReqRspListPci
*rrb
, uint8_t *cc
)
43 S390PCIBusDevice
*pbdev
= NULL
;
44 S390pciState
*s
= s390_get_phb();
45 uint32_t res_code
, initial_l2
, g_l2
;
47 uint64_t resume_token
;
50 if (lduw_p(&rrb
->request
.hdr
.len
) != 32) {
51 res_code
= CLP_RC_LEN
;
56 if ((ldl_p(&rrb
->request
.fmt
) & CLP_MASK_FMT
) != 0) {
57 res_code
= CLP_RC_FMT
;
62 if ((ldl_p(&rrb
->request
.fmt
) & ~CLP_MASK_FMT
) != 0 ||
63 ldq_p(&rrb
->request
.reserved1
) != 0) {
64 res_code
= CLP_RC_RESNOT0
;
69 resume_token
= ldq_p(&rrb
->request
.resume_token
);
72 pbdev
= s390_pci_find_dev_by_idx(s
, resume_token
);
74 res_code
= CLP_RC_LISTPCI_BADRT
;
79 pbdev
= s390_pci_find_next_avail_dev(s
, NULL
);
82 if (lduw_p(&rrb
->response
.hdr
.len
) < 48) {
88 initial_l2
= lduw_p(&rrb
->response
.hdr
.len
);
89 if ((initial_l2
- LIST_PCI_HDR_LEN
) % sizeof(ClpFhListEntry
)
91 res_code
= CLP_RC_LEN
;
97 stl_p(&rrb
->response
.fmt
, 0);
98 stq_p(&rrb
->response
.reserved1
, 0);
99 stl_p(&rrb
->response
.mdd
, FH_MASK_SHM
);
100 stw_p(&rrb
->response
.max_fn
, PCI_MAX_FUNCTIONS
);
101 rrb
->response
.flags
= UID_CHECKING_ENABLED
;
102 rrb
->response
.entry_size
= sizeof(ClpFhListEntry
);
105 g_l2
= LIST_PCI_HDR_LEN
;
106 while (g_l2
< initial_l2
&& pbdev
) {
107 stw_p(&rrb
->response
.fh_list
[i
].device_id
,
108 pci_get_word(pbdev
->pdev
->config
+ PCI_DEVICE_ID
));
109 stw_p(&rrb
->response
.fh_list
[i
].vendor_id
,
110 pci_get_word(pbdev
->pdev
->config
+ PCI_VENDOR_ID
));
111 /* Ignore RESERVED devices. */
112 stl_p(&rrb
->response
.fh_list
[i
].config
,
113 pbdev
->state
== ZPCI_FS_STANDBY
? 0 : 1 << 31);
114 stl_p(&rrb
->response
.fh_list
[i
].fid
, pbdev
->fid
);
115 stl_p(&rrb
->response
.fh_list
[i
].fh
, pbdev
->fh
);
117 g_l2
+= sizeof(ClpFhListEntry
);
118 /* Add endian check for DPRINTF? */
119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
121 lduw_p(&rrb
->response
.fh_list
[i
].vendor_id
),
122 lduw_p(&rrb
->response
.fh_list
[i
].device_id
),
123 ldl_p(&rrb
->response
.fh_list
[i
].fid
),
124 ldl_p(&rrb
->response
.fh_list
[i
].fh
));
125 pbdev
= s390_pci_find_next_avail_dev(s
, pbdev
);
132 resume_token
= pbdev
->fh
& FH_MASK_INDEX
;
134 stq_p(&rrb
->response
.resume_token
, resume_token
);
135 stw_p(&rrb
->response
.hdr
.len
, g_l2
);
136 stw_p(&rrb
->response
.hdr
.rsp
, CLP_RC_OK
);
139 DPRINTF("list pci failed rc 0x%x\n", rc
);
140 stw_p(&rrb
->response
.hdr
.rsp
, res_code
);
145 int clp_service_call(S390CPU
*cpu
, uint8_t r2
, uintptr_t ra
)
149 S390PCIBusDevice
*pbdev
;
152 uint8_t buffer
[4096 * 2];
154 CPUS390XState
*env
= &cpu
->env
;
155 S390pciState
*s
= s390_get_phb();
158 cpu_synchronize_state(CPU(cpu
));
160 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
161 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
165 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
, sizeof(*reqh
))) {
166 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
169 reqh
= (ClpReqHdr
*)buffer
;
170 req_len
= lduw_p(&reqh
->len
);
171 if (req_len
< 16 || req_len
> 8184 || (req_len
% 8 != 0)) {
172 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
176 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
177 req_len
+ sizeof(*resh
))) {
178 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
181 resh
= (ClpRspHdr
*)(buffer
+ req_len
);
182 res_len
= lduw_p(&resh
->len
);
183 if (res_len
< 8 || res_len
> 8176 || (res_len
% 8 != 0)) {
184 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
187 if ((req_len
+ res_len
) > 8192) {
188 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
192 if (s390_cpu_virt_mem_read(cpu
, env
->regs
[r2
], r2
, buffer
,
193 req_len
+ res_len
)) {
194 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
199 stw_p(&resh
->rsp
, CLP_RC_LEN
);
203 switch (lduw_p(&reqh
->cmd
)) {
205 ClpReqRspListPci
*rrb
= (ClpReqRspListPci
*)buffer
;
209 case CLP_SET_PCI_FN
: {
210 ClpReqSetPci
*reqsetpci
= (ClpReqSetPci
*)reqh
;
211 ClpRspSetPci
*ressetpci
= (ClpRspSetPci
*)resh
;
213 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqsetpci
->fh
));
215 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
219 switch (reqsetpci
->oc
) {
220 case CLP_SET_ENABLE_PCI_FN
:
221 switch (reqsetpci
->ndas
) {
223 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_DMAAS
);
228 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_RES
);
232 if (pbdev
->fh
& FH_MASK_ENABLE
) {
233 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
237 pbdev
->fh
|= FH_MASK_ENABLE
;
238 pbdev
->state
= ZPCI_FS_ENABLED
;
239 stl_p(&ressetpci
->fh
, pbdev
->fh
);
240 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
242 case CLP_SET_DISABLE_PCI_FN
:
243 if (!(pbdev
->fh
& FH_MASK_ENABLE
)) {
244 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
247 device_reset(DEVICE(pbdev
));
248 pbdev
->fh
&= ~FH_MASK_ENABLE
;
249 pbdev
->state
= ZPCI_FS_DISABLED
;
250 stl_p(&ressetpci
->fh
, pbdev
->fh
);
251 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_OK
);
254 DPRINTF("unknown set pci command\n");
255 stw_p(&ressetpci
->hdr
.rsp
, CLP_RC_SETPCIFN_FHOP
);
260 case CLP_QUERY_PCI_FN
: {
261 ClpReqQueryPci
*reqquery
= (ClpReqQueryPci
*)reqh
;
262 ClpRspQueryPci
*resquery
= (ClpRspQueryPci
*)resh
;
264 pbdev
= s390_pci_find_dev_by_fh(s
, ldl_p(&reqquery
->fh
));
266 DPRINTF("query pci no pci dev\n");
267 stw_p(&resquery
->hdr
.rsp
, CLP_RC_SETPCIFN_FH
);
271 for (i
= 0; i
< PCI_BAR_COUNT
; i
++) {
272 uint32_t data
= pci_get_long(pbdev
->pdev
->config
+
273 PCI_BASE_ADDRESS_0
+ (i
* 4));
275 stl_p(&resquery
->bar
[i
], data
);
276 resquery
->bar_size
[i
] = pbdev
->pdev
->io_regions
[i
].size
?
277 ctz64(pbdev
->pdev
->io_regions
[i
].size
) : 0;
278 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64
"barsize 0x%x\n", i
,
279 ldl_p(&resquery
->bar
[i
]),
280 pbdev
->pdev
->io_regions
[i
].size
,
281 resquery
->bar_size
[i
]);
284 stq_p(&resquery
->sdma
, ZPCI_SDMA_ADDR
);
285 stq_p(&resquery
->edma
, ZPCI_EDMA_ADDR
);
286 stl_p(&resquery
->fid
, pbdev
->fid
);
287 stw_p(&resquery
->pchid
, 0);
288 stw_p(&resquery
->ug
, 1);
289 stl_p(&resquery
->uid
, pbdev
->uid
);
290 stw_p(&resquery
->hdr
.rsp
, CLP_RC_OK
);
293 case CLP_QUERY_PCI_FNGRP
: {
294 ClpRspQueryPciGrp
*resgrp
= (ClpRspQueryPciGrp
*)resh
;
296 stq_p(&resgrp
->dasm
, 0);
297 stq_p(&resgrp
->msia
, ZPCI_MSI_ADDR
);
298 stw_p(&resgrp
->mui
, 0);
299 stw_p(&resgrp
->i
, 128);
300 stw_p(&resgrp
->maxstbl
, 128);
303 stw_p(&resgrp
->hdr
.rsp
, CLP_RC_OK
);
307 DPRINTF("unknown clp command\n");
308 stw_p(&resh
->rsp
, CLP_RC_CMD
);
313 if (s390_cpu_virt_mem_write(cpu
, env
->regs
[r2
], r2
, buffer
,
314 req_len
+ res_len
)) {
315 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
323 * Swap data contained in s390x big endian registers to little endian
326 * @ptr: a pointer to a uint64_t data field
327 * @len: the length of the valid data, must be 1,2,4 or 8
329 static int zpci_endian_swap(uint64_t *ptr
, uint8_t len
)
331 uint64_t data
= *ptr
;
337 data
= bswap16(data
);
340 data
= bswap32(data
);
343 data
= bswap64(data
);
352 static MemoryRegion
*s390_get_subregion(MemoryRegion
*mr
, uint64_t offset
,
355 MemoryRegion
*subregion
;
356 uint64_t subregion_size
;
358 QTAILQ_FOREACH(subregion
, &mr
->subregions
, subregions_link
) {
359 subregion_size
= int128_get64(subregion
->size
);
360 if ((offset
>= subregion
->addr
) &&
361 (offset
+ len
) <= (subregion
->addr
+ subregion_size
)) {
369 static MemTxResult
zpci_read_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
370 uint64_t offset
, uint64_t *data
, uint8_t len
)
374 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
375 mr
= s390_get_subregion(mr
, offset
, len
);
377 return memory_region_dispatch_read(mr
, offset
, data
, len
,
378 MEMTXATTRS_UNSPECIFIED
);
381 int pcilg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
383 CPUS390XState
*env
= &cpu
->env
;
384 S390PCIBusDevice
*pbdev
;
392 cpu_synchronize_state(CPU(cpu
));
394 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
395 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
400 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
404 fh
= env
->regs
[r2
] >> 32;
405 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
406 len
= env
->regs
[r2
] & 0xf;
407 offset
= env
->regs
[r2
+ 1];
409 if (!(fh
& FH_MASK_ENABLE
)) {
410 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
414 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
416 DPRINTF("pcilg no pci dev\n");
417 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
421 switch (pbdev
->state
) {
422 case ZPCI_FS_PERMANENT_ERROR
:
424 setcc(cpu
, ZPCI_PCI_LS_ERR
);
425 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
432 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
433 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
434 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
437 result
= zpci_read_bar(pbdev
, pcias
, offset
, &data
, len
);
438 if (result
!= MEMTX_OK
) {
439 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
443 case ZPCI_CONFIG_BAR
:
444 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
445 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
448 data
= pci_host_config_read_common(
449 pbdev
->pdev
, offset
, pci_config_size(pbdev
->pdev
), len
);
451 if (zpci_endian_swap(&data
, len
)) {
452 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
457 DPRINTF("pcilg invalid space\n");
458 setcc(cpu
, ZPCI_PCI_LS_ERR
);
459 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
463 env
->regs
[r1
] = data
;
464 setcc(cpu
, ZPCI_PCI_LS_OK
);
468 static MemTxResult
zpci_write_bar(S390PCIBusDevice
*pbdev
, uint8_t pcias
,
469 uint64_t offset
, uint64_t data
, uint8_t len
)
473 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
474 mr
= s390_get_subregion(mr
, offset
, len
);
476 return memory_region_dispatch_write(mr
, offset
, data
, len
,
477 MEMTXATTRS_UNSPECIFIED
);
480 int pcistg_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
482 CPUS390XState
*env
= &cpu
->env
;
483 uint64_t offset
, data
;
484 S390PCIBusDevice
*pbdev
;
490 cpu_synchronize_state(CPU(cpu
));
492 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
493 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
498 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
502 fh
= env
->regs
[r2
] >> 32;
503 pcias
= (env
->regs
[r2
] >> 16) & 0xf;
504 len
= env
->regs
[r2
] & 0xf;
505 offset
= env
->regs
[r2
+ 1];
506 data
= env
->regs
[r1
];
508 if (!(fh
& FH_MASK_ENABLE
)) {
509 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
513 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
515 DPRINTF("pcistg no pci dev\n");
516 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
520 switch (pbdev
->state
) {
521 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED
522 * are already covered by the FH_MASK_ENABLE check above
524 case ZPCI_FS_PERMANENT_ERROR
:
526 setcc(cpu
, ZPCI_PCI_LS_ERR
);
527 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_BLOCKED
);
534 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */
535 case ZPCI_IO_BAR_MIN
...ZPCI_IO_BAR_MAX
:
537 * A length of 0 is invalid and length should not cross a double word
539 if (!len
|| (len
> (8 - (offset
& 0x7)))) {
540 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
544 result
= zpci_write_bar(pbdev
, pcias
, offset
, data
, len
);
545 if (result
!= MEMTX_OK
) {
546 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
550 case ZPCI_CONFIG_BAR
:
551 /* ZPCI uses the pseudo BAR number 15 as configuration space */
552 /* possible access lengths are 1,2,4 and must not cross a word */
553 if (!len
|| (len
> (4 - (offset
& 0x3))) || len
== 3) {
554 s390_program_interrupt(env
, PGM_OPERAND
, 4, ra
);
557 /* len = 1,2,4 so we do not need to test */
558 zpci_endian_swap(&data
, len
);
559 pci_host_config_write_common(pbdev
->pdev
, offset
,
560 pci_config_size(pbdev
->pdev
),
564 DPRINTF("pcistg invalid space\n");
565 setcc(cpu
, ZPCI_PCI_LS_ERR
);
566 s390_set_status_code(env
, r2
, ZPCI_PCI_ST_INVAL_AS
);
570 setcc(cpu
, ZPCI_PCI_LS_OK
);
574 static void s390_pci_update_iotlb(S390PCIIOMMU
*iommu
, S390IOTLBEntry
*entry
)
576 S390IOTLBEntry
*cache
= g_hash_table_lookup(iommu
->iotlb
, &entry
->iova
);
577 IOMMUTLBEntry notify
= {
578 .target_as
= &address_space_memory
,
580 .translated_addr
= entry
->translated_addr
,
582 .addr_mask
= ~PAGE_MASK
,
585 if (entry
->perm
== IOMMU_NONE
) {
589 g_hash_table_remove(iommu
->iotlb
, &entry
->iova
);
592 if (cache
->perm
== entry
->perm
&&
593 cache
->translated_addr
== entry
->translated_addr
) {
597 notify
.perm
= IOMMU_NONE
;
598 memory_region_notify_iommu(&iommu
->iommu_mr
, notify
);
599 notify
.perm
= entry
->perm
;
602 cache
= g_new(S390IOTLBEntry
, 1);
603 cache
->iova
= entry
->iova
;
604 cache
->translated_addr
= entry
->translated_addr
;
605 cache
->len
= PAGE_SIZE
;
606 cache
->perm
= entry
->perm
;
607 g_hash_table_replace(iommu
->iotlb
, &cache
->iova
, cache
);
610 memory_region_notify_iommu(&iommu
->iommu_mr
, notify
);
613 int rpcit_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r2
, uintptr_t ra
)
615 CPUS390XState
*env
= &cpu
->env
;
618 S390PCIBusDevice
*pbdev
;
620 S390IOTLBEntry entry
;
623 cpu_synchronize_state(CPU(cpu
));
625 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
626 s390_program_interrupt(env
, PGM_PRIVILEGED
, 4, ra
);
631 s390_program_interrupt(env
, PGM_SPECIFICATION
, 4, ra
);
635 fh
= env
->regs
[r1
] >> 32;
636 start
= env
->regs
[r2
];
637 end
= start
+ env
->regs
[r2
+ 1];
639 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
641 DPRINTF("rpcit no pci dev\n");
642 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
646 switch (pbdev
->state
) {
647 case ZPCI_FS_RESERVED
:
648 case ZPCI_FS_STANDBY
:
649 case ZPCI_FS_DISABLED
:
650 case ZPCI_FS_PERMANENT_ERROR
:
651 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
654 setcc(cpu
, ZPCI_PCI_LS_ERR
);
655 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_ERROR_RECOVER
);
661 iommu
= pbdev
->iommu
;
662 if (!iommu
->g_iota
) {
663 error
= ERR_EVENT_INVALAS
;
667 if (end
< iommu
->pba
|| start
> iommu
->pal
) {
668 error
= ERR_EVENT_OORANGE
;
672 while (start
< end
) {
673 error
= s390_guest_io_table_walk(iommu
->g_iota
, start
, &entry
);
679 while (entry
.iova
< start
&& entry
.iova
< end
) {
680 s390_pci_update_iotlb(iommu
, &entry
);
681 entry
.iova
+= PAGE_SIZE
;
682 entry
.translated_addr
+= PAGE_SIZE
;
687 pbdev
->state
= ZPCI_FS_ERROR
;
688 setcc(cpu
, ZPCI_PCI_LS_ERR
);
689 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_FUNC_IN_ERR
);
690 s390_pci_generate_error_event(error
, pbdev
->fh
, pbdev
->fid
, start
, 0);
692 setcc(cpu
, ZPCI_PCI_LS_OK
);
697 int pcistb_service_call(S390CPU
*cpu
, uint8_t r1
, uint8_t r3
, uint64_t gaddr
,
698 uint8_t ar
, uintptr_t ra
)
700 CPUS390XState
*env
= &cpu
->env
;
701 S390PCIBusDevice
*pbdev
;
711 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
712 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
716 fh
= env
->regs
[r1
] >> 32;
717 pcias
= (env
->regs
[r1
] >> 16) & 0xf;
718 len
= env
->regs
[r1
] & 0xff;
719 offset
= env
->regs
[r3
];
721 if (!(fh
& FH_MASK_ENABLE
)) {
722 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
726 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
728 DPRINTF("pcistb no pci dev fh 0x%x\n", fh
);
729 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
733 switch (pbdev
->state
) {
734 case ZPCI_FS_PERMANENT_ERROR
:
736 setcc(cpu
, ZPCI_PCI_LS_ERR
);
737 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_BLOCKED
);
743 if (pcias
> ZPCI_IO_BAR_MAX
) {
744 DPRINTF("pcistb invalid space\n");
745 setcc(cpu
, ZPCI_PCI_LS_ERR
);
746 s390_set_status_code(env
, r1
, ZPCI_PCI_ST_INVAL_AS
);
750 /* Verify the address, offset and length */
751 /* offset must be a multiple of 8 */
753 goto specification_error
;
755 /* Length must be greater than 8, a multiple of 8 */
756 /* and not greater than maxstbl */
757 if ((len
<= 8) || (len
% 8) || (len
> pbdev
->maxstbl
)) {
758 goto specification_error
;
760 /* Do not cross a 4K-byte boundary */
761 if (((offset
& 0xfff) + len
) > 0x1000) {
762 goto specification_error
;
764 /* Guest address must be double word aligned */
765 if (gaddr
& 0x07UL
) {
766 goto specification_error
;
769 mr
= pbdev
->pdev
->io_regions
[pcias
].memory
;
770 mr
= s390_get_subregion(mr
, offset
, len
);
773 if (!memory_region_access_valid(mr
, offset
, len
, true)) {
774 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
778 if (s390_cpu_virt_mem_read(cpu
, gaddr
, ar
, buffer
, len
)) {
779 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
783 for (i
= 0; i
< len
/ 8; i
++) {
784 result
= memory_region_dispatch_write(mr
, offset
+ i
* 8,
785 ldq_p(buffer
+ i
* 8), 8,
786 MEMTXATTRS_UNSPECIFIED
);
787 if (result
!= MEMTX_OK
) {
788 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
793 setcc(cpu
, ZPCI_PCI_LS_OK
);
797 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
801 static int reg_irqs(CPUS390XState
*env
, S390PCIBusDevice
*pbdev
, ZpciFib fib
)
804 uint8_t isc
= FIB_DATA_ISC(ldl_p(&fib
.data
));
806 pbdev
->routes
.adapter
.adapter_id
= css_get_adapter_id(
807 CSS_IO_ADAPTER_PCI
, isc
);
808 pbdev
->summary_ind
= get_indicator(ldq_p(&fib
.aisb
), sizeof(uint64_t));
809 len
= BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib
.data
))) * sizeof(unsigned long);
810 pbdev
->indicator
= get_indicator(ldq_p(&fib
.aibv
), len
);
812 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
817 ret
= map_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
822 pbdev
->routes
.adapter
.summary_addr
= ldq_p(&fib
.aisb
);
823 pbdev
->routes
.adapter
.summary_offset
= FIB_DATA_AISBO(ldl_p(&fib
.data
));
824 pbdev
->routes
.adapter
.ind_addr
= ldq_p(&fib
.aibv
);
825 pbdev
->routes
.adapter
.ind_offset
= FIB_DATA_AIBVO(ldl_p(&fib
.data
));
827 pbdev
->noi
= FIB_DATA_NOI(ldl_p(&fib
.data
));
828 pbdev
->sum
= FIB_DATA_SUM(ldl_p(&fib
.data
));
830 DPRINTF("reg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
833 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
834 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
835 pbdev
->summary_ind
= NULL
;
836 pbdev
->indicator
= NULL
;
840 int pci_dereg_irqs(S390PCIBusDevice
*pbdev
)
842 release_indicator(&pbdev
->routes
.adapter
, pbdev
->summary_ind
);
843 release_indicator(&pbdev
->routes
.adapter
, pbdev
->indicator
);
845 pbdev
->summary_ind
= NULL
;
846 pbdev
->indicator
= NULL
;
847 pbdev
->routes
.adapter
.summary_addr
= 0;
848 pbdev
->routes
.adapter
.summary_offset
= 0;
849 pbdev
->routes
.adapter
.ind_addr
= 0;
850 pbdev
->routes
.adapter
.ind_offset
= 0;
855 DPRINTF("dereg_irqs adapter id %d\n", pbdev
->routes
.adapter
.adapter_id
);
859 static int reg_ioat(CPUS390XState
*env
, S390PCIIOMMU
*iommu
, ZpciFib fib
,
862 uint64_t pba
= ldq_p(&fib
.pba
);
863 uint64_t pal
= ldq_p(&fib
.pal
);
864 uint64_t g_iota
= ldq_p(&fib
.iota
);
865 uint8_t dt
= (g_iota
>> 2) & 0x7;
866 uint8_t t
= (g_iota
>> 11) & 0x1;
870 if (pba
> pal
|| pba
< ZPCI_SDMA_ADDR
|| pal
> ZPCI_EDMA_ADDR
) {
871 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
875 /* currently we only support designation type 1 with translation */
876 if (!(dt
== ZPCI_IOTA_RTTO
&& t
)) {
877 error_report("unsupported ioat dt %d t %d", dt
, t
);
878 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
884 iommu
->g_iota
= g_iota
;
886 s390_pci_iommu_enable(iommu
);
891 void pci_dereg_ioat(S390PCIIOMMU
*iommu
)
893 s390_pci_iommu_disable(iommu
);
899 int mpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
902 CPUS390XState
*env
= &cpu
->env
;
906 S390PCIBusDevice
*pbdev
;
907 uint64_t cc
= ZPCI_PCI_LS_OK
;
909 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
910 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
914 oc
= env
->regs
[r1
] & 0xff;
915 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
916 fh
= env
->regs
[r1
] >> 32;
919 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
923 pbdev
= s390_pci_find_dev_by_fh(s390_get_phb(), fh
);
925 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh
);
926 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
930 switch (pbdev
->state
) {
931 case ZPCI_FS_RESERVED
:
932 case ZPCI_FS_STANDBY
:
933 case ZPCI_FS_DISABLED
:
934 case ZPCI_FS_PERMANENT_ERROR
:
935 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
941 if (s390_cpu_virt_mem_read(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
942 s390_cpu_virt_mem_handle_exc(cpu
, ra
);
947 s390_program_interrupt(env
, PGM_OPERAND
, 6, ra
);
952 case ZPCI_MOD_FC_REG_INT
:
953 if (pbdev
->summary_ind
) {
954 cc
= ZPCI_PCI_LS_ERR
;
955 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
956 } else if (reg_irqs(env
, pbdev
, fib
)) {
957 cc
= ZPCI_PCI_LS_ERR
;
958 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_RES_NOT_AVAIL
);
961 case ZPCI_MOD_FC_DEREG_INT
:
962 if (!pbdev
->summary_ind
) {
963 cc
= ZPCI_PCI_LS_ERR
;
964 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
966 pci_dereg_irqs(pbdev
);
969 case ZPCI_MOD_FC_REG_IOAT
:
971 cc
= ZPCI_PCI_LS_ERR
;
972 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
973 } else if (pbdev
->iommu
->enabled
) {
974 cc
= ZPCI_PCI_LS_ERR
;
975 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
976 } else if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
977 cc
= ZPCI_PCI_LS_ERR
;
978 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
981 case ZPCI_MOD_FC_DEREG_IOAT
:
983 cc
= ZPCI_PCI_LS_ERR
;
984 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
985 } else if (!pbdev
->iommu
->enabled
) {
986 cc
= ZPCI_PCI_LS_ERR
;
987 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
989 pci_dereg_ioat(pbdev
->iommu
);
992 case ZPCI_MOD_FC_REREG_IOAT
:
994 cc
= ZPCI_PCI_LS_ERR
;
995 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_DMAAS_INVAL
);
996 } else if (!pbdev
->iommu
->enabled
) {
997 cc
= ZPCI_PCI_LS_ERR
;
998 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1000 pci_dereg_ioat(pbdev
->iommu
);
1001 if (reg_ioat(env
, pbdev
->iommu
, fib
, ra
)) {
1002 cc
= ZPCI_PCI_LS_ERR
;
1003 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_INSUF_RES
);
1007 case ZPCI_MOD_FC_RESET_ERROR
:
1008 switch (pbdev
->state
) {
1009 case ZPCI_FS_BLOCKED
:
1011 pbdev
->state
= ZPCI_FS_ENABLED
;
1014 cc
= ZPCI_PCI_LS_ERR
;
1015 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1018 case ZPCI_MOD_FC_RESET_BLOCK
:
1019 switch (pbdev
->state
) {
1021 pbdev
->state
= ZPCI_FS_BLOCKED
;
1024 cc
= ZPCI_PCI_LS_ERR
;
1025 s390_set_status_code(env
, r1
, ZPCI_MOD_ST_SEQUENCE
);
1028 case ZPCI_MOD_FC_SET_MEASURE
:
1029 pbdev
->fmb_addr
= ldq_p(&fib
.fmb_addr
);
1032 s390_program_interrupt(&cpu
->env
, PGM_OPERAND
, 6, ra
);
1033 cc
= ZPCI_PCI_LS_ERR
;
1040 int stpcifc_service_call(S390CPU
*cpu
, uint8_t r1
, uint64_t fiba
, uint8_t ar
,
1043 CPUS390XState
*env
= &cpu
->env
;
1047 S390PCIBusDevice
*pbdev
;
1049 uint64_t cc
= ZPCI_PCI_LS_OK
;
1051 if (env
->psw
.mask
& PSW_MASK_PSTATE
) {
1052 s390_program_interrupt(env
, PGM_PRIVILEGED
, 6, ra
);
1056 fh
= env
->regs
[r1
] >> 32;
1057 dmaas
= (env
->regs
[r1
] >> 16) & 0xff;
1060 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1061 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_INVAL_DMAAS
);
1066 s390_program_interrupt(env
, PGM_SPECIFICATION
, 6, ra
);
1070 pbdev
= s390_pci_find_dev_by_idx(s390_get_phb(), fh
& FH_MASK_INDEX
);
1072 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1076 memset(&fib
, 0, sizeof(fib
));
1078 switch (pbdev
->state
) {
1079 case ZPCI_FS_RESERVED
:
1080 case ZPCI_FS_STANDBY
:
1081 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1083 case ZPCI_FS_DISABLED
:
1084 if (fh
& FH_MASK_ENABLE
) {
1085 setcc(cpu
, ZPCI_PCI_LS_INVAL_HANDLE
);
1089 /* BLOCKED bit is set to one coincident with the setting of ERROR bit.
1090 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */
1093 case ZPCI_FS_BLOCKED
:
1095 case ZPCI_FS_ENABLED
:
1097 if (pbdev
->iommu
->enabled
) {
1100 if (!(fh
& FH_MASK_ENABLE
)) {
1101 env
->regs
[r1
] |= 1ULL << 63;
1104 case ZPCI_FS_PERMANENT_ERROR
:
1105 setcc(cpu
, ZPCI_PCI_LS_ERR
);
1106 s390_set_status_code(env
, r1
, ZPCI_STPCIFC_ST_PERM_ERROR
);
1110 stq_p(&fib
.pba
, pbdev
->iommu
->pba
);
1111 stq_p(&fib
.pal
, pbdev
->iommu
->pal
);
1112 stq_p(&fib
.iota
, pbdev
->iommu
->g_iota
);
1113 stq_p(&fib
.aibv
, pbdev
->routes
.adapter
.ind_addr
);
1114 stq_p(&fib
.aisb
, pbdev
->routes
.adapter
.summary_addr
);
1115 stq_p(&fib
.fmb_addr
, pbdev
->fmb_addr
);
1117 data
= ((uint32_t)pbdev
->isc
<< 28) | ((uint32_t)pbdev
->noi
<< 16) |
1118 ((uint32_t)pbdev
->routes
.adapter
.ind_offset
<< 8) |
1119 ((uint32_t)pbdev
->sum
<< 7) | pbdev
->routes
.adapter
.summary_offset
;
1120 stl_p(&fib
.data
, data
);
1123 if (s390_cpu_virt_mem_write(cpu
, fiba
, ar
, (uint8_t *)&fib
, sizeof(fib
))) {
1124 s390_cpu_virt_mem_handle_exc(cpu
, ra
);