2 * HP-PARISC Dino PCI chipset emulation.
4 * (C) 2017 by Helge Deller <deller@gmx.de>
6 * This work is licensed under the GNU GPL license version 2 or later.
8 * Documentation available at:
9 * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf
10 * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
17 #include "hw/devices.h"
18 #include "sysemu/sysemu.h"
19 #include "hw/pci/pci.h"
20 #include "hw/pci/pci_bus.h"
22 #include "exec/address-spaces.h"
25 #define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost"
27 #define DINO_IAR0 0x004
28 #define DINO_IODC 0x008
29 #define DINO_IRR0 0x00C /* RO */
30 #define DINO_IAR1 0x010
31 #define DINO_IRR1 0x014 /* RO */
32 #define DINO_IMR 0x018
33 #define DINO_IPR 0x01C
34 #define DINO_TOC_ADDR 0x020
35 #define DINO_ICR 0x024
36 #define DINO_ILR 0x028 /* RO */
37 #define DINO_IO_COMMAND 0x030 /* WO */
38 #define DINO_IO_STATUS 0x034 /* RO */
39 #define DINO_IO_CONTROL 0x038
40 #define DINO_IO_GSC_ERR_RESP 0x040 /* RO */
41 #define DINO_IO_ERR_INFO 0x044 /* RO */
42 #define DINO_IO_PCI_ERR_RESP 0x048 /* RO */
43 #define DINO_IO_FBB_EN 0x05c
44 #define DINO_IO_ADDR_EN 0x060
45 #define DINO_PCI_CONFIG_ADDR 0x064
46 #define DINO_PCI_CONFIG_DATA 0x068
47 #define DINO_PCI_IO_DATA 0x06c
48 #define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */
49 #define DINO_GSC2X_CONFIG 0x7b4 /* RO */
50 #define DINO_GMASK 0x800
51 #define DINO_PAMR 0x804
52 #define DINO_PAPR 0x808
53 #define DINO_DAMODE 0x80c
54 #define DINO_PCICMD 0x810
55 #define DINO_PCISTS 0x814 /* R/WC */
56 #define DINO_MLTIM 0x81c
57 #define DINO_BRDG_FEAT 0x820
58 #define DINO_PCIROR 0x824
59 #define DINO_PCIWOR 0x828
60 #define DINO_TLTIM 0x830
62 #define DINO_IRQS 11 /* bits 0-10 are architected */
63 #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
64 #define DINO_LOCAL_IRQS (DINO_IRQS + 1)
65 #define DINO_MASK_IRQ(x) (1 << (x))
73 #define GSCEXTINT 0x040
74 /* #define xxx 0x080 - bit 7 is "default" */
75 /* #define xxx 0x100 - bit 8 not used */
76 /* #define xxx 0x200 - bit 9 not used */
77 #define RS232INT 0x400
79 #define DINO_MEM_CHUNK_SIZE (8 * 1024 * 1024) /* 8MB */
81 #define DINO_PCI_HOST_BRIDGE(obj) \
82 OBJECT_CHECK(DinoState, (obj), TYPE_DINO_PCI_HOST_BRIDGE)
84 typedef struct DinoState
{
85 PCIHostState parent_obj
;
87 /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops,
88 so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */
99 MemoryRegion this_mem
;
100 MemoryRegion pci_mem
;
101 MemoryRegion pci_mem_alias
[32];
105 MemoryRegion bm_ram_alias
;
106 MemoryRegion bm_pci_alias
;
108 MemoryRegion cpu0_eir_mem
;
112 * Dino can forward memory accesses from the CPU in the range between
113 * 0xf0800000 and 0xff000000 to the PCI bus.
115 static void gsc_to_pci_forwarding(DinoState
*s
)
117 uint32_t io_addr_en
, tmp
;
120 tmp
= extract32(s
->io_control
, 7, 2);
121 enabled
= (tmp
== 0x01);
122 io_addr_en
= s
->io_addr_en
;
124 memory_region_transaction_begin();
125 for (i
= 1; i
< 31; i
++) {
126 MemoryRegion
*mem
= &s
->pci_mem_alias
[i
];
127 if (enabled
&& (io_addr_en
& (1U << i
))) {
128 if (!memory_region_is_mapped(mem
)) {
129 uint32_t addr
= 0xf0000000 + i
* DINO_MEM_CHUNK_SIZE
;
130 memory_region_add_subregion(get_system_memory(), addr
, mem
);
132 } else if (memory_region_is_mapped(mem
)) {
133 memory_region_del_subregion(get_system_memory(), mem
);
136 memory_region_transaction_commit();
139 static bool dino_chip_mem_valid(void *opaque
, hwaddr addr
,
140 unsigned size
, bool is_write
)
151 case DINO_IO_CONTROL
:
152 case DINO_IO_ADDR_EN
:
153 case DINO_PCI_IO_DATA
:
155 case DINO_PCI_IO_DATA
+ 2:
157 case DINO_PCI_IO_DATA
+ 1:
158 case DINO_PCI_IO_DATA
+ 3:
164 static MemTxResult
dino_chip_read_with_attrs(void *opaque
, hwaddr addr
,
165 uint64_t *data
, unsigned size
,
168 DinoState
*s
= opaque
;
169 MemTxResult ret
= MEMTX_OK
;
175 case DINO_PCI_IO_DATA
... DINO_PCI_IO_DATA
+ 3:
176 /* Read from PCI IO space. */
177 io
= &address_space_io
;
178 ioaddr
= s
->parent_obj
.config_reg
;
181 val
= address_space_ldub(io
, ioaddr
, attrs
, &ret
);
184 val
= address_space_lduw_be(io
, ioaddr
, attrs
, &ret
);
187 val
= address_space_ldl_be(io
, ioaddr
, attrs
, &ret
);
190 g_assert_not_reached();
194 case DINO_IO_ADDR_EN
:
197 case DINO_IO_CONTROL
:
215 /* Any read to IPR clears the register. */
222 val
= s
->ilr
& s
->imr
& ~s
->icr
;
225 val
= s
->ilr
& s
->imr
& s
->icr
;
229 /* Controlled by dino_chip_mem_valid above. */
230 g_assert_not_reached();
237 static MemTxResult
dino_chip_write_with_attrs(void *opaque
, hwaddr addr
,
238 uint64_t val
, unsigned size
,
241 DinoState
*s
= opaque
;
247 case DINO_IO_DATA
... DINO_PCI_IO_DATA
+ 3:
248 /* Write into PCI IO space. */
249 io
= &address_space_io
;
250 ioaddr
= s
->parent_obj
.config_reg
;
253 address_space_stb(io
, ioaddr
, val
, attrs
, &ret
);
256 address_space_stw_be(io
, ioaddr
, val
, attrs
, &ret
);
259 address_space_stl_be(io
, ioaddr
, val
, attrs
, &ret
);
262 g_assert_not_reached();
266 case DINO_IO_ADDR_EN
:
267 /* Never allow first (=firmware) and last (=Dino) areas. */
268 s
->io_addr_en
= val
& 0x7ffffffe;
269 gsc_to_pci_forwarding(s
);
271 case DINO_IO_CONTROL
:
273 gsc_to_pci_forwarding(s
);
289 /* Any write to IPR clears the register. */
296 /* These registers are read-only. */
300 /* Controlled by dino_chip_mem_valid above. */
301 g_assert_not_reached();
306 static const MemoryRegionOps dino_chip_ops
= {
307 .read_with_attrs
= dino_chip_read_with_attrs
,
308 .write_with_attrs
= dino_chip_write_with_attrs
,
309 .endianness
= DEVICE_BIG_ENDIAN
,
311 .min_access_size
= 1,
312 .max_access_size
= 4,
313 .accepts
= dino_chip_mem_valid
,
316 .min_access_size
= 1,
317 .max_access_size
= 4,
321 static const VMStateDescription vmstate_dino
= {
324 .minimum_version_id
= 1,
325 .fields
= (VMStateField
[]) {
326 VMSTATE_UINT32(iar0
, DinoState
),
327 VMSTATE_UINT32(iar1
, DinoState
),
328 VMSTATE_UINT32(imr
, DinoState
),
329 VMSTATE_UINT32(ipr
, DinoState
),
330 VMSTATE_UINT32(icr
, DinoState
),
331 VMSTATE_UINT32(ilr
, DinoState
),
332 VMSTATE_UINT32(io_addr_en
, DinoState
),
333 VMSTATE_UINT32(io_control
, DinoState
),
334 VMSTATE_END_OF_LIST()
339 /* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */
341 static uint64_t dino_config_data_read(void *opaque
, hwaddr addr
, unsigned len
)
343 PCIHostState
*s
= opaque
;
344 return pci_data_read(s
->bus
, s
->config_reg
| (addr
& 3), len
);
347 static void dino_config_data_write(void *opaque
, hwaddr addr
,
348 uint64_t val
, unsigned len
)
350 PCIHostState
*s
= opaque
;
351 pci_data_write(s
->bus
, s
->config_reg
| (addr
& 3), val
, len
);
354 static const MemoryRegionOps dino_config_data_ops
= {
355 .read
= dino_config_data_read
,
356 .write
= dino_config_data_write
,
357 .endianness
= DEVICE_LITTLE_ENDIAN
,
360 static AddressSpace
*dino_pcihost_set_iommu(PCIBus
*bus
, void *opaque
,
363 DinoState
*s
= opaque
;
369 * Dino interrupts are connected as shown on Page 78, Table 23
370 * (Little-endian bit numbers)
377 * 6 GSC External Interrupt
378 * 7 Bus Error for "less than fatal" mode
384 static void dino_set_irq(void *opaque
, int irq
, int level
)
386 DinoState
*s
= opaque
;
387 uint32_t bit
= 1u << irq
;
388 uint32_t old_ilr
= s
->ilr
;
391 uint32_t ena
= bit
& ~old_ilr
;
393 s
->ilr
= old_ilr
| bit
;
395 uint32_t iar
= (ena
& s
->icr
? s
->iar1
: s
->iar0
);
396 stl_be_phys(&address_space_memory
, iar
& -32, iar
& 31);
399 s
->ilr
= old_ilr
& ~bit
;
403 static int dino_pci_map_irq(PCIDevice
*d
, int irq_num
)
405 int slot
= d
->devfn
>> 3;
408 assert(irq_num
>= 0 && irq_num
<= 3);
410 local_irq
= slot
& 0x03;
415 static void dino_set_timer_irq(void *opaque
, int irq
, int level
)
417 /* ??? Not connected. */
420 static void dino_set_serial_irq(void *opaque
, int irq
, int level
)
422 dino_set_irq(opaque
, 10, level
);
425 PCIBus
*dino_init(MemoryRegion
*addr_space
,
426 qemu_irq
*p_rtc_irq
, qemu_irq
*p_ser_irq
)
433 dev
= qdev_create(NULL
, TYPE_DINO_PCI_HOST_BRIDGE
);
434 s
= DINO_PCI_HOST_BRIDGE(dev
);
436 /* Dino PCI access from main memory. */
437 memory_region_init_io(&s
->this_mem
, OBJECT(s
), &dino_chip_ops
,
439 memory_region_add_subregion(addr_space
, DINO_HPA
, &s
->this_mem
);
441 /* Dino PCI config. */
442 memory_region_init_io(&s
->parent_obj
.conf_mem
, OBJECT(&s
->parent_obj
),
443 &pci_host_conf_be_ops
, dev
, "pci-conf-idx", 4);
444 memory_region_init_io(&s
->parent_obj
.data_mem
, OBJECT(&s
->parent_obj
),
445 &dino_config_data_ops
, dev
, "pci-conf-data", 4);
446 memory_region_add_subregion(&s
->this_mem
, DINO_PCI_CONFIG_ADDR
,
447 &s
->parent_obj
.conf_mem
);
448 memory_region_add_subregion(&s
->this_mem
, DINO_CONFIG_DATA
,
449 &s
->parent_obj
.data_mem
);
451 /* Dino PCI bus memory. */
452 memory_region_init(&s
->pci_mem
, OBJECT(s
), "pci-memory", 1ull << 32);
454 b
= pci_register_root_bus(dev
, "pci", dino_set_irq
, dino_pci_map_irq
, s
,
455 &s
->pci_mem
, get_system_io(),
456 PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS
);
457 s
->parent_obj
.bus
= b
;
458 qdev_init_nofail(dev
);
460 /* Set up windows into PCI bus memory. */
461 for (i
= 1; i
< 31; i
++) {
462 uint32_t addr
= 0xf0000000 + i
* DINO_MEM_CHUNK_SIZE
;
463 char *name
= g_strdup_printf("PCI Outbound Window %d", i
);
464 memory_region_init_alias(&s
->pci_mem_alias
[i
], OBJECT(s
),
465 name
, &s
->pci_mem
, addr
,
466 DINO_MEM_CHUNK_SIZE
);
469 /* Set up PCI view of memory: Bus master address space. */
470 memory_region_init(&s
->bm
, OBJECT(s
), "bm-dino", 1ull << 32);
471 memory_region_init_alias(&s
->bm_ram_alias
, OBJECT(s
),
472 "bm-system", addr_space
, 0,
473 0xf0000000 + DINO_MEM_CHUNK_SIZE
);
474 memory_region_init_alias(&s
->bm_pci_alias
, OBJECT(s
),
475 "bm-pci", &s
->pci_mem
,
476 0xf0000000 + DINO_MEM_CHUNK_SIZE
,
477 31 * DINO_MEM_CHUNK_SIZE
);
478 memory_region_add_subregion(&s
->bm
, 0,
480 memory_region_add_subregion(&s
->bm
,
481 0xf0000000 + DINO_MEM_CHUNK_SIZE
,
483 address_space_init(&s
->bm_as
, &s
->bm
, "pci-bm");
484 pci_setup_iommu(b
, dino_pcihost_set_iommu
, s
);
486 *p_rtc_irq
= qemu_allocate_irq(dino_set_timer_irq
, s
, 0);
487 *p_ser_irq
= qemu_allocate_irq(dino_set_serial_irq
, s
, 0);
492 static int dino_pcihost_init(SysBusDevice
*dev
)
497 static void dino_pcihost_class_init(ObjectClass
*klass
, void *data
)
499 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
500 DeviceClass
*dc
= DEVICE_CLASS(klass
);
502 k
->init
= dino_pcihost_init
;
503 dc
->vmsd
= &vmstate_dino
;
506 static const TypeInfo dino_pcihost_info
= {
507 .name
= TYPE_DINO_PCI_HOST_BRIDGE
,
508 .parent
= TYPE_PCI_HOST_BRIDGE
,
509 .instance_size
= sizeof(DinoState
),
510 .class_init
= dino_pcihost_class_init
,
513 static void dino_register_types(void)
515 type_register_static(&dino_pcihost_info
);
518 type_init(dino_register_types
)