ppc/xive2: Make type Xive2EndSource not user creatable
[qemu.git] / cpu.c
blobd5648861490c85ddd9c22e23c76305af774d8776
1 /*
2 * Target-specific parts of the CPU object
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qapi/error.h"
24 #include "exec/target_page.h"
25 #include "hw/qdev-core.h"
26 #include "hw/qdev-properties.h"
27 #include "qemu/error-report.h"
28 #include "migration/vmstate.h"
29 #ifdef CONFIG_USER_ONLY
30 #include "qemu.h"
31 #else
32 #include "hw/core/sysemu-cpu-ops.h"
33 #include "exec/address-spaces.h"
34 #endif
35 #include "sysemu/tcg.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/replay.h"
38 #include "exec/exec-all.h"
39 #include "exec/translate-all.h"
40 #include "exec/log.h"
41 #include "hw/core/accel-cpu.h"
42 #include "trace/trace-root.h"
43 #include "qemu/accel.h"
45 uintptr_t qemu_host_page_size;
46 intptr_t qemu_host_page_mask;
48 #ifndef CONFIG_USER_ONLY
49 static int cpu_common_post_load(void *opaque, int version_id)
51 CPUState *cpu = opaque;
53 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
54 version_id is increased. */
55 cpu->interrupt_request &= ~0x01;
56 tlb_flush(cpu);
58 /* loadvm has just updated the content of RAM, bypassing the
59 * usual mechanisms that ensure we flush TBs for writes to
60 * memory we've translated code from. So we must flush all TBs,
61 * which will now be stale.
63 tb_flush(cpu);
65 return 0;
68 static int cpu_common_pre_load(void *opaque)
70 CPUState *cpu = opaque;
72 cpu->exception_index = -1;
74 return 0;
77 static bool cpu_common_exception_index_needed(void *opaque)
79 CPUState *cpu = opaque;
81 return tcg_enabled() && cpu->exception_index != -1;
84 static const VMStateDescription vmstate_cpu_common_exception_index = {
85 .name = "cpu_common/exception_index",
86 .version_id = 1,
87 .minimum_version_id = 1,
88 .needed = cpu_common_exception_index_needed,
89 .fields = (VMStateField[]) {
90 VMSTATE_INT32(exception_index, CPUState),
91 VMSTATE_END_OF_LIST()
95 static bool cpu_common_crash_occurred_needed(void *opaque)
97 CPUState *cpu = opaque;
99 return cpu->crash_occurred;
102 static const VMStateDescription vmstate_cpu_common_crash_occurred = {
103 .name = "cpu_common/crash_occurred",
104 .version_id = 1,
105 .minimum_version_id = 1,
106 .needed = cpu_common_crash_occurred_needed,
107 .fields = (VMStateField[]) {
108 VMSTATE_BOOL(crash_occurred, CPUState),
109 VMSTATE_END_OF_LIST()
113 const VMStateDescription vmstate_cpu_common = {
114 .name = "cpu_common",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .pre_load = cpu_common_pre_load,
118 .post_load = cpu_common_post_load,
119 .fields = (VMStateField[]) {
120 VMSTATE_UINT32(halted, CPUState),
121 VMSTATE_UINT32(interrupt_request, CPUState),
122 VMSTATE_END_OF_LIST()
124 .subsections = (const VMStateDescription*[]) {
125 &vmstate_cpu_common_exception_index,
126 &vmstate_cpu_common_crash_occurred,
127 NULL
130 #endif
132 void cpu_exec_realizefn(CPUState *cpu, Error **errp)
134 #ifndef CONFIG_USER_ONLY
135 CPUClass *cc = CPU_GET_CLASS(cpu);
136 #endif
138 cpu_list_add(cpu);
139 if (!accel_cpu_realizefn(cpu, errp)) {
140 return;
142 /* NB: errp parameter is unused currently */
143 if (tcg_enabled()) {
144 tcg_exec_realizefn(cpu, errp);
147 #ifdef CONFIG_USER_ONLY
148 assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
149 qdev_get_vmsd(DEVICE(cpu))->unmigratable);
150 #else
151 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
152 vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
154 if (cc->sysemu_ops->legacy_vmsd != NULL) {
155 vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
157 #endif /* CONFIG_USER_ONLY */
160 void cpu_exec_unrealizefn(CPUState *cpu)
162 #ifndef CONFIG_USER_ONLY
163 CPUClass *cc = CPU_GET_CLASS(cpu);
165 if (cc->sysemu_ops->legacy_vmsd != NULL) {
166 vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
168 if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
169 vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
171 #endif
172 if (tcg_enabled()) {
173 tcg_exec_unrealizefn(cpu);
176 cpu_list_remove(cpu);
180 * This can't go in hw/core/cpu.c because that file is compiled only
181 * once for both user-mode and system builds.
183 static Property cpu_common_props[] = {
184 #ifdef CONFIG_USER_ONLY
186 * Create a property for the user-only object, so users can
187 * adjust prctl(PR_SET_UNALIGN) from the command-line.
188 * Has no effect if the target does not support the feature.
190 DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
191 prctl_unalign_sigbus, false),
192 #else
194 * Create a memory property for softmmu CPU object, so users can
195 * wire up its memory. The default if no link is set up is to use
196 * the system address space.
198 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
199 MemoryRegion *),
200 #endif
201 DEFINE_PROP_END_OF_LIST(),
204 static bool cpu_get_start_powered_off(Object *obj, Error **errp)
206 CPUState *cpu = CPU(obj);
207 return cpu->start_powered_off;
210 static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
212 CPUState *cpu = CPU(obj);
213 cpu->start_powered_off = value;
216 void cpu_class_init_props(DeviceClass *dc)
218 ObjectClass *oc = OBJECT_CLASS(dc);
220 device_class_set_props(dc, cpu_common_props);
222 * We can't use DEFINE_PROP_BOOL in the Property array for this
223 * property, because we want this to be settable after realize.
225 object_class_property_add_bool(oc, "start-powered-off",
226 cpu_get_start_powered_off,
227 cpu_set_start_powered_off);
230 void cpu_exec_initfn(CPUState *cpu)
232 cpu->as = NULL;
233 cpu->num_ases = 0;
235 #ifndef CONFIG_USER_ONLY
236 cpu->thread_id = qemu_get_thread_id();
237 cpu->memory = get_system_memory();
238 object_ref(OBJECT(cpu->memory));
239 #endif
242 const char *parse_cpu_option(const char *cpu_option)
244 ObjectClass *oc;
245 CPUClass *cc;
246 gchar **model_pieces;
247 const char *cpu_type;
249 model_pieces = g_strsplit(cpu_option, ",", 2);
250 if (!model_pieces[0]) {
251 error_report("-cpu option cannot be empty");
252 exit(1);
255 oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
256 if (oc == NULL) {
257 error_report("unable to find CPU model '%s'", model_pieces[0]);
258 g_strfreev(model_pieces);
259 exit(EXIT_FAILURE);
262 cpu_type = object_class_get_name(oc);
263 cc = CPU_CLASS(oc);
264 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
265 g_strfreev(model_pieces);
266 return cpu_type;
269 #if defined(CONFIG_USER_ONLY)
270 void tb_invalidate_phys_addr(target_ulong addr)
272 mmap_lock();
273 tb_invalidate_phys_page_range(addr, addr + 1);
274 mmap_unlock();
276 #else
277 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
279 ram_addr_t ram_addr;
280 MemoryRegion *mr;
281 hwaddr l = 1;
283 if (!tcg_enabled()) {
284 return;
287 RCU_READ_LOCK_GUARD();
288 mr = address_space_translate(as, addr, &addr, &l, false, attrs);
289 if (!(memory_region_is_ram(mr)
290 || memory_region_is_romd(mr))) {
291 return;
293 ram_addr = memory_region_get_ram_addr(mr) + addr;
294 tb_invalidate_phys_page_range(ram_addr, ram_addr + 1);
296 #endif
298 /* Add a breakpoint. */
299 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
300 CPUBreakpoint **breakpoint)
302 CPUClass *cc = CPU_GET_CLASS(cpu);
303 CPUBreakpoint *bp;
305 if (cc->gdb_adjust_breakpoint) {
306 pc = cc->gdb_adjust_breakpoint(cpu, pc);
309 bp = g_malloc(sizeof(*bp));
311 bp->pc = pc;
312 bp->flags = flags;
314 /* keep all GDB-injected breakpoints in front */
315 if (flags & BP_GDB) {
316 QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
317 } else {
318 QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
321 if (breakpoint) {
322 *breakpoint = bp;
325 trace_breakpoint_insert(cpu->cpu_index, pc, flags);
326 return 0;
329 /* Remove a specific breakpoint. */
330 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
332 CPUClass *cc = CPU_GET_CLASS(cpu);
333 CPUBreakpoint *bp;
335 if (cc->gdb_adjust_breakpoint) {
336 pc = cc->gdb_adjust_breakpoint(cpu, pc);
339 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
340 if (bp->pc == pc && bp->flags == flags) {
341 cpu_breakpoint_remove_by_ref(cpu, bp);
342 return 0;
345 return -ENOENT;
348 /* Remove a specific breakpoint by reference. */
349 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp)
351 QTAILQ_REMOVE(&cpu->breakpoints, bp, entry);
353 trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags);
354 g_free(bp);
357 /* Remove all matching breakpoints. */
358 void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
360 CPUBreakpoint *bp, *next;
362 QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
363 if (bp->flags & mask) {
364 cpu_breakpoint_remove_by_ref(cpu, bp);
369 /* enable or disable single step mode. EXCP_DEBUG is returned by the
370 CPU loop after each instruction */
371 void cpu_single_step(CPUState *cpu, int enabled)
373 if (cpu->singlestep_enabled != enabled) {
374 cpu->singlestep_enabled = enabled;
375 if (kvm_enabled()) {
376 kvm_update_guest_debug(cpu, 0);
378 trace_breakpoint_singlestep(cpu->cpu_index, enabled);
382 void cpu_abort(CPUState *cpu, const char *fmt, ...)
384 va_list ap;
385 va_list ap2;
387 va_start(ap, fmt);
388 va_copy(ap2, ap);
389 fprintf(stderr, "qemu: fatal: ");
390 vfprintf(stderr, fmt, ap);
391 fprintf(stderr, "\n");
392 cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
393 if (qemu_log_separate()) {
394 FILE *logfile = qemu_log_lock();
395 qemu_log("qemu: fatal: ");
396 qemu_log_vprintf(fmt, ap2);
397 qemu_log("\n");
398 log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP);
399 qemu_log_flush();
400 qemu_log_unlock(logfile);
401 qemu_log_close();
403 va_end(ap2);
404 va_end(ap);
405 replay_finish();
406 #if defined(CONFIG_USER_ONLY)
408 struct sigaction act;
409 sigfillset(&act.sa_mask);
410 act.sa_handler = SIG_DFL;
411 act.sa_flags = 0;
412 sigaction(SIGABRT, &act, NULL);
414 #endif
415 abort();
418 /* physical memory access (slow version, mainly for debug) */
419 #if defined(CONFIG_USER_ONLY)
420 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
421 void *ptr, size_t len, bool is_write)
423 int flags;
424 vaddr l, page;
425 void * p;
426 uint8_t *buf = ptr;
428 while (len > 0) {
429 page = addr & TARGET_PAGE_MASK;
430 l = (page + TARGET_PAGE_SIZE) - addr;
431 if (l > len)
432 l = len;
433 flags = page_get_flags(page);
434 if (!(flags & PAGE_VALID))
435 return -1;
436 if (is_write) {
437 if (!(flags & PAGE_WRITE))
438 return -1;
439 /* XXX: this code should not depend on lock_user */
440 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
441 return -1;
442 memcpy(p, buf, l);
443 unlock_user(p, addr, l);
444 } else {
445 if (!(flags & PAGE_READ))
446 return -1;
447 /* XXX: this code should not depend on lock_user */
448 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
449 return -1;
450 memcpy(buf, p, l);
451 unlock_user(p, addr, 0);
453 len -= l;
454 buf += l;
455 addr += l;
457 return 0;
459 #endif
461 bool target_words_bigendian(void)
463 #if defined(TARGET_WORDS_BIGENDIAN)
464 return true;
465 #else
466 return false;
467 #endif
470 void page_size_init(void)
472 /* NOTE: we can always suppose that qemu_host_page_size >=
473 TARGET_PAGE_SIZE */
474 if (qemu_host_page_size == 0) {
475 qemu_host_page_size = qemu_real_host_page_size;
477 if (qemu_host_page_size < TARGET_PAGE_SIZE) {
478 qemu_host_page_size = TARGET_PAGE_SIZE;
480 qemu_host_page_mask = -(intptr_t)qemu_host_page_size;