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arm-dis: Include opcode hex when doing disassembly
[qemu.git] / hw / fdc.c
blob4bbcc4715f9e4fcd7962344229ac6a74e0b95827
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskType {
67 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
68 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
69 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
70 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
71 FDRIVE_DISK_NONE = 0x05, /* No disk */
72 } FDiskType;
73
74 typedef enum FDriveType {
75 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
76 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
77 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
78 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
79 } FDriveType;
80
81 typedef enum FDiskFlags {
82 FDISK_DBL_SIDES = 0x01,
83 } FDiskFlags;
84
85 typedef struct FDrive {
86 BlockDriverState *bs;
87 /* Drive status */
88 FDriveType drive;
89 uint8_t perpendicular; /* 2.88 MB access mode */
90 /* Position */
91 uint8_t head;
92 uint8_t track;
93 uint8_t sect;
94 /* Media */
95 FDiskFlags flags;
96 uint8_t last_sect; /* Nb sector per track */
97 uint8_t max_track; /* Nb of tracks */
98 uint16_t bps; /* Bytes per sector */
99 uint8_t ro; /* Is read-only */
100 } FDrive;
101
102 static void fd_init(FDrive *drv)
103 {
104 /* Drive */
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->perpendicular = 0;
107 /* Disk */
108 drv->last_sect = 0;
109 drv->max_track = 0;
110 }
111
112 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
113 uint8_t last_sect)
114 {
115 return (((track * 2) + head) * last_sect) + sect - 1;
116 }
117
118 /* Returns current position, in sectors, for given drive */
119 static int fd_sector(FDrive *drv)
120 {
121 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
122 }
123
124 /* Seek to a new position:
125 * returns 0 if already on right track
126 * returns 1 if track changed
127 * returns 2 if track is invalid
128 * returns 3 if sector is invalid
129 * returns 4 if seek is disabled
130 */
131 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
132 int enable_seek)
133 {
134 uint32_t sector;
135 int ret;
136
137 if (track > drv->max_track ||
138 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 2;
144 }
145 if (sect > drv->last_sect) {
146 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
147 head, track, sect, 1,
148 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
149 drv->max_track, drv->last_sect);
150 return 3;
151 }
152 sector = fd_sector_calc(head, track, sect, drv->last_sect);
153 ret = 0;
154 if (sector != fd_sector(drv)) {
155 #if 0
156 if (!enable_seek) {
157 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
158 head, track, sect, 1, drv->max_track, drv->last_sect);
159 return 4;
160 }
161 #endif
162 drv->head = head;
163 if (drv->track != track)
164 ret = 1;
165 drv->track = track;
166 drv->sect = sect;
167 }
168
169 return ret;
170 }
171
172 /* Set drive back to track 0 */
173 static void fd_recalibrate(FDrive *drv)
174 {
175 FLOPPY_DPRINTF("recalibrate\n");
176 drv->head = 0;
177 drv->track = 0;
178 drv->sect = 1;
179 }
180
181 /* Recognize floppy formats */
182 typedef struct FDFormat {
183 FDriveType drive;
184 FDiskType disk;
185 uint8_t last_sect;
186 uint8_t max_track;
187 uint8_t max_head;
188 const char *str;
189 } FDFormat;
190
191 static const FDFormat fd_formats[] = {
192 /* First entry is default format */
193 /* 1.44 MB 3"1/2 floppy disks */
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
201 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
202 /* 2.88 MB 3"1/2 floppy disks */
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
207 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
208 /* 720 kB 3"1/2 floppy disks */
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
214 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
215 /* 1.2 MB 5"1/4 floppy disks */
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
221 /* 720 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
224 /* 360 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
229 /* 320 kB 5"1/4 floppy disks */
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
231 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
232 /* 360 kB must match 5"1/4 better than 3"1/2... */
233 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
234 /* end */
235 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 };
237
238 /* Revalidate a disk drive after a disk change */
239 static void fd_revalidate(FDrive *drv)
240 {
241 const FDFormat *parse;
242 uint64_t nb_sectors, size;
243 int i, first_match, match;
244 int nb_heads, max_track, last_sect, ro;
245
246 FLOPPY_DPRINTF("revalidate\n");
247 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
248 ro = bdrv_is_read_only(drv->bs);
249 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
250 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
251 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 nb_heads - 1, max_track, last_sect);
253 } else {
254 bdrv_get_geometry(drv->bs, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0;; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FDRIVE_DRV_NONE)
260 break;
261 if (drv->drive == parse->drive ||
262 drv->drive == FDRIVE_DRV_NONE) {
263 size = (parse->max_head + 1) * parse->max_track *
264 parse->last_sect;
265 if (nb_sectors == size) {
266 match = i;
267 break;
268 }
269 if (first_match == -1)
270 first_match = i;
271 }
272 }
273 if (match == -1) {
274 if (first_match == -1)
275 match = 1;
276 else
277 match = first_match;
278 parse = &fd_formats[match];
279 }
280 nb_heads = parse->max_head + 1;
281 max_track = parse->max_track;
282 last_sect = parse->last_sect;
283 drv->drive = parse->drive;
284 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
285 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
286 }
287 if (nb_heads == 1) {
288 drv->flags &= ~FDISK_DBL_SIDES;
289 } else {
290 drv->flags |= FDISK_DBL_SIDES;
291 }
292 drv->max_track = max_track;
293 drv->last_sect = last_sect;
294 drv->ro = ro;
295 } else {
296 FLOPPY_DPRINTF("No disk in drive\n");
297 drv->last_sect = 0;
298 drv->max_track = 0;
299 drv->flags &= ~FDISK_DBL_SIDES;
300 }
301 }
302
303 /********************************************************/
304 /* Intel 82078 floppy disk controller emulation */
305
306 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
307 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
308 static int fdctrl_transfer_handler (void *opaque, int nchan,
309 int dma_pos, int dma_len);
310 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
311
312 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
313 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
314 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
315 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
317 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
319 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
321 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
322 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
323
324 enum {
325 FD_DIR_WRITE = 0,
326 FD_DIR_READ = 1,
327 FD_DIR_SCANE = 2,
328 FD_DIR_SCANL = 3,
329 FD_DIR_SCANH = 4,
330 };
331
332 enum {
333 FD_STATE_MULTI = 0x01, /* multi track flag */
334 FD_STATE_FORMAT = 0x02, /* format flag */
335 FD_STATE_SEEK = 0x04, /* seek flag */
336 };
337
338 enum {
339 FD_REG_SRA = 0x00,
340 FD_REG_SRB = 0x01,
341 FD_REG_DOR = 0x02,
342 FD_REG_TDR = 0x03,
343 FD_REG_MSR = 0x04,
344 FD_REG_DSR = 0x04,
345 FD_REG_FIFO = 0x05,
346 FD_REG_DIR = 0x07,
347 };
348
349 enum {
350 FD_CMD_READ_TRACK = 0x02,
351 FD_CMD_SPECIFY = 0x03,
352 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 FD_CMD_WRITE = 0x05,
354 FD_CMD_READ = 0x06,
355 FD_CMD_RECALIBRATE = 0x07,
356 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 FD_CMD_WRITE_DELETED = 0x09,
358 FD_CMD_READ_ID = 0x0a,
359 FD_CMD_READ_DELETED = 0x0c,
360 FD_CMD_FORMAT_TRACK = 0x0d,
361 FD_CMD_DUMPREG = 0x0e,
362 FD_CMD_SEEK = 0x0f,
363 FD_CMD_VERSION = 0x10,
364 FD_CMD_SCAN_EQUAL = 0x11,
365 FD_CMD_PERPENDICULAR_MODE = 0x12,
366 FD_CMD_CONFIGURE = 0x13,
367 FD_CMD_LOCK = 0x14,
368 FD_CMD_VERIFY = 0x16,
369 FD_CMD_POWERDOWN_MODE = 0x17,
370 FD_CMD_PART_ID = 0x18,
371 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 FD_CMD_SAVE = 0x2e,
374 FD_CMD_OPTION = 0x33,
375 FD_CMD_RESTORE = 0x4e,
376 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 };
381
382 enum {
383 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 FD_CONFIG_POLL = 0x10, /* Poll enabled */
386 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 FD_CONFIG_EIS = 0x40, /* No implied seeks */
388 };
389
390 enum {
391 FD_SR0_EQPMT = 0x10,
392 FD_SR0_SEEK = 0x20,
393 FD_SR0_ABNTERM = 0x40,
394 FD_SR0_INVCMD = 0x80,
395 FD_SR0_RDYCHG = 0xc0,
396 };
397
398 enum {
399 FD_SR1_EC = 0x80, /* End of cylinder */
400 };
401
402 enum {
403 FD_SR2_SNS = 0x04, /* Scan not satisfied */
404 FD_SR2_SEH = 0x08, /* Scan equal hit */
405 };
406
407 enum {
408 FD_SRA_DIR = 0x01,
409 FD_SRA_nWP = 0x02,
410 FD_SRA_nINDX = 0x04,
411 FD_SRA_HDSEL = 0x08,
412 FD_SRA_nTRK0 = 0x10,
413 FD_SRA_STEP = 0x20,
414 FD_SRA_nDRV2 = 0x40,
415 FD_SRA_INTPEND = 0x80,
416 };
417
418 enum {
419 FD_SRB_MTR0 = 0x01,
420 FD_SRB_MTR1 = 0x02,
421 FD_SRB_WGATE = 0x04,
422 FD_SRB_RDATA = 0x08,
423 FD_SRB_WDATA = 0x10,
424 FD_SRB_DR0 = 0x20,
425 };
426
427 enum {
428 #if MAX_FD == 4
429 FD_DOR_SELMASK = 0x03,
430 #else
431 FD_DOR_SELMASK = 0x01,
432 #endif
433 FD_DOR_nRESET = 0x04,
434 FD_DOR_DMAEN = 0x08,
435 FD_DOR_MOTEN0 = 0x10,
436 FD_DOR_MOTEN1 = 0x20,
437 FD_DOR_MOTEN2 = 0x40,
438 FD_DOR_MOTEN3 = 0x80,
439 };
440
441 enum {
442 #if MAX_FD == 4
443 FD_TDR_BOOTSEL = 0x0c,
444 #else
445 FD_TDR_BOOTSEL = 0x04,
446 #endif
447 };
448
449 enum {
450 FD_DSR_DRATEMASK= 0x03,
451 FD_DSR_PWRDOWN = 0x40,
452 FD_DSR_SWRESET = 0x80,
453 };
454
455 enum {
456 FD_MSR_DRV0BUSY = 0x01,
457 FD_MSR_DRV1BUSY = 0x02,
458 FD_MSR_DRV2BUSY = 0x04,
459 FD_MSR_DRV3BUSY = 0x08,
460 FD_MSR_CMDBUSY = 0x10,
461 FD_MSR_NONDMA = 0x20,
462 FD_MSR_DIO = 0x40,
463 FD_MSR_RQM = 0x80,
464 };
465
466 enum {
467 FD_DIR_DSKCHG = 0x80,
468 };
469
470 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473
474 struct FDCtrl {
475 /* Controller's identification */
476 uint8_t version;
477 /* HW */
478 qemu_irq irq;
479 int dma_chann;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t dor_vmstate; /* only used as temp during vmstate */
486 uint8_t tdr;
487 uint8_t dsr;
488 uint8_t msr;
489 uint8_t cur_drv;
490 uint8_t status0;
491 uint8_t status1;
492 uint8_t status2;
493 /* Command FIFO */
494 uint8_t *fifo;
495 int32_t fifo_size;
496 uint32_t data_pos;
497 uint32_t data_len;
498 uint8_t data_state;
499 uint8_t data_dir;
500 uint8_t eot; /* last wanted sector */
501 /* States kept only to be returned back */
502 /* Timers state */
503 uint8_t timer0;
504 uint8_t timer1;
505 /* precompensation */
506 uint8_t precomp_trk;
507 uint8_t config;
508 uint8_t lock;
509 /* Power down config (also with status regB access mode */
510 uint8_t pwrd;
511 /* Sun4m quirks? */
512 int sun4m;
513 /* Floppy drives */
514 uint8_t num_floppies;
515 FDrive drives[MAX_FD];
516 int reset_sensei;
517 };
518
519 typedef struct FDCtrlSysBus {
520 SysBusDevice busdev;
521 struct FDCtrl state;
522 } FDCtrlSysBus;
523
524 typedef struct FDCtrlISABus {
525 ISADevice busdev;
526 struct FDCtrl state;
527 int32_t bootindexA;
528 int32_t bootindexB;
529 } FDCtrlISABus;
530
531 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
532 {
533 FDCtrl *fdctrl = opaque;
534 uint32_t retval;
535
536 switch (reg) {
537 case FD_REG_SRA:
538 retval = fdctrl_read_statusA(fdctrl);
539 break;
540 case FD_REG_SRB:
541 retval = fdctrl_read_statusB(fdctrl);
542 break;
543 case FD_REG_DOR:
544 retval = fdctrl_read_dor(fdctrl);
545 break;
546 case FD_REG_TDR:
547 retval = fdctrl_read_tape(fdctrl);
548 break;
549 case FD_REG_MSR:
550 retval = fdctrl_read_main_status(fdctrl);
551 break;
552 case FD_REG_FIFO:
553 retval = fdctrl_read_data(fdctrl);
554 break;
555 case FD_REG_DIR:
556 retval = fdctrl_read_dir(fdctrl);
557 break;
558 default:
559 retval = (uint32_t)(-1);
560 break;
561 }
562 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
563
564 return retval;
565 }
566
567 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
568 {
569 FDCtrl *fdctrl = opaque;
570
571 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
572
573 switch (reg) {
574 case FD_REG_DOR:
575 fdctrl_write_dor(fdctrl, value);
576 break;
577 case FD_REG_TDR:
578 fdctrl_write_tape(fdctrl, value);
579 break;
580 case FD_REG_DSR:
581 fdctrl_write_rate(fdctrl, value);
582 break;
583 case FD_REG_FIFO:
584 fdctrl_write_data(fdctrl, value);
585 break;
586 default:
587 break;
588 }
589 }
590
591 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
592 {
593 return fdctrl_read(opaque, reg & 7);
594 }
595
596 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
597 {
598 fdctrl_write(opaque, reg & 7, value);
599 }
600
601 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
602 {
603 return fdctrl_read(opaque, (uint32_t)reg);
604 }
605
606 static void fdctrl_write_mem (void *opaque,
607 target_phys_addr_t reg, uint32_t value)
608 {
609 fdctrl_write(opaque, (uint32_t)reg, value);
610 }
611
612 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
613 fdctrl_read_mem,
614 fdctrl_read_mem,
615 fdctrl_read_mem,
616 };
617
618 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
619 fdctrl_write_mem,
620 fdctrl_write_mem,
621 fdctrl_write_mem,
622 };
623
624 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
625 fdctrl_read_mem,
626 NULL,
627 NULL,
628 };
629
630 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
631 fdctrl_write_mem,
632 NULL,
633 NULL,
634 };
635
636 static const VMStateDescription vmstate_fdrive = {
637 .name = "fdrive",
638 .version_id = 1,
639 .minimum_version_id = 1,
640 .minimum_version_id_old = 1,
641 .fields = (VMStateField []) {
642 VMSTATE_UINT8(head, FDrive),
643 VMSTATE_UINT8(track, FDrive),
644 VMSTATE_UINT8(sect, FDrive),
645 VMSTATE_END_OF_LIST()
646 }
647 };
648
649 static void fdc_pre_save(void *opaque)
650 {
651 FDCtrl *s = opaque;
652
653 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
654 }
655
656 static int fdc_post_load(void *opaque, int version_id)
657 {
658 FDCtrl *s = opaque;
659
660 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
661 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
662 return 0;
663 }
664
665 static const VMStateDescription vmstate_fdc = {
666 .name = "fdc",
667 .version_id = 2,
668 .minimum_version_id = 2,
669 .minimum_version_id_old = 2,
670 .pre_save = fdc_pre_save,
671 .post_load = fdc_post_load,
672 .fields = (VMStateField []) {
673 /* Controller State */
674 VMSTATE_UINT8(sra, FDCtrl),
675 VMSTATE_UINT8(srb, FDCtrl),
676 VMSTATE_UINT8(dor_vmstate, FDCtrl),
677 VMSTATE_UINT8(tdr, FDCtrl),
678 VMSTATE_UINT8(dsr, FDCtrl),
679 VMSTATE_UINT8(msr, FDCtrl),
680 VMSTATE_UINT8(status0, FDCtrl),
681 VMSTATE_UINT8(status1, FDCtrl),
682 VMSTATE_UINT8(status2, FDCtrl),
683 /* Command FIFO */
684 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
685 uint8_t),
686 VMSTATE_UINT32(data_pos, FDCtrl),
687 VMSTATE_UINT32(data_len, FDCtrl),
688 VMSTATE_UINT8(data_state, FDCtrl),
689 VMSTATE_UINT8(data_dir, FDCtrl),
690 VMSTATE_UINT8(eot, FDCtrl),
691 /* States kept only to be returned back */
692 VMSTATE_UINT8(timer0, FDCtrl),
693 VMSTATE_UINT8(timer1, FDCtrl),
694 VMSTATE_UINT8(precomp_trk, FDCtrl),
695 VMSTATE_UINT8(config, FDCtrl),
696 VMSTATE_UINT8(lock, FDCtrl),
697 VMSTATE_UINT8(pwrd, FDCtrl),
698 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
699 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
700 vmstate_fdrive, FDrive),
701 VMSTATE_END_OF_LIST()
702 }
703 };
704
705 static void fdctrl_external_reset_sysbus(DeviceState *d)
706 {
707 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
708 FDCtrl *s = &sys->state;
709
710 fdctrl_reset(s, 0);
711 }
712
713 static void fdctrl_external_reset_isa(DeviceState *d)
714 {
715 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
716 FDCtrl *s = &isa->state;
717
718 fdctrl_reset(s, 0);
719 }
720
721 static void fdctrl_handle_tc(void *opaque, int irq, int level)
722 {
723 //FDCtrl *s = opaque;
724
725 if (level) {
726 // XXX
727 FLOPPY_DPRINTF("TC pulsed\n");
728 }
729 }
730
731 /* XXX: may change if moved to bdrv */
732 int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
733 {
734 return fdctrl->drives[drive_num].drive;
735 }
736
737 /* Change IRQ state */
738 static void fdctrl_reset_irq(FDCtrl *fdctrl)
739 {
740 if (!(fdctrl->sra & FD_SRA_INTPEND))
741 return;
742 FLOPPY_DPRINTF("Reset interrupt\n");
743 qemu_set_irq(fdctrl->irq, 0);
744 fdctrl->sra &= ~FD_SRA_INTPEND;
745 }
746
747 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
748 {
749 /* Sparc mutation */
750 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
751 /* XXX: not sure */
752 fdctrl->msr &= ~FD_MSR_CMDBUSY;
753 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
754 fdctrl->status0 = status0;
755 return;
756 }
757 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
758 qemu_set_irq(fdctrl->irq, 1);
759 fdctrl->sra |= FD_SRA_INTPEND;
760 }
761 fdctrl->reset_sensei = 0;
762 fdctrl->status0 = status0;
763 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
764 }
765
766 /* Reset controller */
767 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
768 {
769 int i;
770
771 FLOPPY_DPRINTF("reset controller\n");
772 fdctrl_reset_irq(fdctrl);
773 /* Initialise controller */
774 fdctrl->sra = 0;
775 fdctrl->srb = 0xc0;
776 if (!fdctrl->drives[1].bs)
777 fdctrl->sra |= FD_SRA_nDRV2;
778 fdctrl->cur_drv = 0;
779 fdctrl->dor = FD_DOR_nRESET;
780 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
781 fdctrl->msr = FD_MSR_RQM;
782 /* FIFO state */
783 fdctrl->data_pos = 0;
784 fdctrl->data_len = 0;
785 fdctrl->data_state = 0;
786 fdctrl->data_dir = FD_DIR_WRITE;
787 for (i = 0; i < MAX_FD; i++)
788 fd_recalibrate(&fdctrl->drives[i]);
789 fdctrl_reset_fifo(fdctrl);
790 if (do_irq) {
791 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
792 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
793 }
794 }
795
796 static inline FDrive *drv0(FDCtrl *fdctrl)
797 {
798 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
799 }
800
801 static inline FDrive *drv1(FDCtrl *fdctrl)
802 {
803 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
804 return &fdctrl->drives[1];
805 else
806 return &fdctrl->drives[0];
807 }
808
809 #if MAX_FD == 4
810 static inline FDrive *drv2(FDCtrl *fdctrl)
811 {
812 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
813 return &fdctrl->drives[2];
814 else
815 return &fdctrl->drives[1];
816 }
817
818 static inline FDrive *drv3(FDCtrl *fdctrl)
819 {
820 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
821 return &fdctrl->drives[3];
822 else
823 return &fdctrl->drives[2];
824 }
825 #endif
826
827 static FDrive *get_cur_drv(FDCtrl *fdctrl)
828 {
829 switch (fdctrl->cur_drv) {
830 case 0: return drv0(fdctrl);
831 case 1: return drv1(fdctrl);
832 #if MAX_FD == 4
833 case 2: return drv2(fdctrl);
834 case 3: return drv3(fdctrl);
835 #endif
836 default: return NULL;
837 }
838 }
839
840 /* Status A register : 0x00 (read-only) */
841 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
842 {
843 uint32_t retval = fdctrl->sra;
844
845 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
846
847 return retval;
848 }
849
850 /* Status B register : 0x01 (read-only) */
851 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
852 {
853 uint32_t retval = fdctrl->srb;
854
855 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
856
857 return retval;
858 }
859
860 /* Digital output register : 0x02 */
861 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
862 {
863 uint32_t retval = fdctrl->dor;
864
865 /* Selected drive */
866 retval |= fdctrl->cur_drv;
867 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
868
869 return retval;
870 }
871
872 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
873 {
874 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
875
876 /* Motors */
877 if (value & FD_DOR_MOTEN0)
878 fdctrl->srb |= FD_SRB_MTR0;
879 else
880 fdctrl->srb &= ~FD_SRB_MTR0;
881 if (value & FD_DOR_MOTEN1)
882 fdctrl->srb |= FD_SRB_MTR1;
883 else
884 fdctrl->srb &= ~FD_SRB_MTR1;
885
886 /* Drive */
887 if (value & 1)
888 fdctrl->srb |= FD_SRB_DR0;
889 else
890 fdctrl->srb &= ~FD_SRB_DR0;
891
892 /* Reset */
893 if (!(value & FD_DOR_nRESET)) {
894 if (fdctrl->dor & FD_DOR_nRESET) {
895 FLOPPY_DPRINTF("controller enter RESET state\n");
896 }
897 } else {
898 if (!(fdctrl->dor & FD_DOR_nRESET)) {
899 FLOPPY_DPRINTF("controller out of RESET state\n");
900 fdctrl_reset(fdctrl, 1);
901 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
902 }
903 }
904 /* Selected drive */
905 fdctrl->cur_drv = value & FD_DOR_SELMASK;
906
907 fdctrl->dor = value;
908 }
909
910 /* Tape drive register : 0x03 */
911 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
912 {
913 uint32_t retval = fdctrl->tdr;
914
915 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
916
917 return retval;
918 }
919
920 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
921 {
922 /* Reset mode */
923 if (!(fdctrl->dor & FD_DOR_nRESET)) {
924 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
925 return;
926 }
927 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
928 /* Disk boot selection indicator */
929 fdctrl->tdr = value & FD_TDR_BOOTSEL;
930 /* Tape indicators: never allow */
931 }
932
933 /* Main status register : 0x04 (read) */
934 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
935 {
936 uint32_t retval = fdctrl->msr;
937
938 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
939 fdctrl->dor |= FD_DOR_nRESET;
940
941 /* Sparc mutation */
942 if (fdctrl->sun4m) {
943 retval |= FD_MSR_DIO;
944 fdctrl_reset_irq(fdctrl);
945 };
946
947 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
948
949 return retval;
950 }
951
952 /* Data select rate register : 0x04 (write) */
953 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
954 {
955 /* Reset mode */
956 if (!(fdctrl->dor & FD_DOR_nRESET)) {
957 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
958 return;
959 }
960 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
961 /* Reset: autoclear */
962 if (value & FD_DSR_SWRESET) {
963 fdctrl->dor &= ~FD_DOR_nRESET;
964 fdctrl_reset(fdctrl, 1);
965 fdctrl->dor |= FD_DOR_nRESET;
966 }
967 if (value & FD_DSR_PWRDOWN) {
968 fdctrl_reset(fdctrl, 1);
969 }
970 fdctrl->dsr = value;
971 }
972
973 static int fdctrl_media_changed(FDrive *drv)
974 {
975 int ret;
976
977 if (!drv->bs)
978 return 0;
979 ret = bdrv_media_changed(drv->bs);
980 if (ret) {
981 fd_revalidate(drv);
982 }
983 return ret;
984 }
985
986 /* Digital input register : 0x07 (read-only) */
987 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
988 {
989 uint32_t retval = 0;
990
991 if (fdctrl_media_changed(drv0(fdctrl))
992 || fdctrl_media_changed(drv1(fdctrl))
993 #if MAX_FD == 4
994 || fdctrl_media_changed(drv2(fdctrl))
995 || fdctrl_media_changed(drv3(fdctrl))
996 #endif
997 )
998 retval |= FD_DIR_DSKCHG;
999 if (retval != 0) {
1000 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1001 }
1002
1003 return retval;
1004 }
1005
1006 /* FIFO state control */
1007 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
1008 {
1009 fdctrl->data_dir = FD_DIR_WRITE;
1010 fdctrl->data_pos = 0;
1011 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1012 }
1013
1014 /* Set FIFO status for the host to read */
1015 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
1016 {
1017 fdctrl->data_dir = FD_DIR_READ;
1018 fdctrl->data_len = fifo_len;
1019 fdctrl->data_pos = 0;
1020 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1021 if (do_irq)
1022 fdctrl_raise_irq(fdctrl, 0x00);
1023 }
1024
1025 /* Set an error: unimplemented/unknown command */
1026 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1027 {
1028 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1029 fdctrl->fifo[0] = FD_SR0_INVCMD;
1030 fdctrl_set_fifo(fdctrl, 1, 0);
1031 }
1032
1033 /* Seek to next sector */
1034 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1035 {
1036 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1037 cur_drv->head, cur_drv->track, cur_drv->sect,
1038 fd_sector(cur_drv));
1039 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1040 error in fact */
1041 if (cur_drv->sect >= cur_drv->last_sect ||
1042 cur_drv->sect == fdctrl->eot) {
1043 cur_drv->sect = 1;
1044 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1045 if (cur_drv->head == 0 &&
1046 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1047 cur_drv->head = 1;
1048 } else {
1049 cur_drv->head = 0;
1050 cur_drv->track++;
1051 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1052 return 0;
1053 }
1054 } else {
1055 cur_drv->track++;
1056 return 0;
1057 }
1058 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1059 cur_drv->head, cur_drv->track,
1060 cur_drv->sect, fd_sector(cur_drv));
1061 } else {
1062 cur_drv->sect++;
1063 }
1064 return 1;
1065 }
1066
1067 /* Callback for transfer end (stop or abort) */
1068 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1069 uint8_t status1, uint8_t status2)
1070 {
1071 FDrive *cur_drv;
1072
1073 cur_drv = get_cur_drv(fdctrl);
1074 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1075 status0, status1, status2,
1076 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1077 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1078 fdctrl->fifo[1] = status1;
1079 fdctrl->fifo[2] = status2;
1080 fdctrl->fifo[3] = cur_drv->track;
1081 fdctrl->fifo[4] = cur_drv->head;
1082 fdctrl->fifo[5] = cur_drv->sect;
1083 fdctrl->fifo[6] = FD_SECTOR_SC;
1084 fdctrl->data_dir = FD_DIR_READ;
1085 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1086 DMA_release_DREQ(fdctrl->dma_chann);
1087 }
1088 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1089 fdctrl->msr &= ~FD_MSR_NONDMA;
1090 fdctrl_set_fifo(fdctrl, 7, 1);
1091 }
1092
1093 /* Prepare a data transfer (either DMA or FIFO) */
1094 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1095 {
1096 FDrive *cur_drv;
1097 uint8_t kh, kt, ks;
1098 int did_seek = 0;
1099
1100 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1101 cur_drv = get_cur_drv(fdctrl);
1102 kt = fdctrl->fifo[2];
1103 kh = fdctrl->fifo[3];
1104 ks = fdctrl->fifo[4];
1105 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1106 GET_CUR_DRV(fdctrl), kh, kt, ks,
1107 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1108 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1109 case 2:
1110 /* sect too big */
1111 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1112 fdctrl->fifo[3] = kt;
1113 fdctrl->fifo[4] = kh;
1114 fdctrl->fifo[5] = ks;
1115 return;
1116 case 3:
1117 /* track too big */
1118 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1119 fdctrl->fifo[3] = kt;
1120 fdctrl->fifo[4] = kh;
1121 fdctrl->fifo[5] = ks;
1122 return;
1123 case 4:
1124 /* No seek enabled */
1125 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1126 fdctrl->fifo[3] = kt;
1127 fdctrl->fifo[4] = kh;
1128 fdctrl->fifo[5] = ks;
1129 return;
1130 case 1:
1131 did_seek = 1;
1132 break;
1133 default:
1134 break;
1135 }
1136
1137 /* Set the FIFO state */
1138 fdctrl->data_dir = direction;
1139 fdctrl->data_pos = 0;
1140 fdctrl->msr |= FD_MSR_CMDBUSY;
1141 if (fdctrl->fifo[0] & 0x80)
1142 fdctrl->data_state |= FD_STATE_MULTI;
1143 else
1144 fdctrl->data_state &= ~FD_STATE_MULTI;
1145 if (did_seek)
1146 fdctrl->data_state |= FD_STATE_SEEK;
1147 else
1148 fdctrl->data_state &= ~FD_STATE_SEEK;
1149 if (fdctrl->fifo[5] == 00) {
1150 fdctrl->data_len = fdctrl->fifo[8];
1151 } else {
1152 int tmp;
1153 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1154 tmp = (fdctrl->fifo[6] - ks + 1);
1155 if (fdctrl->fifo[0] & 0x80)
1156 tmp += fdctrl->fifo[6];
1157 fdctrl->data_len *= tmp;
1158 }
1159 fdctrl->eot = fdctrl->fifo[6];
1160 if (fdctrl->dor & FD_DOR_DMAEN) {
1161 int dma_mode;
1162 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1163 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1164 dma_mode = (dma_mode >> 2) & 3;
1165 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1166 dma_mode, direction,
1167 (128 << fdctrl->fifo[5]) *
1168 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1169 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1170 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1171 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1172 (direction == FD_DIR_READ && dma_mode == 1)) {
1173 /* No access is allowed until DMA transfer has completed */
1174 fdctrl->msr &= ~FD_MSR_RQM;
1175 /* Now, we just have to wait for the DMA controller to
1176 * recall us...
1177 */
1178 DMA_hold_DREQ(fdctrl->dma_chann);
1179 DMA_schedule(fdctrl->dma_chann);
1180 return;
1181 } else {
1182 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1183 }
1184 }
1185 FLOPPY_DPRINTF("start non-DMA transfer\n");
1186 fdctrl->msr |= FD_MSR_NONDMA;
1187 if (direction != FD_DIR_WRITE)
1188 fdctrl->msr |= FD_MSR_DIO;
1189 /* IO based transfer: calculate len */
1190 fdctrl_raise_irq(fdctrl, 0x00);
1191
1192 return;
1193 }
1194
1195 /* Prepare a transfer of deleted data */
1196 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1197 {
1198 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1199
1200 /* We don't handle deleted data,
1201 * so we don't return *ANYTHING*
1202 */
1203 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1204 }
1205
1206 /* handlers for DMA transfers */
1207 static int fdctrl_transfer_handler (void *opaque, int nchan,
1208 int dma_pos, int dma_len)
1209 {
1210 FDCtrl *fdctrl;
1211 FDrive *cur_drv;
1212 int len, start_pos, rel_pos;
1213 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1214
1215 fdctrl = opaque;
1216 if (fdctrl->msr & FD_MSR_RQM) {
1217 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1218 return 0;
1219 }
1220 cur_drv = get_cur_drv(fdctrl);
1221 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1222 fdctrl->data_dir == FD_DIR_SCANH)
1223 status2 = FD_SR2_SNS;
1224 if (dma_len > fdctrl->data_len)
1225 dma_len = fdctrl->data_len;
1226 if (cur_drv->bs == NULL) {
1227 if (fdctrl->data_dir == FD_DIR_WRITE)
1228 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1229 else
1230 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1231 len = 0;
1232 goto transfer_error;
1233 }
1234 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1235 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1236 len = dma_len - fdctrl->data_pos;
1237 if (len + rel_pos > FD_SECTOR_LEN)
1238 len = FD_SECTOR_LEN - rel_pos;
1239 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1240 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1241 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1242 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1243 fd_sector(cur_drv) * FD_SECTOR_LEN);
1244 if (fdctrl->data_dir != FD_DIR_WRITE ||
1245 len < FD_SECTOR_LEN || rel_pos != 0) {
1246 /* READ & SCAN commands and realign to a sector for WRITE */
1247 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1248 fdctrl->fifo, 1) < 0) {
1249 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1250 fd_sector(cur_drv));
1251 /* Sure, image size is too small... */
1252 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1253 }
1254 }
1255 switch (fdctrl->data_dir) {
1256 case FD_DIR_READ:
1257 /* READ commands */
1258 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1259 fdctrl->data_pos, len);
1260 break;
1261 case FD_DIR_WRITE:
1262 /* WRITE commands */
1263 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1264 fdctrl->data_pos, len);
1265 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1266 fdctrl->fifo, 1) < 0) {
1267 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1268 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1269 goto transfer_error;
1270 }
1271 break;
1272 default:
1273 /* SCAN commands */
1274 {
1275 uint8_t tmpbuf[FD_SECTOR_LEN];
1276 int ret;
1277 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1278 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1279 if (ret == 0) {
1280 status2 = FD_SR2_SEH;
1281 goto end_transfer;
1282 }
1283 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1284 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1285 status2 = 0x00;
1286 goto end_transfer;
1287 }
1288 }
1289 break;
1290 }
1291 fdctrl->data_pos += len;
1292 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1293 if (rel_pos == 0) {
1294 /* Seek to next sector */
1295 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1296 break;
1297 }
1298 }
1299 end_transfer:
1300 len = fdctrl->data_pos - start_pos;
1301 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1302 fdctrl->data_pos, len, fdctrl->data_len);
1303 if (fdctrl->data_dir == FD_DIR_SCANE ||
1304 fdctrl->data_dir == FD_DIR_SCANL ||
1305 fdctrl->data_dir == FD_DIR_SCANH)
1306 status2 = FD_SR2_SEH;
1307 if (FD_DID_SEEK(fdctrl->data_state))
1308 status0 |= FD_SR0_SEEK;
1309 fdctrl->data_len -= len;
1310 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1311 transfer_error:
1312
1313 return len;
1314 }
1315
1316 /* Data register : 0x05 */
1317 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1318 {
1319 FDrive *cur_drv;
1320 uint32_t retval = 0;
1321 int pos;
1322
1323 cur_drv = get_cur_drv(fdctrl);
1324 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1325 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1326 FLOPPY_ERROR("controller not ready for reading\n");
1327 return 0;
1328 }
1329 pos = fdctrl->data_pos;
1330 if (fdctrl->msr & FD_MSR_NONDMA) {
1331 pos %= FD_SECTOR_LEN;
1332 if (pos == 0) {
1333 if (fdctrl->data_pos != 0)
1334 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1335 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1336 fd_sector(cur_drv));
1337 return 0;
1338 }
1339 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1340 FLOPPY_DPRINTF("error getting sector %d\n",
1341 fd_sector(cur_drv));
1342 /* Sure, image size is too small... */
1343 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1344 }
1345 }
1346 }
1347 retval = fdctrl->fifo[pos];
1348 if (++fdctrl->data_pos == fdctrl->data_len) {
1349 fdctrl->data_pos = 0;
1350 /* Switch from transfer mode to status mode
1351 * then from status mode to command mode
1352 */
1353 if (fdctrl->msr & FD_MSR_NONDMA) {
1354 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1355 } else {
1356 fdctrl_reset_fifo(fdctrl);
1357 fdctrl_reset_irq(fdctrl);
1358 }
1359 }
1360 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1361
1362 return retval;
1363 }
1364
1365 static void fdctrl_format_sector(FDCtrl *fdctrl)
1366 {
1367 FDrive *cur_drv;
1368 uint8_t kh, kt, ks;
1369
1370 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1371 cur_drv = get_cur_drv(fdctrl);
1372 kt = fdctrl->fifo[6];
1373 kh = fdctrl->fifo[7];
1374 ks = fdctrl->fifo[8];
1375 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1376 GET_CUR_DRV(fdctrl), kh, kt, ks,
1377 fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
1378 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1379 case 2:
1380 /* sect too big */
1381 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1382 fdctrl->fifo[3] = kt;
1383 fdctrl->fifo[4] = kh;
1384 fdctrl->fifo[5] = ks;
1385 return;
1386 case 3:
1387 /* track too big */
1388 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1389 fdctrl->fifo[3] = kt;
1390 fdctrl->fifo[4] = kh;
1391 fdctrl->fifo[5] = ks;
1392 return;
1393 case 4:
1394 /* No seek enabled */
1395 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1396 fdctrl->fifo[3] = kt;
1397 fdctrl->fifo[4] = kh;
1398 fdctrl->fifo[5] = ks;
1399 return;
1400 case 1:
1401 fdctrl->data_state |= FD_STATE_SEEK;
1402 break;
1403 default:
1404 break;
1405 }
1406 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1407 if (cur_drv->bs == NULL ||
1408 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1409 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1410 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1411 } else {
1412 if (cur_drv->sect == cur_drv->last_sect) {
1413 fdctrl->data_state &= ~FD_STATE_FORMAT;
1414 /* Last sector done */
1415 if (FD_DID_SEEK(fdctrl->data_state))
1416 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1417 else
1418 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1419 } else {
1420 /* More to do */
1421 fdctrl->data_pos = 0;
1422 fdctrl->data_len = 4;
1423 }
1424 }
1425 }
1426
1427 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1428 {
1429 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1430 fdctrl->fifo[0] = fdctrl->lock << 4;
1431 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1432 }
1433
1434 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1435 {
1436 FDrive *cur_drv = get_cur_drv(fdctrl);
1437
1438 /* Drives position */
1439 fdctrl->fifo[0] = drv0(fdctrl)->track;
1440 fdctrl->fifo[1] = drv1(fdctrl)->track;
1441 #if MAX_FD == 4
1442 fdctrl->fifo[2] = drv2(fdctrl)->track;
1443 fdctrl->fifo[3] = drv3(fdctrl)->track;
1444 #else
1445 fdctrl->fifo[2] = 0;
1446 fdctrl->fifo[3] = 0;
1447 #endif
1448 /* timers */
1449 fdctrl->fifo[4] = fdctrl->timer0;
1450 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1451 fdctrl->fifo[6] = cur_drv->last_sect;
1452 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1453 (cur_drv->perpendicular << 2);
1454 fdctrl->fifo[8] = fdctrl->config;
1455 fdctrl->fifo[9] = fdctrl->precomp_trk;
1456 fdctrl_set_fifo(fdctrl, 10, 0);
1457 }
1458
1459 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1460 {
1461 /* Controller's version */
1462 fdctrl->fifo[0] = fdctrl->version;
1463 fdctrl_set_fifo(fdctrl, 1, 1);
1464 }
1465
1466 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1467 {
1468 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1469 fdctrl_set_fifo(fdctrl, 1, 0);
1470 }
1471
1472 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1473 {
1474 FDrive *cur_drv = get_cur_drv(fdctrl);
1475
1476 /* Drives position */
1477 drv0(fdctrl)->track = fdctrl->fifo[3];
1478 drv1(fdctrl)->track = fdctrl->fifo[4];
1479 #if MAX_FD == 4
1480 drv2(fdctrl)->track = fdctrl->fifo[5];
1481 drv3(fdctrl)->track = fdctrl->fifo[6];
1482 #endif
1483 /* timers */
1484 fdctrl->timer0 = fdctrl->fifo[7];
1485 fdctrl->timer1 = fdctrl->fifo[8];
1486 cur_drv->last_sect = fdctrl->fifo[9];
1487 fdctrl->lock = fdctrl->fifo[10] >> 7;
1488 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1489 fdctrl->config = fdctrl->fifo[11];
1490 fdctrl->precomp_trk = fdctrl->fifo[12];
1491 fdctrl->pwrd = fdctrl->fifo[13];
1492 fdctrl_reset_fifo(fdctrl);
1493 }
1494
1495 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1496 {
1497 FDrive *cur_drv = get_cur_drv(fdctrl);
1498
1499 fdctrl->fifo[0] = 0;
1500 fdctrl->fifo[1] = 0;
1501 /* Drives position */
1502 fdctrl->fifo[2] = drv0(fdctrl)->track;
1503 fdctrl->fifo[3] = drv1(fdctrl)->track;
1504 #if MAX_FD == 4
1505 fdctrl->fifo[4] = drv2(fdctrl)->track;
1506 fdctrl->fifo[5] = drv3(fdctrl)->track;
1507 #else
1508 fdctrl->fifo[4] = 0;
1509 fdctrl->fifo[5] = 0;
1510 #endif
1511 /* timers */
1512 fdctrl->fifo[6] = fdctrl->timer0;
1513 fdctrl->fifo[7] = fdctrl->timer1;
1514 fdctrl->fifo[8] = cur_drv->last_sect;
1515 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1516 (cur_drv->perpendicular << 2);
1517 fdctrl->fifo[10] = fdctrl->config;
1518 fdctrl->fifo[11] = fdctrl->precomp_trk;
1519 fdctrl->fifo[12] = fdctrl->pwrd;
1520 fdctrl->fifo[13] = 0;
1521 fdctrl->fifo[14] = 0;
1522 fdctrl_set_fifo(fdctrl, 15, 1);
1523 }
1524
1525 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1526 {
1527 FDrive *cur_drv = get_cur_drv(fdctrl);
1528
1529 /* XXX: should set main status register to busy */
1530 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1531 qemu_mod_timer(fdctrl->result_timer,
1532 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1533 }
1534
1535 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1536 {
1537 FDrive *cur_drv;
1538
1539 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1540 cur_drv = get_cur_drv(fdctrl);
1541 fdctrl->data_state |= FD_STATE_FORMAT;
1542 if (fdctrl->fifo[0] & 0x80)
1543 fdctrl->data_state |= FD_STATE_MULTI;
1544 else
1545 fdctrl->data_state &= ~FD_STATE_MULTI;
1546 fdctrl->data_state &= ~FD_STATE_SEEK;
1547 cur_drv->bps =
1548 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1549 #if 0
1550 cur_drv->last_sect =
1551 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1552 fdctrl->fifo[3] / 2;
1553 #else
1554 cur_drv->last_sect = fdctrl->fifo[3];
1555 #endif
1556 /* TODO: implement format using DMA expected by the Bochs BIOS
1557 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1558 * the sector with the specified fill byte
1559 */
1560 fdctrl->data_state &= ~FD_STATE_FORMAT;
1561 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1562 }
1563
1564 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1565 {
1566 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1567 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1568 if (fdctrl->fifo[2] & 1)
1569 fdctrl->dor &= ~FD_DOR_DMAEN;
1570 else
1571 fdctrl->dor |= FD_DOR_DMAEN;
1572 /* No result back */
1573 fdctrl_reset_fifo(fdctrl);
1574 }
1575
1576 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1577 {
1578 FDrive *cur_drv;
1579
1580 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1581 cur_drv = get_cur_drv(fdctrl);
1582 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1583 /* 1 Byte status back */
1584 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1585 (cur_drv->track == 0 ? 0x10 : 0x00) |
1586 (cur_drv->head << 2) |
1587 GET_CUR_DRV(fdctrl) |
1588 0x28;
1589 fdctrl_set_fifo(fdctrl, 1, 0);
1590 }
1591
1592 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1593 {
1594 FDrive *cur_drv;
1595
1596 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1597 cur_drv = get_cur_drv(fdctrl);
1598 fd_recalibrate(cur_drv);
1599 fdctrl_reset_fifo(fdctrl);
1600 /* Raise Interrupt */
1601 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1602 }
1603
1604 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1605 {
1606 FDrive *cur_drv = get_cur_drv(fdctrl);
1607
1608 if(fdctrl->reset_sensei > 0) {
1609 fdctrl->fifo[0] =
1610 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1611 fdctrl->reset_sensei--;
1612 } else {
1613 /* XXX: status0 handling is broken for read/write
1614 commands, so we do this hack. It should be suppressed
1615 ASAP */
1616 fdctrl->fifo[0] =
1617 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1618 }
1619
1620 fdctrl->fifo[1] = cur_drv->track;
1621 fdctrl_set_fifo(fdctrl, 2, 0);
1622 fdctrl_reset_irq(fdctrl);
1623 fdctrl->status0 = FD_SR0_RDYCHG;
1624 }
1625
1626 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1627 {
1628 FDrive *cur_drv;
1629
1630 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1631 cur_drv = get_cur_drv(fdctrl);
1632 fdctrl_reset_fifo(fdctrl);
1633 if (fdctrl->fifo[2] > cur_drv->max_track) {
1634 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1635 } else {
1636 cur_drv->track = fdctrl->fifo[2];
1637 /* Raise Interrupt */
1638 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1639 }
1640 }
1641
1642 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1643 {
1644 FDrive *cur_drv = get_cur_drv(fdctrl);
1645
1646 if (fdctrl->fifo[1] & 0x80)
1647 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1648 /* No result back */
1649 fdctrl_reset_fifo(fdctrl);
1650 }
1651
1652 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1653 {
1654 fdctrl->config = fdctrl->fifo[2];
1655 fdctrl->precomp_trk = fdctrl->fifo[3];
1656 /* No result back */
1657 fdctrl_reset_fifo(fdctrl);
1658 }
1659
1660 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1661 {
1662 fdctrl->pwrd = fdctrl->fifo[1];
1663 fdctrl->fifo[0] = fdctrl->fifo[1];
1664 fdctrl_set_fifo(fdctrl, 1, 1);
1665 }
1666
1667 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1668 {
1669 /* No result back */
1670 fdctrl_reset_fifo(fdctrl);
1671 }
1672
1673 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1674 {
1675 FDrive *cur_drv = get_cur_drv(fdctrl);
1676
1677 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1678 /* Command parameters done */
1679 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1680 fdctrl->fifo[0] = fdctrl->fifo[1];
1681 fdctrl->fifo[2] = 0;
1682 fdctrl->fifo[3] = 0;
1683 fdctrl_set_fifo(fdctrl, 4, 1);
1684 } else {
1685 fdctrl_reset_fifo(fdctrl);
1686 }
1687 } else if (fdctrl->data_len > 7) {
1688 /* ERROR */
1689 fdctrl->fifo[0] = 0x80 |
1690 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1691 fdctrl_set_fifo(fdctrl, 1, 1);
1692 }
1693 }
1694
1695 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1696 {
1697 FDrive *cur_drv;
1698
1699 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1700 cur_drv = get_cur_drv(fdctrl);
1701 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1702 cur_drv->track = cur_drv->max_track - 1;
1703 } else {
1704 cur_drv->track += fdctrl->fifo[2];
1705 }
1706 fdctrl_reset_fifo(fdctrl);
1707 /* Raise Interrupt */
1708 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 }
1710
1711 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1712 {
1713 FDrive *cur_drv;
1714
1715 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1716 cur_drv = get_cur_drv(fdctrl);
1717 if (fdctrl->fifo[2] > cur_drv->track) {
1718 cur_drv->track = 0;
1719 } else {
1720 cur_drv->track -= fdctrl->fifo[2];
1721 }
1722 fdctrl_reset_fifo(fdctrl);
1723 /* Raise Interrupt */
1724 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1725 }
1726
1727 static const struct {
1728 uint8_t value;
1729 uint8_t mask;
1730 const char* name;
1731 int parameters;
1732 void (*handler)(FDCtrl *fdctrl, int direction);
1733 int direction;
1734 } handlers[] = {
1735 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1736 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1737 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1738 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1739 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1740 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1741 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1742 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1743 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1744 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1745 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1746 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1747 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1748 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1749 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1750 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1751 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1752 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1753 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1754 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1755 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1756 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1757 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1758 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1759 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1760 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1761 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1762 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1763 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1764 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1765 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1766 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1767 };
1768 /* Associate command to an index in the 'handlers' array */
1769 static uint8_t command_to_handler[256];
1770
1771 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1772 {
1773 FDrive *cur_drv;
1774 int pos;
1775
1776 /* Reset mode */
1777 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1778 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1779 return;
1780 }
1781 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1782 FLOPPY_ERROR("controller not ready for writing\n");
1783 return;
1784 }
1785 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1786 /* Is it write command time ? */
1787 if (fdctrl->msr & FD_MSR_NONDMA) {
1788 /* FIFO data write */
1789 pos = fdctrl->data_pos++;
1790 pos %= FD_SECTOR_LEN;
1791 fdctrl->fifo[pos] = value;
1792 if (pos == FD_SECTOR_LEN - 1 ||
1793 fdctrl->data_pos == fdctrl->data_len) {
1794 cur_drv = get_cur_drv(fdctrl);
1795 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1796 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1797 return;
1798 }
1799 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1800 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1801 fd_sector(cur_drv));
1802 return;
1803 }
1804 }
1805 /* Switch from transfer mode to status mode
1806 * then from status mode to command mode
1807 */
1808 if (fdctrl->data_pos == fdctrl->data_len)
1809 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1810 return;
1811 }
1812 if (fdctrl->data_pos == 0) {
1813 /* Command */
1814 pos = command_to_handler[value & 0xff];
1815 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1816 fdctrl->data_len = handlers[pos].parameters + 1;
1817 }
1818
1819 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1820 fdctrl->fifo[fdctrl->data_pos++] = value;
1821 if (fdctrl->data_pos == fdctrl->data_len) {
1822 /* We now have all parameters
1823 * and will be able to treat the command
1824 */
1825 if (fdctrl->data_state & FD_STATE_FORMAT) {
1826 fdctrl_format_sector(fdctrl);
1827 return;
1828 }
1829
1830 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1831 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1832 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1833 }
1834 }
1835
1836 static void fdctrl_result_timer(void *opaque)
1837 {
1838 FDCtrl *fdctrl = opaque;
1839 FDrive *cur_drv = get_cur_drv(fdctrl);
1840
1841 /* Pretend we are spinning.
1842 * This is needed for Coherent, which uses READ ID to check for
1843 * sector interleaving.
1844 */
1845 if (cur_drv->last_sect != 0) {
1846 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1847 }
1848 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1849 }
1850
1851 /* Init functions */
1852 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1853 {
1854 unsigned int i;
1855 FDrive *drive;
1856
1857 for (i = 0; i < MAX_FD; i++) {
1858 drive = &fdctrl->drives[i];
1859
1860 if (drive->bs) {
1861 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1862 error_report("fdc doesn't support drive option werror");
1863 return -1;
1864 }
1865 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1866 error_report("fdc doesn't support drive option rerror");
1867 return -1;
1868 }
1869 }
1870
1871 fd_init(drive);
1872 fd_revalidate(drive);
1873 if (drive->bs) {
1874 bdrv_set_removable(drive->bs, 1);
1875 }
1876 }
1877 return 0;
1878 }
1879
1880 FDCtrl *fdctrl_init_isa(DriveInfo **fds)
1881 {
1882 ISADevice *dev;
1883
1884 dev = isa_create("isa-fdc");
1885 if (fds[0]) {
1886 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1887 }
1888 if (fds[1]) {
1889 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1890 }
1891 qdev_init_nofail(&dev->qdev);
1892 return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
1893 }
1894
1895 FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1896 target_phys_addr_t mmio_base, DriveInfo **fds)
1897 {
1898 FDCtrl *fdctrl;
1899 DeviceState *dev;
1900 FDCtrlSysBus *sys;
1901
1902 dev = qdev_create(NULL, "sysbus-fdc");
1903 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1904 fdctrl = &sys->state;
1905 fdctrl->dma_chann = dma_chann; /* FIXME */
1906 if (fds[0]) {
1907 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1908 }
1909 if (fds[1]) {
1910 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1911 }
1912 qdev_init_nofail(dev);
1913 sysbus_connect_irq(&sys->busdev, 0, irq);
1914 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1915
1916 return fdctrl;
1917 }
1918
1919 FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1920 DriveInfo **fds, qemu_irq *fdc_tc)
1921 {
1922 DeviceState *dev;
1923 FDCtrlSysBus *sys;
1924 FDCtrl *fdctrl;
1925
1926 dev = qdev_create(NULL, "SUNW,fdtwo");
1927 if (fds[0]) {
1928 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1929 }
1930 qdev_init_nofail(dev);
1931 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1932 fdctrl = &sys->state;
1933 sysbus_connect_irq(&sys->busdev, 0, irq);
1934 sysbus_mmio_map(&sys->busdev, 0, io_base);
1935 *fdc_tc = qdev_get_gpio_in(dev, 0);
1936
1937 return fdctrl;
1938 }
1939
1940 static int fdctrl_init_common(FDCtrl *fdctrl)
1941 {
1942 int i, j;
1943 static int command_tables_inited = 0;
1944
1945 /* Fill 'command_to_handler' lookup table */
1946 if (!command_tables_inited) {
1947 command_tables_inited = 1;
1948 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1949 for (j = 0; j < sizeof(command_to_handler); j++) {
1950 if ((j & handlers[i].mask) == handlers[i].value) {
1951 command_to_handler[j] = i;
1952 }
1953 }
1954 }
1955 }
1956
1957 FLOPPY_DPRINTF("init controller\n");
1958 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1959 fdctrl->fifo_size = 512;
1960 fdctrl->result_timer = qemu_new_timer(vm_clock,
1961 fdctrl_result_timer, fdctrl);
1962
1963 fdctrl->version = 0x90; /* Intel 82078 controller */
1964 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1965 fdctrl->num_floppies = MAX_FD;
1966
1967 if (fdctrl->dma_chann != -1)
1968 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1969 return fdctrl_connect_drives(fdctrl);
1970 }
1971
1972 static int isabus_fdc_init1(ISADevice *dev)
1973 {
1974 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1975 FDCtrl *fdctrl = &isa->state;
1976 int iobase = 0x3f0;
1977 int isairq = 6;
1978 int dma_chann = 2;
1979 int ret;
1980
1981 register_ioport_read(iobase + 0x01, 5, 1,
1982 &fdctrl_read_port, fdctrl);
1983 register_ioport_read(iobase + 0x07, 1, 1,
1984 &fdctrl_read_port, fdctrl);
1985 register_ioport_write(iobase + 0x01, 5, 1,
1986 &fdctrl_write_port, fdctrl);
1987 register_ioport_write(iobase + 0x07, 1, 1,
1988 &fdctrl_write_port, fdctrl);
1989 isa_init_ioport_range(dev, iobase, 6);
1990 isa_init_ioport(dev, iobase + 7);
1991
1992 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1993 fdctrl->dma_chann = dma_chann;
1994
1995 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1996 ret = fdctrl_init_common(fdctrl);
1997
1998 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1999 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2000
2001 return ret;
2002 }
2003
2004 static int sysbus_fdc_init1(SysBusDevice *dev)
2005 {
2006 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2007 FDCtrl *fdctrl = &sys->state;
2008 int io;
2009 int ret;
2010
2011 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl,
2012 DEVICE_NATIVE_ENDIAN);
2013 sysbus_init_mmio(dev, 0x08, io);
2014 sysbus_init_irq(dev, &fdctrl->irq);
2015 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2016 fdctrl->dma_chann = -1;
2017
2018 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2019 ret = fdctrl_init_common(fdctrl);
2020
2021 return ret;
2022 }
2023
2024 static int sun4m_fdc_init1(SysBusDevice *dev)
2025 {
2026 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2027 int io;
2028
2029 io = cpu_register_io_memory(fdctrl_mem_read_strict,
2030 fdctrl_mem_write_strict, fdctrl,
2031 DEVICE_NATIVE_ENDIAN);
2032 sysbus_init_mmio(dev, 0x08, io);
2033 sysbus_init_irq(dev, &fdctrl->irq);
2034 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2035
2036 fdctrl->sun4m = 1;
2037 qdev_set_legacy_instance_id(&dev->qdev, io, 2);
2038 return fdctrl_init_common(fdctrl);
2039 }
2040
2041 static const VMStateDescription vmstate_isa_fdc ={
2042 .name = "fdc",
2043 .version_id = 2,
2044 .minimum_version_id = 2,
2045 .fields = (VMStateField []) {
2046 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2047 VMSTATE_END_OF_LIST()
2048 }
2049 };
2050
2051 static ISADeviceInfo isa_fdc_info = {
2052 .init = isabus_fdc_init1,
2053 .qdev.name = "isa-fdc",
2054 .qdev.fw_name = "fdc",
2055 .qdev.size = sizeof(FDCtrlISABus),
2056 .qdev.no_user = 1,
2057 .qdev.vmsd = &vmstate_isa_fdc,
2058 .qdev.reset = fdctrl_external_reset_isa,
2059 .qdev.props = (Property[]) {
2060 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2061 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2062 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2063 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2064 DEFINE_PROP_END_OF_LIST(),
2065 },
2066 };
2067
2068 static const VMStateDescription vmstate_sysbus_fdc ={
2069 .name = "fdc",
2070 .version_id = 2,
2071 .minimum_version_id = 2,
2072 .fields = (VMStateField []) {
2073 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2074 VMSTATE_END_OF_LIST()
2075 }
2076 };
2077
2078 static SysBusDeviceInfo sysbus_fdc_info = {
2079 .init = sysbus_fdc_init1,
2080 .qdev.name = "sysbus-fdc",
2081 .qdev.size = sizeof(FDCtrlSysBus),
2082 .qdev.vmsd = &vmstate_sysbus_fdc,
2083 .qdev.reset = fdctrl_external_reset_sysbus,
2084 .qdev.props = (Property[]) {
2085 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2086 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2087 DEFINE_PROP_END_OF_LIST(),
2088 },
2089 };
2090
2091 static SysBusDeviceInfo sun4m_fdc_info = {
2092 .init = sun4m_fdc_init1,
2093 .qdev.name = "SUNW,fdtwo",
2094 .qdev.size = sizeof(FDCtrlSysBus),
2095 .qdev.vmsd = &vmstate_sysbus_fdc,
2096 .qdev.reset = fdctrl_external_reset_sysbus,
2097 .qdev.props = (Property[]) {
2098 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2099 DEFINE_PROP_END_OF_LIST(),
2100 },
2101 };
2102
2103 static void fdc_register_devices(void)
2104 {
2105 isa_qdev_register(&isa_fdc_info);
2106 sysbus_register_withprop(&sysbus_fdc_info);
2107 sysbus_register_withprop(&sun4m_fdc_info);
2108 }
2109
2110 device_init(fdc_register_devices)
QEmu