hw/s390x/s390-pci-bus.h

   1 /*
   2  * s390 PCI BUS definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_BUS_H
  15 #define HW_S390_PCI_BUS_H
  16
  17 #include <hw/pci/pci.h>
  18 #include <hw/pci/pci_host.h>
  19 #include "hw/s390x/sclp.h"
  20 #include "hw/s390x/s390_flic.h"
  21 #include "hw/s390x/css.h"
  22
  23 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
  24 #define FH_MASK_ENABLE   0x80000000
  25 #define FH_MASK_INSTANCE 0x7f000000
  26 #define FH_MASK_SHM      0x00ff0000
  27 #define FH_MASK_INDEX    0x0000001f
  28 #define FH_SHM_VFIO      0x00010000
  29 #define FH_SHM_EMUL      0x00020000
  30 #define S390_PCIPT_ADAPTER 2
  31
  32 #define S390_PCI_HOST_BRIDGE(obj) \
  33     OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
  34
  35 #define HP_EVENT_TO_CONFIGURED        0x0301
  36 #define HP_EVENT_RESERVED_TO_STANDBY  0x0302
  37 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
  38 #define HP_EVENT_STANDBY_TO_RESERVED  0x0308
  39
  40 #define ERR_EVENT_INVALAS 0x1
  41 #define ERR_EVENT_OORANGE 0x2
  42 #define ERR_EVENT_INVALTF 0x3
  43 #define ERR_EVENT_TPROTE  0x4
  44 #define ERR_EVENT_APROTE  0x5
  45 #define ERR_EVENT_KEYE    0x6
  46 #define ERR_EVENT_INVALTE 0x7
  47 #define ERR_EVENT_INVALTL 0x8
  48 #define ERR_EVENT_TT      0x9
  49 #define ERR_EVENT_INVALMS 0xa
  50 #define ERR_EVENT_SERR    0xb
  51 #define ERR_EVENT_NOMSI   0x10
  52 #define ERR_EVENT_INVALBV 0x11
  53 #define ERR_EVENT_AIBV    0x12
  54 #define ERR_EVENT_AIRERR  0x13
  55 #define ERR_EVENT_FMBA    0x2a
  56 #define ERR_EVENT_FMBUP   0x2b
  57 #define ERR_EVENT_FMBPRO  0x2c
  58 #define ERR_EVENT_CCONF   0x30
  59 #define ERR_EVENT_SERVAC  0x3a
  60 #define ERR_EVENT_PERMERR 0x3b
  61
  62 #define ERR_EVENT_Q_BIT 0x2
  63 #define ERR_EVENT_MVN_OFFSET 16
  64
  65 #define ZPCI_MSI_VEC_BITS 11
  66 #define ZPCI_MSI_VEC_MASK 0x7ff
  67
  68 #define ZPCI_MSI_ADDR  0xfe00000000000000ULL
  69 #define ZPCI_SDMA_ADDR 0x100000000ULL
  70 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
  71
  72 #define PAGE_SHIFT      12
  73 #define PAGE_MASK       (~(PAGE_SIZE-1))
  74 #define PAGE_DEFAULT_ACC        0
  75 #define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
  76
  77 /* I/O Translation Anchor (IOTA) */
  78 enum ZpciIoatDtype {
  79     ZPCI_IOTA_STO = 0,
  80     ZPCI_IOTA_RTTO = 1,
  81     ZPCI_IOTA_RSTO = 2,
  82     ZPCI_IOTA_RFTO = 3,
  83     ZPCI_IOTA_PFAA = 4,
  84     ZPCI_IOTA_IOPFAA = 5,
  85     ZPCI_IOTA_IOPTO = 7
  86 };
  87
  88 #define ZPCI_IOTA_IOT_ENABLED           0x800ULL
  89 #define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
  90 #define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
  91 #define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
  92 #define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
  93 #define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
  94 #define ZPCI_IOTA_FS_4K                 0
  95 #define ZPCI_IOTA_FS_1M                 1
  96 #define ZPCI_IOTA_FS_2G                 2
  97 #define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)
  98
  99 #define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
 100 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
 101 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
 102 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
 103 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
 104                              ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
 105
 106 /* I/O Region and segment tables */
 107 #define ZPCI_INDEX_MASK         0x7ffULL
 108
 109 #define ZPCI_TABLE_TYPE_MASK    0xc
 110 #define ZPCI_TABLE_TYPE_RFX     0xc
 111 #define ZPCI_TABLE_TYPE_RSX     0x8
 112 #define ZPCI_TABLE_TYPE_RTX     0x4
 113 #define ZPCI_TABLE_TYPE_SX      0x0
 114
 115 #define ZPCI_TABLE_LEN_RFX      0x3
 116 #define ZPCI_TABLE_LEN_RSX      0x3
 117 #define ZPCI_TABLE_LEN_RTX      0x3
 118
 119 #define ZPCI_TABLE_OFFSET_MASK  0xc0
 120 #define ZPCI_TABLE_SIZE         0x4000
 121 #define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
 122 #define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
 123 #define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 124
 125 #define ZPCI_TABLE_BITS         11
 126 #define ZPCI_PT_BITS            8
 127 #define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
 128 #define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
 129
 130 #define ZPCI_RTE_FLAG_MASK      0x3fffULL
 131 #define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
 132 #define ZPCI_STE_FLAG_MASK      0x7ffULL
 133 #define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)
 134
 135 /* I/O Page tables */
 136 #define ZPCI_PTE_VALID_MASK             0x400
 137 #define ZPCI_PTE_INVALID                0x400
 138 #define ZPCI_PTE_VALID                  0x000
 139 #define ZPCI_PT_SIZE                    0x800
 140 #define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
 141 #define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 142 #define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)
 143
 144 #define ZPCI_PTE_FLAG_MASK              0xfffULL
 145 #define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)
 146
 147 /* Shared bits */
 148 #define ZPCI_TABLE_VALID                0x00
 149 #define ZPCI_TABLE_INVALID              0x20
 150 #define ZPCI_TABLE_PROTECTED            0x200
 151 #define ZPCI_TABLE_UNPROTECTED          0x000
 152
 153 #define ZPCI_TABLE_VALID_MASK           0x20
 154 #define ZPCI_TABLE_PROT_MASK            0x200
 155
 156 /* PCI Function States
 157  *
 158  * reserved: default; device has just been plugged or is in progress of being
 159  *           unplugged
 160  * standby: device is present but not configured; transition from any
 161  *          configured state/to this state via sclp configure/deconfigure
 162  *
 163  * The following states make up the "configured" meta-state:
 164  * disabled: device is configured but not enabled; transition between this
 165  *           state and enabled via clp enable/disable
 166  * enbaled: device is ready for use; transition to disabled via clp disable;
 167  *          may enter an error state
 168  * blocked: ignore all DMA and interrupts; transition back to enabled or from
 169  *          error state via mpcifc
 170  * error: an error occured; transition back to enabled via mpcifc
 171  * permanent error: an unrecoverable error occured; transition to standby via
 172  *                  sclp deconfigure
 173  */
 174 typedef enum {
 175     ZPCI_FS_RESERVED,
 176     ZPCI_FS_STANDBY,
 177     ZPCI_FS_DISABLED,
 178     ZPCI_FS_ENABLED,
 179     ZPCI_FS_BLOCKED,
 180     ZPCI_FS_ERROR,
 181     ZPCI_FS_PERMANENT_ERROR,
 182 } ZpciState;
 183
 184 typedef struct SeiContainer {
 185     QTAILQ_ENTRY(SeiContainer) link;
 186     uint32_t fid;
 187     uint32_t fh;
 188     uint8_t cc;
 189     uint16_t pec;
 190     uint64_t faddr;
 191     uint32_t e;
 192 } SeiContainer;
 193
 194 typedef struct PciCcdfErr {
 195     uint32_t reserved1;
 196     uint32_t fh;
 197     uint32_t fid;
 198     uint32_t e;
 199     uint64_t faddr;
 200     uint32_t reserved3;
 201     uint16_t reserved4;
 202     uint16_t pec;
 203 } QEMU_PACKED PciCcdfErr;
 204
 205 typedef struct PciCcdfAvail {
 206     uint32_t reserved1;
 207     uint32_t fh;
 208     uint32_t fid;
 209     uint32_t reserved2;
 210     uint32_t reserved3;
 211     uint32_t reserved4;
 212     uint32_t reserved5;
 213     uint16_t reserved6;
 214     uint16_t pec;
 215 } QEMU_PACKED PciCcdfAvail;
 216
 217 typedef struct ChscSeiNt2Res {
 218     uint16_t length;
 219     uint16_t code;
 220     uint16_t reserved1;
 221     uint8_t reserved2;
 222     uint8_t nt;
 223     uint8_t flags;
 224     uint8_t reserved3;
 225     uint8_t reserved4;
 226     uint8_t cc;
 227     uint32_t reserved5[13];
 228     uint8_t ccdf[4016];
 229 } QEMU_PACKED ChscSeiNt2Res;
 230
 231 typedef struct PciCfgSccb {
 232     SCCBHeader header;
 233     uint8_t atype;
 234     uint8_t reserved1;
 235     uint16_t reserved2;
 236     uint32_t aid;
 237 } QEMU_PACKED PciCfgSccb;
 238
 239 typedef struct S390MsixInfo {
 240     bool available;
 241     uint8_t table_bar;
 242     uint8_t pba_bar;
 243     uint16_t entries;
 244     uint32_t table_offset;
 245     uint32_t pba_offset;
 246 } S390MsixInfo;
 247
 248 typedef struct S390PCIBusDevice {
 249     PCIDevice *pdev;
 250     ZpciState state;
 251     bool iommu_enabled;
 252     uint32_t fh;
 253     uint32_t fid;
 254     uint64_t g_iota;
 255     uint64_t pba;
 256     uint64_t pal;
 257     uint64_t fmb_addr;
 258     uint8_t isc;
 259     uint16_t noi;
 260     uint8_t sum;
 261     S390MsixInfo msix;
 262     AdapterRoutes routes;
 263     AddressSpace as;
 264     MemoryRegion mr;
 265     MemoryRegion iommu_mr;
 266     IndAddr *summary_ind;
 267     IndAddr *indicator;
 268 } S390PCIBusDevice;
 269
 270 typedef struct S390pciState {
 271     PCIHostState parent_obj;
 272     S390PCIBusDevice pbdev[PCI_SLOT_MAX];
 273     AddressSpace msix_notify_as;
 274     MemoryRegion msix_notify_mr;
 275     QTAILQ_HEAD(, SeiContainer) pending_sei;
 276 } S390pciState;
 277
 278 int chsc_sei_nt2_get_event(void *res);
 279 int chsc_sei_nt2_have_event(void);
 280 void s390_pci_sclp_configure(SCCB *sccb);
 281 void s390_pci_sclp_deconfigure(SCCB *sccb);
 282 void s390_pci_iommu_enable(S390PCIBusDevice *pbdev);
 283 void s390_pci_iommu_disable(S390PCIBusDevice *pbdev);
 284 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
 285                                    uint64_t faddr, uint32_t e);
 286 S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
 287 S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
 288 S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
 289
 290 #endif