2 * ARM PrimeCell PL080/PL081 DMA controller
4 * Copyright (c) 2006 CodeSourcery.
5 * Copyright (c) 2018 Linaro Limited
6 * Written by Paul Brook, Peter Maydell
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 or
10 * (at your option) any later version.
13 /* This is a model of the Arm PrimeCell PL080/PL081 DMA controller:
15 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0196g/DDI0196.pdf
16 * and the PL081 TRM is:
17 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf
20 * + sysbus IRQ 0: DMACINTR combined interrupt line
21 * + sysbus IRQ 1: DMACINTERR error interrupt request
22 * + sysbus IRQ 2: DMACINTTC count interrupt request
23 * + sysbus MMIO region 0: MemoryRegion for the device's registers
24 * + QOM property "downstream": MemoryRegion defining where DMA
25 * bus master transactions are made
28 #ifndef HW_DMA_PL080_H
29 #define HW_DMA_PL080_H
31 #include "hw/sysbus.h"
33 #define PL080_MAX_CHANNELS 8
43 #define TYPE_PL080 "pl080"
44 #define TYPE_PL081 "pl081"
45 #define PL080(obj) OBJECT_CHECK(PL080State, (obj), TYPE_PL080)
47 typedef struct PL080State
{
48 SysBusDevice parent_obj
;
59 pl080_channel chan
[PL080_MAX_CHANNELS
];
61 /* Flag to avoid recursive DMA invocations. */
67 MemoryRegion
*downstream
;
68 AddressSpace downstream_as
;