2 * ARM Integrator CP System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL
10 #include "hw/sysbus.h"
11 #include "hw/devices.h"
12 #include "hw/boards.h"
13 #include "hw/arm/arm.h"
14 #include "hw/misc/arm_integrator_debug.h"
16 #include "exec/address-spaces.h"
17 #include "sysemu/sysemu.h"
18 #include "qemu/error-report.h"
20 #define TYPE_INTEGRATOR_CM "integrator_core"
21 #define INTEGRATOR_CM(obj) \
22 OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
24 typedef struct IntegratorCMState
{
26 SysBusDevice parent_obj
;
40 uint32_t cm_refcnt_offset
;
46 static uint8_t integrator_spd
[128] = {
47 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
48 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
51 static uint64_t integratorcm_read(void *opaque
, hwaddr offset
,
54 IntegratorCMState
*s
= opaque
;
55 if (offset
>= 0x100 && offset
< 0x200) {
59 return integrator_spd
[offset
>> 2];
61 switch (offset
>> 2) {
73 if (s
->cm_lock
== 0xa05f) {
78 case 6: /* CM_LMBUSCNT */
79 /* ??? High frequency timer. */
80 hw_error("integratorcm_read: CM_LMBUSCNT");
81 case 7: /* CM_AUXOSC */
83 case 8: /* CM_SDRAM */
87 case 10: /* CM_REFCNT */
88 /* This register, CM_REFCNT, provides a 32-bit count value.
89 * The count increments at the fixed reference clock frequency of 24MHz
90 * and can be used as a real-time counter.
92 return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
93 1000) - s
->cm_refcnt_offset
;
94 case 12: /* CM_FLAGS */
96 case 14: /* CM_NVFLAGS */
98 case 16: /* CM_IRQ_STAT */
99 return s
->int_level
& s
->irq_enabled
;
100 case 17: /* CM_IRQ_RSTAT */
102 case 18: /* CM_IRQ_ENSET */
103 return s
->irq_enabled
;
104 case 20: /* CM_SOFT_INTSET */
105 return s
->int_level
& 1;
106 case 24: /* CM_FIQ_STAT */
107 return s
->int_level
& s
->fiq_enabled
;
108 case 25: /* CM_FIQ_RSTAT */
110 case 26: /* CM_FIQ_ENSET */
111 return s
->fiq_enabled
;
112 case 32: /* CM_VOLTAGE_CTL0 */
113 case 33: /* CM_VOLTAGE_CTL1 */
114 case 34: /* CM_VOLTAGE_CTL2 */
115 case 35: /* CM_VOLTAGE_CTL3 */
116 /* ??? Voltage control unimplemented. */
119 hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
125 static void integratorcm_do_remap(IntegratorCMState
*s
)
127 /* Sync memory region state with CM_CTRL REMAP bit:
128 * bit 0 => flash at address 0; bit 1 => RAM
130 memory_region_set_enabled(&s
->flash
, !(s
->cm_ctrl
& 4));
133 static void integratorcm_set_ctrl(IntegratorCMState
*s
, uint32_t value
)
136 qemu_system_reset_request();
138 if ((s
->cm_ctrl
^ value
) & 1) {
139 /* (value & 1) != 0 means the green "MISC LED" is lit.
140 * We don't have any nice place to display LEDs. printf is a bad
141 * idea because Linux uses the LED as a heartbeat and the output
142 * will swamp anything else on the terminal.
145 /* Note that the RESET bit [3] always reads as zero */
146 s
->cm_ctrl
= (s
->cm_ctrl
& ~5) | (value
& 5);
147 integratorcm_do_remap(s
);
150 static void integratorcm_update(IntegratorCMState
*s
)
152 /* ??? The CPU irq/fiq is raised when either the core module or base PIC
154 if (s
->int_level
& (s
->irq_enabled
| s
->fiq_enabled
))
155 hw_error("Core module interrupt\n");
158 static void integratorcm_write(void *opaque
, hwaddr offset
,
159 uint64_t value
, unsigned size
)
161 IntegratorCMState
*s
= opaque
;
162 switch (offset
>> 2) {
164 if (s
->cm_lock
== 0xa05f)
167 case 3: /* CM_CTRL */
168 integratorcm_set_ctrl(s
, value
);
170 case 5: /* CM_LOCK */
171 s
->cm_lock
= value
& 0xffff;
173 case 7: /* CM_AUXOSC */
174 if (s
->cm_lock
== 0xa05f)
175 s
->cm_auxosc
= value
;
177 case 8: /* CM_SDRAM */
180 case 9: /* CM_INIT */
181 /* ??? This can change the memory bus frequency. */
184 case 12: /* CM_FLAGSS */
185 s
->cm_flags
|= value
;
187 case 13: /* CM_FLAGSC */
188 s
->cm_flags
&= ~value
;
190 case 14: /* CM_NVFLAGSS */
191 s
->cm_nvflags
|= value
;
193 case 15: /* CM_NVFLAGSS */
194 s
->cm_nvflags
&= ~value
;
196 case 18: /* CM_IRQ_ENSET */
197 s
->irq_enabled
|= value
;
198 integratorcm_update(s
);
200 case 19: /* CM_IRQ_ENCLR */
201 s
->irq_enabled
&= ~value
;
202 integratorcm_update(s
);
204 case 20: /* CM_SOFT_INTSET */
205 s
->int_level
|= (value
& 1);
206 integratorcm_update(s
);
208 case 21: /* CM_SOFT_INTCLR */
209 s
->int_level
&= ~(value
& 1);
210 integratorcm_update(s
);
212 case 26: /* CM_FIQ_ENSET */
213 s
->fiq_enabled
|= value
;
214 integratorcm_update(s
);
216 case 27: /* CM_FIQ_ENCLR */
217 s
->fiq_enabled
&= ~value
;
218 integratorcm_update(s
);
220 case 32: /* CM_VOLTAGE_CTL0 */
221 case 33: /* CM_VOLTAGE_CTL1 */
222 case 34: /* CM_VOLTAGE_CTL2 */
223 case 35: /* CM_VOLTAGE_CTL3 */
224 /* ??? Voltage control unimplemented. */
227 hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
233 /* Integrator/CM control registers. */
235 static const MemoryRegionOps integratorcm_ops
= {
236 .read
= integratorcm_read
,
237 .write
= integratorcm_write
,
238 .endianness
= DEVICE_NATIVE_ENDIAN
,
241 static int integratorcm_init(SysBusDevice
*dev
)
243 IntegratorCMState
*s
= INTEGRATOR_CM(dev
);
245 s
->cm_osc
= 0x01000048;
246 /* ??? What should the high bits of this value be? */
247 s
->cm_auxosc
= 0x0007feff;
248 s
->cm_sdram
= 0x00011122;
249 if (s
->memsz
>= 256) {
250 integrator_spd
[31] = 64;
252 } else if (s
->memsz
>= 128) {
253 integrator_spd
[31] = 32;
255 } else if (s
->memsz
>= 64) {
256 integrator_spd
[31] = 16;
258 } else if (s
->memsz
>= 32) {
259 integrator_spd
[31] = 4;
262 integrator_spd
[31] = 2;
264 memcpy(integrator_spd
+ 73, "QEMU-MEMORY", 11);
265 s
->cm_init
= 0x00000112;
266 s
->cm_refcnt_offset
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), 24,
268 memory_region_init_ram(&s
->flash
, OBJECT(s
), "integrator.flash", 0x100000,
270 vmstate_register_ram_global(&s
->flash
);
272 memory_region_init_io(&s
->iomem
, OBJECT(s
), &integratorcm_ops
, s
,
273 "integratorcm", 0x00800000);
274 sysbus_init_mmio(dev
, &s
->iomem
);
276 integratorcm_do_remap(s
);
277 /* ??? Save/restore. */
281 /* Integrator/CP hardware emulation. */
282 /* Primary interrupt controller. */
284 #define TYPE_INTEGRATOR_PIC "integrator_pic"
285 #define INTEGRATOR_PIC(obj) \
286 OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
288 typedef struct icp_pic_state
{
290 SysBusDevice parent_obj
;
295 uint32_t irq_enabled
;
296 uint32_t fiq_enabled
;
301 static void icp_pic_update(icp_pic_state
*s
)
305 flags
= (s
->level
& s
->irq_enabled
);
306 qemu_set_irq(s
->parent_irq
, flags
!= 0);
307 flags
= (s
->level
& s
->fiq_enabled
);
308 qemu_set_irq(s
->parent_fiq
, flags
!= 0);
311 static void icp_pic_set_irq(void *opaque
, int irq
, int level
)
313 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
315 s
->level
|= 1 << irq
;
317 s
->level
&= ~(1 << irq
);
321 static uint64_t icp_pic_read(void *opaque
, hwaddr offset
,
324 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
326 switch (offset
>> 2) {
327 case 0: /* IRQ_STATUS */
328 return s
->level
& s
->irq_enabled
;
329 case 1: /* IRQ_RAWSTAT */
331 case 2: /* IRQ_ENABLESET */
332 return s
->irq_enabled
;
333 case 4: /* INT_SOFTSET */
335 case 8: /* FRQ_STATUS */
336 return s
->level
& s
->fiq_enabled
;
337 case 9: /* FRQ_RAWSTAT */
339 case 10: /* FRQ_ENABLESET */
340 return s
->fiq_enabled
;
341 case 3: /* IRQ_ENABLECLR */
342 case 5: /* INT_SOFTCLR */
343 case 11: /* FRQ_ENABLECLR */
345 printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset
);
350 static void icp_pic_write(void *opaque
, hwaddr offset
,
351 uint64_t value
, unsigned size
)
353 icp_pic_state
*s
= (icp_pic_state
*)opaque
;
355 switch (offset
>> 2) {
356 case 2: /* IRQ_ENABLESET */
357 s
->irq_enabled
|= value
;
359 case 3: /* IRQ_ENABLECLR */
360 s
->irq_enabled
&= ~value
;
362 case 4: /* INT_SOFTSET */
364 icp_pic_set_irq(s
, 0, 1);
366 case 5: /* INT_SOFTCLR */
368 icp_pic_set_irq(s
, 0, 0);
370 case 10: /* FRQ_ENABLESET */
371 s
->fiq_enabled
|= value
;
373 case 11: /* FRQ_ENABLECLR */
374 s
->fiq_enabled
&= ~value
;
376 case 0: /* IRQ_STATUS */
377 case 1: /* IRQ_RAWSTAT */
378 case 8: /* FRQ_STATUS */
379 case 9: /* FRQ_RAWSTAT */
381 printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset
);
387 static const MemoryRegionOps icp_pic_ops
= {
388 .read
= icp_pic_read
,
389 .write
= icp_pic_write
,
390 .endianness
= DEVICE_NATIVE_ENDIAN
,
393 static int icp_pic_init(SysBusDevice
*sbd
)
395 DeviceState
*dev
= DEVICE(sbd
);
396 icp_pic_state
*s
= INTEGRATOR_PIC(dev
);
398 qdev_init_gpio_in(dev
, icp_pic_set_irq
, 32);
399 sysbus_init_irq(sbd
, &s
->parent_irq
);
400 sysbus_init_irq(sbd
, &s
->parent_fiq
);
401 memory_region_init_io(&s
->iomem
, OBJECT(s
), &icp_pic_ops
, s
,
402 "icp-pic", 0x00800000);
403 sysbus_init_mmio(sbd
, &s
->iomem
);
407 /* CP control registers. */
409 static uint64_t icp_control_read(void *opaque
, hwaddr offset
,
412 switch (offset
>> 2) {
413 case 0: /* CP_IDFIELD */
415 case 1: /* CP_FLASHPROG */
417 case 2: /* CP_INTREG */
419 case 3: /* CP_DECODE */
422 hw_error("icp_control_read: Bad offset %x\n", (int)offset
);
427 static void icp_control_write(void *opaque
, hwaddr offset
,
428 uint64_t value
, unsigned size
)
430 switch (offset
>> 2) {
431 case 1: /* CP_FLASHPROG */
432 case 2: /* CP_INTREG */
433 case 3: /* CP_DECODE */
434 /* Nothing interesting implemented yet. */
437 hw_error("icp_control_write: Bad offset %x\n", (int)offset
);
441 static const MemoryRegionOps icp_control_ops
= {
442 .read
= icp_control_read
,
443 .write
= icp_control_write
,
444 .endianness
= DEVICE_NATIVE_ENDIAN
,
447 static void icp_control_init(hwaddr base
)
451 io
= (MemoryRegion
*)g_malloc0(sizeof(MemoryRegion
));
452 memory_region_init_io(io
, NULL
, &icp_control_ops
, NULL
,
453 "control", 0x00800000);
454 memory_region_add_subregion(get_system_memory(), base
, io
);
455 /* ??? Save/restore. */
461 static struct arm_boot_info integrator_binfo
= {
466 static void integratorcp_init(MachineState
*machine
)
468 ram_addr_t ram_size
= machine
->ram_size
;
469 const char *cpu_model
= machine
->cpu_model
;
470 const char *kernel_filename
= machine
->kernel_filename
;
471 const char *kernel_cmdline
= machine
->kernel_cmdline
;
472 const char *initrd_filename
= machine
->initrd_filename
;
476 MemoryRegion
*address_space_mem
= get_system_memory();
477 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
478 MemoryRegion
*ram_alias
= g_new(MemoryRegion
, 1);
485 cpu_model
= "arm926";
488 cpu_oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
490 fprintf(stderr
, "Unable to find CPU definition\n");
494 cpuobj
= object_new(object_class_get_name(cpu_oc
));
496 /* By default ARM1176 CPUs have EL3 enabled. This board does not
497 * currently support EL3 so the CPU EL3 property is disabled before
500 if (object_property_find(cpuobj
, "has_el3", NULL
)) {
501 object_property_set_bool(cpuobj
, false, "has_el3", &err
);
503 error_report("%s", error_get_pretty(err
));
508 object_property_set_bool(cpuobj
, true, "realized", &err
);
510 error_report("%s", error_get_pretty(err
));
514 cpu
= ARM_CPU(cpuobj
);
516 memory_region_init_ram(ram
, NULL
, "integrator.ram", ram_size
, &error_abort
);
517 vmstate_register_ram_global(ram
);
518 /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
519 /* ??? RAM should repeat to fill physical memory space. */
520 /* SDRAM at address zero*/
521 memory_region_add_subregion(address_space_mem
, 0, ram
);
522 /* And again at address 0x80000000 */
523 memory_region_init_alias(ram_alias
, NULL
, "ram.alias", ram
, 0, ram_size
);
524 memory_region_add_subregion(address_space_mem
, 0x80000000, ram_alias
);
526 dev
= qdev_create(NULL
, TYPE_INTEGRATOR_CM
);
527 qdev_prop_set_uint32(dev
, "memsz", ram_size
>> 20);
528 qdev_init_nofail(dev
);
529 sysbus_mmio_map((SysBusDevice
*)dev
, 0, 0x10000000);
531 dev
= sysbus_create_varargs(TYPE_INTEGRATOR_PIC
, 0x14000000,
532 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
),
533 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_FIQ
),
535 for (i
= 0; i
< 32; i
++) {
536 pic
[i
] = qdev_get_gpio_in(dev
, i
);
538 sysbus_create_simple(TYPE_INTEGRATOR_PIC
, 0xca000000, pic
[26]);
539 sysbus_create_varargs("integrator_pit", 0x13000000,
540 pic
[5], pic
[6], pic
[7], NULL
);
541 sysbus_create_simple("pl031", 0x15000000, pic
[8]);
542 sysbus_create_simple("pl011", 0x16000000, pic
[1]);
543 sysbus_create_simple("pl011", 0x17000000, pic
[2]);
544 icp_control_init(0xcb000000);
545 sysbus_create_simple("pl050_keyboard", 0x18000000, pic
[3]);
546 sysbus_create_simple("pl050_mouse", 0x19000000, pic
[4]);
547 sysbus_create_simple(TYPE_INTEGRATOR_DEBUG
, 0x1a000000, 0);
548 sysbus_create_varargs("pl181", 0x1c000000, pic
[23], pic
[24], NULL
);
549 if (nd_table
[0].used
)
550 smc91c111_init(&nd_table
[0], 0xc8000000, pic
[27]);
552 sysbus_create_simple("pl110", 0xc0000000, pic
[22]);
554 integrator_binfo
.ram_size
= ram_size
;
555 integrator_binfo
.kernel_filename
= kernel_filename
;
556 integrator_binfo
.kernel_cmdline
= kernel_cmdline
;
557 integrator_binfo
.initrd_filename
= initrd_filename
;
558 arm_load_kernel(cpu
, &integrator_binfo
);
561 static QEMUMachine integratorcp_machine
= {
562 .name
= "integratorcp",
563 .desc
= "ARM Integrator/CP (ARM926EJ-S)",
564 .init
= integratorcp_init
,
567 static void integratorcp_machine_init(void)
569 qemu_register_machine(&integratorcp_machine
);
572 machine_init(integratorcp_machine_init
);
574 static Property core_properties
[] = {
575 DEFINE_PROP_UINT32("memsz", IntegratorCMState
, memsz
, 0),
576 DEFINE_PROP_END_OF_LIST(),
579 static void core_class_init(ObjectClass
*klass
, void *data
)
581 DeviceClass
*dc
= DEVICE_CLASS(klass
);
582 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
584 k
->init
= integratorcm_init
;
585 dc
->props
= core_properties
;
588 static const TypeInfo core_info
= {
589 .name
= TYPE_INTEGRATOR_CM
,
590 .parent
= TYPE_SYS_BUS_DEVICE
,
591 .instance_size
= sizeof(IntegratorCMState
),
592 .class_init
= core_class_init
,
595 static void icp_pic_class_init(ObjectClass
*klass
, void *data
)
597 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
599 sdc
->init
= icp_pic_init
;
602 static const TypeInfo icp_pic_info
= {
603 .name
= TYPE_INTEGRATOR_PIC
,
604 .parent
= TYPE_SYS_BUS_DEVICE
,
605 .instance_size
= sizeof(icp_pic_state
),
606 .class_init
= icp_pic_class_init
,
609 static void integratorcp_register_types(void)
611 type_register_static(&icp_pic_info
);
612 type_register_static(&core_info
);
615 type_init(integratorcp_register_types
)