hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "pci_host.h"
  33 #include "ppc.h"
  34 #include "boards.h"
  35 #include "qemu-log.h"
  36 #include "ide.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "blockdev.h"
  40 #include "exec-memory.h"
  41
  42 //#define HARD_DEBUG_PPC_IO
  43 //#define DEBUG_PPC_IO
  44
  45 /* SMP is not enabled, for now */
  46 #define MAX_CPUS 1
  47
  48 #define MAX_IDE_BUS 2
  49
  50 #define BIOS_SIZE (1024 * 1024)
  51 #define BIOS_FILENAME "ppc_rom.bin"
  52 #define KERNEL_LOAD_ADDR 0x01000000
  53 #define INITRD_LOAD_ADDR 0x01800000
  54
  55 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  56 #define DEBUG_PPC_IO
  57 #endif
  58
  59 #if defined (HARD_DEBUG_PPC_IO)
  60 #define PPC_IO_DPRINTF(fmt, ...)                         \
  61 do {                                                     \
  62     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  63         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  64     } else {                                             \
  65         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  66     }                                                    \
  67 } while (0)
  68 #elif defined (DEBUG_PPC_IO)
  69 #define PPC_IO_DPRINTF(fmt, ...) \
  70 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  71 #else
  72 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  73 #endif
  74
  75 /* Constants for devices init */
  76 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  77 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  78 static const int ide_irq[2] = { 13, 13 };
  79
  80 #define NE2000_NB_MAX 6
  81
  82 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  83 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  84
  85 /* ISA IO ports bridge */
  86 #define PPC_IO_BASE 0x80000000
  87
  88 /* PCI intack register */
  89 /* Read-only register (?) */
  90 static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
  91                               uint64_t value, unsigned size)
  92 {
  93 #if 0
  94     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr,
  95            value);
  96 #endif
  97 }
  98
  99 static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr,
 100                                 unsigned size)
 101 {
 102     uint32_t retval = 0;
 103
 104     if ((addr & 0xf) == 0)
 105         retval = pic_read_irq(isa_pic);
 106 #if 0
 107     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 108            retval);
 109 #endif
 110
 111     return retval;
 112 }
 113
 114 static const MemoryRegionOps PPC_intack_ops = {
 115     .read = PPC_intack_read,
 116     .write = PPC_intack_write,
 117     .endianness = DEVICE_LITTLE_ENDIAN,
 118 };
 119
 120 /* PowerPC control and status registers */
 121 #if 0 // Not used
 122 static struct {
 123     /* IDs */
 124     uint32_t veni_devi;
 125     uint32_t revi;
 126     /* Control and status */
 127     uint32_t gcsr;
 128     uint32_t xcfr;
 129     uint32_t ct32;
 130     uint32_t mcsr;
 131     /* General purpose registers */
 132     uint32_t gprg[6];
 133     /* Exceptions */
 134     uint32_t feen;
 135     uint32_t fest;
 136     uint32_t fema;
 137     uint32_t fecl;
 138     uint32_t eeen;
 139     uint32_t eest;
 140     uint32_t eecl;
 141     uint32_t eeint;
 142     uint32_t eemck0;
 143     uint32_t eemck1;
 144     /* Error diagnostic */
 145 } XCSR;
 146
 147 static void PPC_XCSR_writeb (void *opaque,
 148                              target_phys_addr_t addr, uint32_t value)
 149 {
 150     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 151            value);
 152 }
 153
 154 static void PPC_XCSR_writew (void *opaque,
 155                              target_phys_addr_t addr, uint32_t value)
 156 {
 157     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 158            value);
 159 }
 160
 161 static void PPC_XCSR_writel (void *opaque,
 162                              target_phys_addr_t addr, uint32_t value)
 163 {
 164     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 165            value);
 166 }
 167
 168 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 169 {
 170     uint32_t retval = 0;
 171
 172     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 173            retval);
 174
 175     return retval;
 176 }
 177
 178 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 179 {
 180     uint32_t retval = 0;
 181
 182     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 183            retval);
 184
 185     return retval;
 186 }
 187
 188 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 189 {
 190     uint32_t retval = 0;
 191
 192     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 193            retval);
 194
 195     return retval;
 196 }
 197
 198 static const MemoryRegionOps PPC_XCSR_ops = {
 199     .old_mmio = {
 200         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 201         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 202     },
 203     .endianness = DEVICE_LITTLE_ENDIAN,
 204 };
 205
 206 #endif
 207
 208 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 209 typedef struct sysctrl_t {
 210     qemu_irq reset_irq;
 211     M48t59State *nvram;
 212     uint8_t state;
 213     uint8_t syscontrol;
 214     uint8_t fake_io[2];
 215     int contiguous_map;
 216     int endian;
 217 } sysctrl_t;
 218
 219 enum {
 220     STATE_HARDFILE = 0x01,
 221 };
 222
 223 static sysctrl_t *sysctrl;
 224
 225 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 226 {
 227     sysctrl_t *sysctrl = opaque;
 228
 229     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 230                    val);
 231     sysctrl->fake_io[addr - 0x0398] = val;
 232 }
 233
 234 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 235 {
 236     sysctrl_t *sysctrl = opaque;
 237
 238     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 239                    sysctrl->fake_io[addr - 0x0398]);
 240     return sysctrl->fake_io[addr - 0x0398];
 241 }
 242
 243 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 244 {
 245     sysctrl_t *sysctrl = opaque;
 246
 247     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 248                    addr - PPC_IO_BASE, val);
 249     switch (addr) {
 250     case 0x0092:
 251         /* Special port 92 */
 252         /* Check soft reset asked */
 253         if (val & 0x01) {
 254             qemu_irq_raise(sysctrl->reset_irq);
 255         } else {
 256             qemu_irq_lower(sysctrl->reset_irq);
 257         }
 258         /* Check LE mode */
 259         if (val & 0x02) {
 260             sysctrl->endian = 1;
 261         } else {
 262             sysctrl->endian = 0;
 263         }
 264         break;
 265     case 0x0800:
 266         /* Motorola CPU configuration register : read-only */
 267         break;
 268     case 0x0802:
 269         /* Motorola base module feature register : read-only */
 270         break;
 271     case 0x0803:
 272         /* Motorola base module status register : read-only */
 273         break;
 274     case 0x0808:
 275         /* Hardfile light register */
 276         if (val & 1)
 277             sysctrl->state |= STATE_HARDFILE;
 278         else
 279             sysctrl->state &= ~STATE_HARDFILE;
 280         break;
 281     case 0x0810:
 282         /* Password protect 1 register */
 283         if (sysctrl->nvram != NULL)
 284             m48t59_toggle_lock(sysctrl->nvram, 1);
 285         break;
 286     case 0x0812:
 287         /* Password protect 2 register */
 288         if (sysctrl->nvram != NULL)
 289             m48t59_toggle_lock(sysctrl->nvram, 2);
 290         break;
 291     case 0x0814:
 292         /* L2 invalidate register */
 293         //        tlb_flush(first_cpu, 1);
 294         break;
 295     case 0x081C:
 296         /* system control register */
 297         sysctrl->syscontrol = val & 0x0F;
 298         break;
 299     case 0x0850:
 300         /* I/O map type register */
 301         sysctrl->contiguous_map = val & 0x01;
 302         break;
 303     default:
 304         printf("ERROR: unaffected IO port write: %04" PRIx32
 305                " => %02" PRIx32"\n", addr, val);
 306         break;
 307     }
 308 }
 309
 310 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 311 {
 312     sysctrl_t *sysctrl = opaque;
 313     uint32_t retval = 0xFF;
 314
 315     switch (addr) {
 316     case 0x0092:
 317         /* Special port 92 */
 318         retval = 0x00;
 319         break;
 320     case 0x0800:
 321         /* Motorola CPU configuration register */
 322         retval = 0xEF; /* MPC750 */
 323         break;
 324     case 0x0802:
 325         /* Motorola Base module feature register */
 326         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 327         break;
 328     case 0x0803:
 329         /* Motorola base module status register */
 330         retval = 0xE0; /* Standard MPC750 */
 331         break;
 332     case 0x080C:
 333         /* Equipment present register:
 334          *  no L2 cache
 335          *  no upgrade processor
 336          *  no cards in PCI slots
 337          *  SCSI fuse is bad
 338          */
 339         retval = 0x3C;
 340         break;
 341     case 0x0810:
 342         /* Motorola base module extended feature register */
 343         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 344         break;
 345     case 0x0814:
 346         /* L2 invalidate: don't care */
 347         break;
 348     case 0x0818:
 349         /* Keylock */
 350         retval = 0x00;
 351         break;
 352     case 0x081C:
 353         /* system control register
 354          * 7 - 6 / 1 - 0: L2 cache enable
 355          */
 356         retval = sysctrl->syscontrol;
 357         break;
 358     case 0x0823:
 359         /* */
 360         retval = 0x03; /* no L2 cache */
 361         break;
 362     case 0x0850:
 363         /* I/O map type register */
 364         retval = sysctrl->contiguous_map;
 365         break;
 366     default:
 367         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 368         break;
 369     }
 370     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 371                    addr - PPC_IO_BASE, retval);
 372
 373     return retval;
 374 }
 375
 376 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 377                                                  target_phys_addr_t addr)
 378 {
 379     if (sysctrl->contiguous_map == 0) {
 380         /* 64 KB contiguous space for IOs */
 381         addr &= 0xFFFF;
 382     } else {
 383         /* 8 MB non-contiguous space for IOs */
 384         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 385     }
 386
 387     return addr;
 388 }
 389
 390 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 391                                 uint32_t value)
 392 {
 393     sysctrl_t *sysctrl = opaque;
 394
 395     addr = prep_IO_address(sysctrl, addr);
 396     cpu_outb(addr, value);
 397 }
 398
 399 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 400 {
 401     sysctrl_t *sysctrl = opaque;
 402     uint32_t ret;
 403
 404     addr = prep_IO_address(sysctrl, addr);
 405     ret = cpu_inb(addr);
 406
 407     return ret;
 408 }
 409
 410 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 411                                 uint32_t value)
 412 {
 413     sysctrl_t *sysctrl = opaque;
 414
 415     addr = prep_IO_address(sysctrl, addr);
 416     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 417     cpu_outw(addr, value);
 418 }
 419
 420 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 421 {
 422     sysctrl_t *sysctrl = opaque;
 423     uint32_t ret;
 424
 425     addr = prep_IO_address(sysctrl, addr);
 426     ret = cpu_inw(addr);
 427     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 428
 429     return ret;
 430 }
 431
 432 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 433                                 uint32_t value)
 434 {
 435     sysctrl_t *sysctrl = opaque;
 436
 437     addr = prep_IO_address(sysctrl, addr);
 438     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 439     cpu_outl(addr, value);
 440 }
 441
 442 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 443 {
 444     sysctrl_t *sysctrl = opaque;
 445     uint32_t ret;
 446
 447     addr = prep_IO_address(sysctrl, addr);
 448     ret = cpu_inl(addr);
 449     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 450
 451     return ret;
 452 }
 453
 454 static const MemoryRegionOps PPC_prep_io_ops = {
 455     .old_mmio = {
 456         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 457         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 458     },
 459     .endianness = DEVICE_LITTLE_ENDIAN,
 460 };
 461
 462 #define NVRAM_SIZE        0x2000
 463
 464 static void cpu_request_exit(void *opaque, int irq, int level)
 465 {
 466     CPUPPCState *env = cpu_single_env;
 467
 468     if (env && level) {
 469         cpu_exit(env);
 470     }
 471 }
 472
 473 static void ppc_prep_reset(void *opaque)
 474 {
 475     CPUPPCState *env = opaque;
 476
 477     cpu_state_reset(env);
 478 }
 479
 480 /* PowerPC PREP hardware initialisation */
 481 static void ppc_prep_init (ram_addr_t ram_size,
 482                            const char *boot_device,
 483                            const char *kernel_filename,
 484                            const char *kernel_cmdline,
 485                            const char *initrd_filename,
 486                            const char *cpu_model)
 487 {
 488     MemoryRegion *sysmem = get_system_memory();
 489     CPUPPCState *env = NULL;
 490     char *filename;
 491     nvram_t nvram;
 492     M48t59State *m48t59;
 493     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 494     MemoryRegion *intack = g_new(MemoryRegion, 1);
 495 #if 0
 496     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 497 #endif
 498     int linux_boot, i, nb_nics1, bios_size;
 499     MemoryRegion *ram = g_new(MemoryRegion, 1);
 500     MemoryRegion *bios = g_new(MemoryRegion, 1);
 501     uint32_t kernel_base, initrd_base;
 502     long kernel_size, initrd_size;
 503     DeviceState *dev;
 504     SysBusDevice *sys;
 505     PCIHostState *pcihost;
 506     PCIBus *pci_bus;
 507     PCIDevice *pci;
 508     ISABus *isa_bus;
 509     qemu_irq *cpu_exit_irq;
 510     int ppc_boot_device;
 511     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 512     DriveInfo *fd[MAX_FD];
 513
 514     sysctrl = g_malloc0(sizeof(sysctrl_t));
 515
 516     linux_boot = (kernel_filename != NULL);
 517
 518     /* init CPUs */
 519     if (cpu_model == NULL)
 520         cpu_model = "602";
 521     for (i = 0; i < smp_cpus; i++) {
 522         env = cpu_init(cpu_model);
 523         if (!env) {
 524             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 525             exit(1);
 526         }
 527         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 528             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 529             cpu_ppc_tb_init(env, 7812500UL);
 530         } else {
 531             /* Set time-base frequency to 100 Mhz */
 532             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 533         }
 534         qemu_register_reset(ppc_prep_reset, env);
 535     }
 536
 537     /* allocate RAM */
 538     memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
 539     vmstate_register_ram_global(ram);
 540     memory_region_add_subregion(sysmem, 0, ram);
 541
 542     /* allocate and load BIOS */
 543     memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
 544     memory_region_set_readonly(bios, true);
 545     memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
 546     vmstate_register_ram_global(bios);
 547     if (bios_name == NULL)
 548         bios_name = BIOS_FILENAME;
 549     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 550     if (filename) {
 551         bios_size = get_image_size(filename);
 552     } else {
 553         bios_size = -1;
 554     }
 555     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 556         target_phys_addr_t bios_addr;
 557         bios_size = (bios_size + 0xfff) & ~0xfff;
 558         bios_addr = (uint32_t)(-bios_size);
 559         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 560     }
 561     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 562         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 563     }
 564     if (filename) {
 565         g_free(filename);
 566     }
 567
 568     if (linux_boot) {
 569         kernel_base = KERNEL_LOAD_ADDR;
 570         /* now we can load the kernel */
 571         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 572                                           ram_size - kernel_base);
 573         if (kernel_size < 0) {
 574             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 575             exit(1);
 576         }
 577         /* load initrd */
 578         if (initrd_filename) {
 579             initrd_base = INITRD_LOAD_ADDR;
 580             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 581                                               ram_size - initrd_base);
 582             if (initrd_size < 0) {
 583                 hw_error("qemu: could not load initial ram disk '%s'\n",
 584                           initrd_filename);
 585             }
 586         } else {
 587             initrd_base = 0;
 588             initrd_size = 0;
 589         }
 590         ppc_boot_device = 'm';
 591     } else {
 592         kernel_base = 0;
 593         kernel_size = 0;
 594         initrd_base = 0;
 595         initrd_size = 0;
 596         ppc_boot_device = '\0';
 597         /* For now, OHW cannot boot from the network. */
 598         for (i = 0; boot_device[i] != '\0'; i++) {
 599             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 600                 ppc_boot_device = boot_device[i];
 601                 break;
 602             }
 603         }
 604         if (ppc_boot_device == '\0') {
 605             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 606             exit(1);
 607         }
 608     }
 609
 610     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 611         hw_error("Only 6xx bus is supported on PREP machine\n");
 612     }
 613
 614     dev = qdev_create(NULL, "raven-pcihost");
 615     sys = sysbus_from_qdev(dev);
 616     pcihost = DO_UPCAST(PCIHostState, busdev, sys);
 617     pcihost->address_space = get_system_memory();
 618     qdev_init_nofail(dev);
 619     object_property_add_child(object_get_root(), "raven", OBJECT(dev), NULL);
 620     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 621     if (pci_bus == NULL) {
 622         fprintf(stderr, "Couldn't create PCI host controller.\n");
 623         exit(1);
 624     }
 625
 626     /* PCI -> ISA bridge */
 627     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 628     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 629     qdev_connect_gpio_out(&pci->qdev, 0,
 630                           first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 631     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 632     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 633     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 634     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 635     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 636     isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
 637
 638     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 639     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 640                           "ppc-io", 0x00800000);
 641     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 642
 643     /* init basic PC hardware */
 644     pci_vga_init(pci_bus);
 645
 646     if (serial_hds[0])
 647         serial_isa_init(isa_bus, 0, serial_hds[0]);
 648     nb_nics1 = nb_nics;
 649     if (nb_nics1 > NE2000_NB_MAX)
 650         nb_nics1 = NE2000_NB_MAX;
 651     for(i = 0; i < nb_nics1; i++) {
 652         if (nd_table[i].model == NULL) {
 653             nd_table[i].model = g_strdup("ne2k_isa");
 654         }
 655         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 656             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 657                             &nd_table[i]);
 658         } else {
 659             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 660         }
 661     }
 662
 663     ide_drive_get(hd, MAX_IDE_BUS);
 664     for(i = 0; i < MAX_IDE_BUS; i++) {
 665         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 666                      hd[2 * i],
 667                      hd[2 * i + 1]);
 668     }
 669     isa_create_simple(isa_bus, "i8042");
 670
 671     //    SB16_init();
 672
 673     for(i = 0; i < MAX_FD; i++) {
 674         fd[i] = drive_get(IF_FLOPPY, 0, i);
 675     }
 676     fdctrl_init_isa(isa_bus, fd);
 677
 678     /* Register fake IO ports for PREP */
 679     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 680     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 681     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 682     /* System control ports */
 683     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 684     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 685     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 686     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 687     /* PCI intack location */
 688     memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4);
 689     memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack);
 690     /* PowerPC control and status register group */
 691 #if 0
 692     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 693     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 694 #endif
 695
 696     if (usb_enabled) {
 697         pci_create_simple(pci_bus, -1, "pci-ohci");
 698     }
 699
 700     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 701     if (m48t59 == NULL)
 702         return;
 703     sysctrl->nvram = m48t59;
 704
 705     /* Initialise NVRAM */
 706     nvram.opaque = m48t59;
 707     nvram.read_fn = &m48t59_read;
 708     nvram.write_fn = &m48t59_write;
 709     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 710                          kernel_base, kernel_size,
 711                          kernel_cmdline,
 712                          initrd_base, initrd_size,
 713                          /* XXX: need an option to load a NVRAM image */
 714                          0,
 715                          graphic_width, graphic_height, graphic_depth);
 716
 717     /* Special port to get debug messages from Open-Firmware */
 718     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 719 }
 720
 721 static QEMUMachine prep_machine = {
 722     .name = "prep",
 723     .desc = "PowerPC PREP platform",
 724     .init = ppc_prep_init,
 725     .max_cpus = MAX_CPUS,
 726 };
 727
 728 static void prep_machine_init(void)
 729 {
 730     qemu_register_machine(&prep_machine);
 731 }
 732
 733 machine_init(prep_machine_init);