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xtensa hw/: Don't use CPUState
[qemu.git] / hw / omap2.c
blob157defb39335d5578210028258df6b0822f14c82
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "blockdev.h"
22 #include "hw.h"
23 #include "arm-misc.h"
24 #include "omap.h"
25 #include "sysemu.h"
26 #include "qemu-timer.h"
27 #include "qemu-char.h"
28 #include "flash.h"
29 #include "soc_dma.h"
30 #include "sysbus.h"
31 #include "audio/audio.h"
32
33 /* Enhanced Audio Controller (CODEC only) */
34 struct omap_eac_s {
35 qemu_irq irq;
36 MemoryRegion iomem;
37
38 uint16_t sysconfig;
39 uint8_t config[4];
40 uint8_t control;
41 uint8_t address;
42 uint16_t data;
43 uint8_t vtol;
44 uint8_t vtsl;
45 uint16_t mixer;
46 uint16_t gain[4];
47 uint8_t att;
48 uint16_t max[7];
49
50 struct {
51 qemu_irq txdrq;
52 qemu_irq rxdrq;
53 uint32_t (*txrx)(void *opaque, uint32_t, int);
54 void *opaque;
55
56 #define EAC_BUF_LEN 1024
57 uint32_t rxbuf[EAC_BUF_LEN];
58 int rxoff;
59 int rxlen;
60 int rxavail;
61 uint32_t txbuf[EAC_BUF_LEN];
62 int txlen;
63 int txavail;
64
65 int enable;
66 int rate;
67
68 uint16_t config[4];
69
70 /* These need to be moved to the actual codec */
71 QEMUSoundCard card;
72 SWVoiceIn *in_voice;
73 SWVoiceOut *out_voice;
74 int hw_enable;
75 } codec;
76
77 struct {
78 uint8_t control;
79 uint16_t config;
80 } modem, bt;
81 };
82
83 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
84 {
85 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
86 }
87
88 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
89 {
90 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
91 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
92 }
93
94 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
95 {
96 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
97 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
98 }
99
100 static inline void omap_eac_in_refill(struct omap_eac_s *s)
101 {
102 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
103 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
104 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
105 int recv = 1;
106 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
107
108 left -= leftwrap;
109 start = 0;
110 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
111 leftwrap)) > 0) { /* Be defensive */
112 start += recv;
113 leftwrap -= recv;
114 }
115 if (recv <= 0)
116 s->codec.rxavail = 0;
117 else
118 s->codec.rxavail -= start >> 2;
119 s->codec.rxlen += start >> 2;
120
121 if (recv > 0 && left > 0) {
122 start = 0;
123 while (left && (recv = AUD_read(s->codec.in_voice,
124 (uint8_t *) s->codec.rxbuf + start,
125 left)) > 0) { /* Be defensive */
126 start += recv;
127 left -= recv;
128 }
129 if (recv <= 0)
130 s->codec.rxavail = 0;
131 else
132 s->codec.rxavail -= start >> 2;
133 s->codec.rxlen += start >> 2;
134 }
135 }
136
137 static inline void omap_eac_out_empty(struct omap_eac_s *s)
138 {
139 int left = s->codec.txlen << 2;
140 int start = 0;
141 int sent = 1;
142
143 while (left && (sent = AUD_write(s->codec.out_voice,
144 (uint8_t *) s->codec.txbuf + start,
145 left)) > 0) { /* Be defensive */
146 start += sent;
147 left -= sent;
148 }
149
150 if (!sent) {
151 s->codec.txavail = 0;
152 omap_eac_out_dmarequest_update(s);
153 }
154
155 if (start)
156 s->codec.txlen = 0;
157 }
158
159 static void omap_eac_in_cb(void *opaque, int avail_b)
160 {
161 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
162
163 s->codec.rxavail = avail_b >> 2;
164 omap_eac_in_refill(s);
165 /* TODO: possibly discard current buffer if overrun */
166 omap_eac_in_dmarequest_update(s);
167 }
168
169 static void omap_eac_out_cb(void *opaque, int free_b)
170 {
171 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
172
173 s->codec.txavail = free_b >> 2;
174 if (s->codec.txlen)
175 omap_eac_out_empty(s);
176 else
177 omap_eac_out_dmarequest_update(s);
178 }
179
180 static void omap_eac_enable_update(struct omap_eac_s *s)
181 {
182 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
183 (s->codec.config[1] & 2) && /* AUDEN */
184 s->codec.hw_enable;
185 }
186
187 static const int omap_eac_fsint[4] = {
188 8000,
189 11025,
190 22050,
191 44100,
192 };
193
194 static const int omap_eac_fsint2[8] = {
195 8000,
196 11025,
197 22050,
198 44100,
199 48000,
200 0, 0, 0,
201 };
202
203 static const int omap_eac_fsint3[16] = {
204 8000,
205 11025,
206 16000,
207 22050,
208 24000,
209 32000,
210 44100,
211 48000,
212 0, 0, 0, 0, 0, 0, 0, 0,
213 };
214
215 static void omap_eac_rate_update(struct omap_eac_s *s)
216 {
217 int fsint[3];
218
219 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
220 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
221 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
222 if (fsint[2] < 0xf)
223 s->codec.rate = omap_eac_fsint3[fsint[2]];
224 else if (fsint[1] < 0x7)
225 s->codec.rate = omap_eac_fsint2[fsint[1]];
226 else
227 s->codec.rate = omap_eac_fsint[fsint[0]];
228 }
229
230 static void omap_eac_volume_update(struct omap_eac_s *s)
231 {
232 /* TODO */
233 }
234
235 static void omap_eac_format_update(struct omap_eac_s *s)
236 {
237 struct audsettings fmt;
238
239 /* The hardware buffers at most one sample */
240 if (s->codec.rxlen)
241 s->codec.rxlen = 1;
242
243 if (s->codec.in_voice) {
244 AUD_set_active_in(s->codec.in_voice, 0);
245 AUD_close_in(&s->codec.card, s->codec.in_voice);
246 s->codec.in_voice = NULL;
247 }
248 if (s->codec.out_voice) {
249 omap_eac_out_empty(s);
250 AUD_set_active_out(s->codec.out_voice, 0);
251 AUD_close_out(&s->codec.card, s->codec.out_voice);
252 s->codec.out_voice = NULL;
253 s->codec.txavail = 0;
254 }
255 /* Discard what couldn't be written */
256 s->codec.txlen = 0;
257
258 omap_eac_enable_update(s);
259 if (!s->codec.enable)
260 return;
261
262 omap_eac_rate_update(s);
263 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
264 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
265 fmt.freq = s->codec.rate;
266 /* TODO: signedness possibly depends on the CODEC hardware - or
267 * does I2S specify it? */
268 /* All register writes are 16 bits so we we store 16-bit samples
269 * in the buffers regardless of AGCFR[B8_16] value. */
270 fmt.fmt = AUD_FMT_U16;
271
272 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
273 "eac.codec.in", s, omap_eac_in_cb, &fmt);
274 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
275 "eac.codec.out", s, omap_eac_out_cb, &fmt);
276
277 omap_eac_volume_update(s);
278
279 AUD_set_active_in(s->codec.in_voice, 1);
280 AUD_set_active_out(s->codec.out_voice, 1);
281 }
282
283 static void omap_eac_reset(struct omap_eac_s *s)
284 {
285 s->sysconfig = 0;
286 s->config[0] = 0x0c;
287 s->config[1] = 0x09;
288 s->config[2] = 0xab;
289 s->config[3] = 0x03;
290 s->control = 0x00;
291 s->address = 0x00;
292 s->data = 0x0000;
293 s->vtol = 0x00;
294 s->vtsl = 0x00;
295 s->mixer = 0x0000;
296 s->gain[0] = 0xe7e7;
297 s->gain[1] = 0x6767;
298 s->gain[2] = 0x6767;
299 s->gain[3] = 0x6767;
300 s->att = 0xce;
301 s->max[0] = 0;
302 s->max[1] = 0;
303 s->max[2] = 0;
304 s->max[3] = 0;
305 s->max[4] = 0;
306 s->max[5] = 0;
307 s->max[6] = 0;
308
309 s->modem.control = 0x00;
310 s->modem.config = 0x0000;
311 s->bt.control = 0x00;
312 s->bt.config = 0x0000;
313 s->codec.config[0] = 0x0649;
314 s->codec.config[1] = 0x0000;
315 s->codec.config[2] = 0x0007;
316 s->codec.config[3] = 0x1ffc;
317 s->codec.rxoff = 0;
318 s->codec.rxlen = 0;
319 s->codec.txlen = 0;
320 s->codec.rxavail = 0;
321 s->codec.txavail = 0;
322
323 omap_eac_format_update(s);
324 omap_eac_interrupt_update(s);
325 }
326
327 static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
328 unsigned size)
329 {
330 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
331 uint32_t ret;
332
333 if (size != 2) {
334 return omap_badwidth_read16(opaque, addr);
335 }
336
337 switch (addr) {
338 case 0x000: /* CPCFR1 */
339 return s->config[0];
340 case 0x004: /* CPCFR2 */
341 return s->config[1];
342 case 0x008: /* CPCFR3 */
343 return s->config[2];
344 case 0x00c: /* CPCFR4 */
345 return s->config[3];
346
347 case 0x010: /* CPTCTL */
348 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
349 ((s->codec.txlen < s->codec.txavail) << 5);
350
351 case 0x014: /* CPTTADR */
352 return s->address;
353 case 0x018: /* CPTDATL */
354 return s->data & 0xff;
355 case 0x01c: /* CPTDATH */
356 return s->data >> 8;
357 case 0x020: /* CPTVSLL */
358 return s->vtol;
359 case 0x024: /* CPTVSLH */
360 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
361 case 0x040: /* MPCTR */
362 return s->modem.control;
363 case 0x044: /* MPMCCFR */
364 return s->modem.config;
365 case 0x060: /* BPCTR */
366 return s->bt.control;
367 case 0x064: /* BPMCCFR */
368 return s->bt.config;
369 case 0x080: /* AMSCFR */
370 return s->mixer;
371 case 0x084: /* AMVCTR */
372 return s->gain[0];
373 case 0x088: /* AM1VCTR */
374 return s->gain[1];
375 case 0x08c: /* AM2VCTR */
376 return s->gain[2];
377 case 0x090: /* AM3VCTR */
378 return s->gain[3];
379 case 0x094: /* ASTCTR */
380 return s->att;
381 case 0x098: /* APD1LCR */
382 return s->max[0];
383 case 0x09c: /* APD1RCR */
384 return s->max[1];
385 case 0x0a0: /* APD2LCR */
386 return s->max[2];
387 case 0x0a4: /* APD2RCR */
388 return s->max[3];
389 case 0x0a8: /* APD3LCR */
390 return s->max[4];
391 case 0x0ac: /* APD3RCR */
392 return s->max[5];
393 case 0x0b0: /* APD4R */
394 return s->max[6];
395 case 0x0b4: /* ADWR */
396 /* This should be write-only? Docs list it as read-only. */
397 return 0x0000;
398 case 0x0b8: /* ADRDR */
399 if (likely(s->codec.rxlen > 1)) {
400 ret = s->codec.rxbuf[s->codec.rxoff ++];
401 s->codec.rxlen --;
402 s->codec.rxoff &= EAC_BUF_LEN - 1;
403 return ret;
404 } else if (s->codec.rxlen) {
405 ret = s->codec.rxbuf[s->codec.rxoff ++];
406 s->codec.rxlen --;
407 s->codec.rxoff &= EAC_BUF_LEN - 1;
408 if (s->codec.rxavail)
409 omap_eac_in_refill(s);
410 omap_eac_in_dmarequest_update(s);
411 return ret;
412 }
413 return 0x0000;
414 case 0x0bc: /* AGCFR */
415 return s->codec.config[0];
416 case 0x0c0: /* AGCTR */
417 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
418 case 0x0c4: /* AGCFR2 */
419 return s->codec.config[2];
420 case 0x0c8: /* AGCFR3 */
421 return s->codec.config[3];
422 case 0x0cc: /* MBPDMACTR */
423 case 0x0d0: /* MPDDMARR */
424 case 0x0d8: /* MPUDMARR */
425 case 0x0e4: /* BPDDMARR */
426 case 0x0ec: /* BPUDMARR */
427 return 0x0000;
428
429 case 0x100: /* VERSION_NUMBER */
430 return 0x0010;
431
432 case 0x104: /* SYSCONFIG */
433 return s->sysconfig;
434
435 case 0x108: /* SYSSTATUS */
436 return 1 | 0xe; /* RESETDONE | stuff */
437 }
438
439 OMAP_BAD_REG(addr);
440 return 0;
441 }
442
443 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
444 uint64_t value, unsigned size)
445 {
446 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
447
448 if (size != 2) {
449 return omap_badwidth_write16(opaque, addr, value);
450 }
451
452 switch (addr) {
453 case 0x098: /* APD1LCR */
454 case 0x09c: /* APD1RCR */
455 case 0x0a0: /* APD2LCR */
456 case 0x0a4: /* APD2RCR */
457 case 0x0a8: /* APD3LCR */
458 case 0x0ac: /* APD3RCR */
459 case 0x0b0: /* APD4R */
460 case 0x0b8: /* ADRDR */
461 case 0x0d0: /* MPDDMARR */
462 case 0x0d8: /* MPUDMARR */
463 case 0x0e4: /* BPDDMARR */
464 case 0x0ec: /* BPUDMARR */
465 case 0x100: /* VERSION_NUMBER */
466 case 0x108: /* SYSSTATUS */
467 OMAP_RO_REG(addr);
468 return;
469
470 case 0x000: /* CPCFR1 */
471 s->config[0] = value & 0xff;
472 omap_eac_format_update(s);
473 break;
474 case 0x004: /* CPCFR2 */
475 s->config[1] = value & 0xff;
476 omap_eac_format_update(s);
477 break;
478 case 0x008: /* CPCFR3 */
479 s->config[2] = value & 0xff;
480 omap_eac_format_update(s);
481 break;
482 case 0x00c: /* CPCFR4 */
483 s->config[3] = value & 0xff;
484 omap_eac_format_update(s);
485 break;
486
487 case 0x010: /* CPTCTL */
488 /* Assuming TXF and TXE bits are read-only... */
489 s->control = value & 0x5f;
490 omap_eac_interrupt_update(s);
491 break;
492
493 case 0x014: /* CPTTADR */
494 s->address = value & 0xff;
495 break;
496 case 0x018: /* CPTDATL */
497 s->data &= 0xff00;
498 s->data |= value & 0xff;
499 break;
500 case 0x01c: /* CPTDATH */
501 s->data &= 0x00ff;
502 s->data |= value << 8;
503 break;
504 case 0x020: /* CPTVSLL */
505 s->vtol = value & 0xf8;
506 break;
507 case 0x024: /* CPTVSLH */
508 s->vtsl = value & 0x9f;
509 break;
510 case 0x040: /* MPCTR */
511 s->modem.control = value & 0x8f;
512 break;
513 case 0x044: /* MPMCCFR */
514 s->modem.config = value & 0x7fff;
515 break;
516 case 0x060: /* BPCTR */
517 s->bt.control = value & 0x8f;
518 break;
519 case 0x064: /* BPMCCFR */
520 s->bt.config = value & 0x7fff;
521 break;
522 case 0x080: /* AMSCFR */
523 s->mixer = value & 0x0fff;
524 break;
525 case 0x084: /* AMVCTR */
526 s->gain[0] = value & 0xffff;
527 break;
528 case 0x088: /* AM1VCTR */
529 s->gain[1] = value & 0xff7f;
530 break;
531 case 0x08c: /* AM2VCTR */
532 s->gain[2] = value & 0xff7f;
533 break;
534 case 0x090: /* AM3VCTR */
535 s->gain[3] = value & 0xff7f;
536 break;
537 case 0x094: /* ASTCTR */
538 s->att = value & 0xff;
539 break;
540
541 case 0x0b4: /* ADWR */
542 s->codec.txbuf[s->codec.txlen ++] = value;
543 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
544 s->codec.txlen == s->codec.txavail)) {
545 if (s->codec.txavail)
546 omap_eac_out_empty(s);
547 /* Discard what couldn't be written */
548 s->codec.txlen = 0;
549 }
550 break;
551
552 case 0x0bc: /* AGCFR */
553 s->codec.config[0] = value & 0x07ff;
554 omap_eac_format_update(s);
555 break;
556 case 0x0c0: /* AGCTR */
557 s->codec.config[1] = value & 0x780f;
558 omap_eac_format_update(s);
559 break;
560 case 0x0c4: /* AGCFR2 */
561 s->codec.config[2] = value & 0x003f;
562 omap_eac_format_update(s);
563 break;
564 case 0x0c8: /* AGCFR3 */
565 s->codec.config[3] = value & 0xffff;
566 omap_eac_format_update(s);
567 break;
568 case 0x0cc: /* MBPDMACTR */
569 case 0x0d4: /* MPDDMAWR */
570 case 0x0e0: /* MPUDMAWR */
571 case 0x0e8: /* BPDDMAWR */
572 case 0x0f0: /* BPUDMAWR */
573 break;
574
575 case 0x104: /* SYSCONFIG */
576 if (value & (1 << 1)) /* SOFTRESET */
577 omap_eac_reset(s);
578 s->sysconfig = value & 0x31d;
579 break;
580
581 default:
582 OMAP_BAD_REG(addr);
583 return;
584 }
585 }
586
587 static const MemoryRegionOps omap_eac_ops = {
588 .read = omap_eac_read,
589 .write = omap_eac_write,
590 .endianness = DEVICE_NATIVE_ENDIAN,
591 };
592
593 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
594 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
595 {
596 struct omap_eac_s *s = (struct omap_eac_s *)
597 g_malloc0(sizeof(struct omap_eac_s));
598
599 s->irq = irq;
600 s->codec.rxdrq = *drq ++;
601 s->codec.txdrq = *drq;
602 omap_eac_reset(s);
603
604 AUD_register_card("OMAP EAC", &s->codec.card);
605
606 memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac",
607 omap_l4_region_size(ta, 0));
608 omap_l4_attach(ta, 0, &s->iomem);
609
610 return s;
611 }
612
613 /* STI/XTI (emulation interface) console - reverse engineered only */
614 struct omap_sti_s {
615 qemu_irq irq;
616 MemoryRegion iomem;
617 MemoryRegion iomem_fifo;
618 CharDriverState *chr;
619
620 uint32_t sysconfig;
621 uint32_t systest;
622 uint32_t irqst;
623 uint32_t irqen;
624 uint32_t clkcontrol;
625 uint32_t serial_config;
626 };
627
628 #define STI_TRACE_CONSOLE_CHANNEL 239
629 #define STI_TRACE_CONTROL_CHANNEL 253
630
631 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
632 {
633 qemu_set_irq(s->irq, s->irqst & s->irqen);
634 }
635
636 static void omap_sti_reset(struct omap_sti_s *s)
637 {
638 s->sysconfig = 0;
639 s->irqst = 0;
640 s->irqen = 0;
641 s->clkcontrol = 0;
642 s->serial_config = 0;
643
644 omap_sti_interrupt_update(s);
645 }
646
647 static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
648 unsigned size)
649 {
650 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
651
652 if (size != 4) {
653 return omap_badwidth_read32(opaque, addr);
654 }
655
656 switch (addr) {
657 case 0x00: /* STI_REVISION */
658 return 0x10;
659
660 case 0x10: /* STI_SYSCONFIG */
661 return s->sysconfig;
662
663 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
664 return 0x00;
665
666 case 0x18: /* STI_IRQSTATUS */
667 return s->irqst;
668
669 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
670 return s->irqen;
671
672 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
673 case 0x28: /* STI_RX_DR / XTI_RXDATA */
674 /* TODO */
675 return 0;
676
677 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
678 return s->clkcontrol;
679
680 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
681 return s->serial_config;
682 }
683
684 OMAP_BAD_REG(addr);
685 return 0;
686 }
687
688 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
689 uint64_t value, unsigned size)
690 {
691 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
692
693 if (size != 4) {
694 return omap_badwidth_write32(opaque, addr, value);
695 }
696
697 switch (addr) {
698 case 0x00: /* STI_REVISION */
699 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
700 OMAP_RO_REG(addr);
701 return;
702
703 case 0x10: /* STI_SYSCONFIG */
704 if (value & (1 << 1)) /* SOFTRESET */
705 omap_sti_reset(s);
706 s->sysconfig = value & 0xfe;
707 break;
708
709 case 0x18: /* STI_IRQSTATUS */
710 s->irqst &= ~value;
711 omap_sti_interrupt_update(s);
712 break;
713
714 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
715 s->irqen = value & 0xffff;
716 omap_sti_interrupt_update(s);
717 break;
718
719 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
720 s->clkcontrol = value & 0xff;
721 break;
722
723 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
724 s->serial_config = value & 0xff;
725 break;
726
727 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
728 case 0x28: /* STI_RX_DR / XTI_RXDATA */
729 /* TODO */
730 return;
731
732 default:
733 OMAP_BAD_REG(addr);
734 return;
735 }
736 }
737
738 static const MemoryRegionOps omap_sti_ops = {
739 .read = omap_sti_read,
740 .write = omap_sti_write,
741 .endianness = DEVICE_NATIVE_ENDIAN,
742 };
743
744 static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
745 unsigned size)
746 {
747 OMAP_BAD_REG(addr);
748 return 0;
749 }
750
751 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
752 uint64_t value, unsigned size)
753 {
754 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
755 int ch = addr >> 6;
756 uint8_t byte = value;
757
758 if (size != 1) {
759 return omap_badwidth_write8(opaque, addr, size);
760 }
761
762 if (ch == STI_TRACE_CONTROL_CHANNEL) {
763 /* Flush channel <i>value</i>. */
764 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
765 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
766 if (value == 0xc0 || value == 0xc3) {
767 /* Open channel <i>ch</i>. */
768 } else if (value == 0x00)
769 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
770 else
771 qemu_chr_fe_write(s->chr, &byte, 1);
772 }
773 }
774
775 static const MemoryRegionOps omap_sti_fifo_ops = {
776 .read = omap_sti_fifo_read,
777 .write = omap_sti_fifo_write,
778 .endianness = DEVICE_NATIVE_ENDIAN,
779 };
780
781 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
782 MemoryRegion *sysmem,
783 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
784 CharDriverState *chr)
785 {
786 struct omap_sti_s *s = (struct omap_sti_s *)
787 g_malloc0(sizeof(struct omap_sti_s));
788
789 s->irq = irq;
790 omap_sti_reset(s);
791
792 s->chr = chr ?: qemu_chr_new("null", "null", NULL);
793
794 memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti",
795 omap_l4_region_size(ta, 0));
796 omap_l4_attach(ta, 0, &s->iomem);
797
798 memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s,
799 "omap.sti.fifo", 0x10000);
800 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
801
802 return s;
803 }
804
805 /* L4 Interconnect */
806 #define L4TA(n) (n)
807 #define L4TAO(n) ((n) + 39)
808
809 static const struct omap_l4_region_s omap_l4_region[125] = {
810 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
811 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
812 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
813 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
814 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
815 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
816 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
817 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
818 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
819 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
820 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
821 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
822 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
823 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
824 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
825 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
826 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
827 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
828 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
829 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
830 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
831 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
832 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
833 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
834 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
835 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
836 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
837 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
838 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
839 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
840 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
841 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
842 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
843 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
844 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
845 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
846 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
847 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
848 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
849 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
850 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
851 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
852 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
853 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
854 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
855 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
856 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
857 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
858 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
859 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
860 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
861 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
862 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
863 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
864 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
865 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
866 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
867 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
868 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
869 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
870 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
871 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
872 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
873 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
874 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
875 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
876 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
877 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
878 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
879 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
880 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
881 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
882 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
883 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
884 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
885 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
886 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
887 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
888 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
889 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
890 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
891 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
892 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
893 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
894 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
895 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
896 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
897 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
898 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
899 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
900 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
901 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
902 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
903 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
904 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
905 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
906 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
907 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
908 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
909 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
910 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
911 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
912 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
913 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
914 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
915 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
916 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
917 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
918 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
919 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
920 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
921 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
922 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
923 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
924 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
925 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
926 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
927 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
928 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
929 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
930 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
931 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
932 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
933 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
934 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
935 };
936
937 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
938 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
939 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
940 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
941 { L4TAO(3), 7, 3, 2 }, /* PRCM */
942 { L4TA(1), 10, 2, 1 }, /* BCM */
943 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
944 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
945 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
946 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
947 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
948 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
949 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
950 { L4TA(12), 38, 2, 1 }, /* sDMA */
951 { L4TA(13), 40, 5, 4 }, /* SSI */
952 { L4TAO(4), 45, 2, 1 }, /* USB */
953 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
954 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
955 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
956 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
957 { L4TA(18), 55, 2, 1 }, /* XTI */
958 { L4TA(19), 57, 2, 1 }, /* UART1 */
959 { L4TA(20), 59, 2, 1 }, /* UART2 */
960 { L4TA(21), 61, 2, 1 }, /* UART3 */
961 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
962 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
963 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
964 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
965 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
966 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
967 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
968 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
969 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
970 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
971 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
972 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
973 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
974 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
975 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
976 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
977 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
978 { L4TA(32), 97, 2, 1 }, /* EAC */
979 { L4TA(33), 99, 2, 1 }, /* FAC */
980 { L4TA(34), 101, 2, 1 }, /* IPC */
981 { L4TA(35), 103, 2, 1 }, /* SPI1 */
982 { L4TA(36), 105, 2, 1 }, /* SPI2 */
983 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
984 { L4TAO(10), 109, 2, 1 },
985 { L4TAO(11), 111, 2, 1 }, /* RNG */
986 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
987 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
988 { L4TA(37), 117, 2, 1 }, /* AES */
989 { L4TA(38), 119, 2, 1 }, /* PKA */
990 { -1, 121, 2, 1 },
991 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
992 };
993
994 #define omap_l4ta(bus, cs) \
995 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
996 #define omap_l4tao(bus, cs) \
997 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
998
999 /* Power, Reset, and Clock Management */
1000 struct omap_prcm_s {
1001 qemu_irq irq[3];
1002 struct omap_mpu_state_s *mpu;
1003 MemoryRegion iomem0;
1004 MemoryRegion iomem1;
1005
1006 uint32_t irqst[3];
1007 uint32_t irqen[3];
1008
1009 uint32_t sysconfig;
1010 uint32_t voltctrl;
1011 uint32_t scratch[20];
1012
1013 uint32_t clksrc[1];
1014 uint32_t clkout[1];
1015 uint32_t clkemul[1];
1016 uint32_t clkpol[1];
1017 uint32_t clksel[8];
1018 uint32_t clken[12];
1019 uint32_t clkctrl[4];
1020 uint32_t clkidle[7];
1021 uint32_t setuptime[2];
1022
1023 uint32_t wkup[3];
1024 uint32_t wken[3];
1025 uint32_t wkst[3];
1026 uint32_t rst[4];
1027 uint32_t rstctrl[1];
1028 uint32_t power[4];
1029 uint32_t rsttime_wkup;
1030
1031 uint32_t ev;
1032 uint32_t evtime[2];
1033
1034 int dpll_lock, apll_lock[2];
1035 };
1036
1037 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1038 {
1039 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1040 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1041 }
1042
1043 static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
1044 unsigned size)
1045 {
1046 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1047 uint32_t ret;
1048
1049 if (size != 4) {
1050 return omap_badwidth_read32(opaque, addr);
1051 }
1052
1053 switch (addr) {
1054 case 0x000: /* PRCM_REVISION */
1055 return 0x10;
1056
1057 case 0x010: /* PRCM_SYSCONFIG */
1058 return s->sysconfig;
1059
1060 case 0x018: /* PRCM_IRQSTATUS_MPU */
1061 return s->irqst[0];
1062
1063 case 0x01c: /* PRCM_IRQENABLE_MPU */
1064 return s->irqen[0];
1065
1066 case 0x050: /* PRCM_VOLTCTRL */
1067 return s->voltctrl;
1068 case 0x054: /* PRCM_VOLTST */
1069 return s->voltctrl & 3;
1070
1071 case 0x060: /* PRCM_CLKSRC_CTRL */
1072 return s->clksrc[0];
1073 case 0x070: /* PRCM_CLKOUT_CTRL */
1074 return s->clkout[0];
1075 case 0x078: /* PRCM_CLKEMUL_CTRL */
1076 return s->clkemul[0];
1077 case 0x080: /* PRCM_CLKCFG_CTRL */
1078 case 0x084: /* PRCM_CLKCFG_STATUS */
1079 return 0;
1080
1081 case 0x090: /* PRCM_VOLTSETUP */
1082 return s->setuptime[0];
1083
1084 case 0x094: /* PRCM_CLKSSETUP */
1085 return s->setuptime[1];
1086
1087 case 0x098: /* PRCM_POLCTRL */
1088 return s->clkpol[0];
1089
1090 case 0x0b0: /* GENERAL_PURPOSE1 */
1091 case 0x0b4: /* GENERAL_PURPOSE2 */
1092 case 0x0b8: /* GENERAL_PURPOSE3 */
1093 case 0x0bc: /* GENERAL_PURPOSE4 */
1094 case 0x0c0: /* GENERAL_PURPOSE5 */
1095 case 0x0c4: /* GENERAL_PURPOSE6 */
1096 case 0x0c8: /* GENERAL_PURPOSE7 */
1097 case 0x0cc: /* GENERAL_PURPOSE8 */
1098 case 0x0d0: /* GENERAL_PURPOSE9 */
1099 case 0x0d4: /* GENERAL_PURPOSE10 */
1100 case 0x0d8: /* GENERAL_PURPOSE11 */
1101 case 0x0dc: /* GENERAL_PURPOSE12 */
1102 case 0x0e0: /* GENERAL_PURPOSE13 */
1103 case 0x0e4: /* GENERAL_PURPOSE14 */
1104 case 0x0e8: /* GENERAL_PURPOSE15 */
1105 case 0x0ec: /* GENERAL_PURPOSE16 */
1106 case 0x0f0: /* GENERAL_PURPOSE17 */
1107 case 0x0f4: /* GENERAL_PURPOSE18 */
1108 case 0x0f8: /* GENERAL_PURPOSE19 */
1109 case 0x0fc: /* GENERAL_PURPOSE20 */
1110 return s->scratch[(addr - 0xb0) >> 2];
1111
1112 case 0x140: /* CM_CLKSEL_MPU */
1113 return s->clksel[0];
1114 case 0x148: /* CM_CLKSTCTRL_MPU */
1115 return s->clkctrl[0];
1116
1117 case 0x158: /* RM_RSTST_MPU */
1118 return s->rst[0];
1119 case 0x1c8: /* PM_WKDEP_MPU */
1120 return s->wkup[0];
1121 case 0x1d4: /* PM_EVGENCTRL_MPU */
1122 return s->ev;
1123 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1124 return s->evtime[0];
1125 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1126 return s->evtime[1];
1127 case 0x1e0: /* PM_PWSTCTRL_MPU */
1128 return s->power[0];
1129 case 0x1e4: /* PM_PWSTST_MPU */
1130 return 0;
1131
1132 case 0x200: /* CM_FCLKEN1_CORE */
1133 return s->clken[0];
1134 case 0x204: /* CM_FCLKEN2_CORE */
1135 return s->clken[1];
1136 case 0x210: /* CM_ICLKEN1_CORE */
1137 return s->clken[2];
1138 case 0x214: /* CM_ICLKEN2_CORE */
1139 return s->clken[3];
1140 case 0x21c: /* CM_ICLKEN4_CORE */
1141 return s->clken[4];
1142
1143 case 0x220: /* CM_IDLEST1_CORE */
1144 /* TODO: check the actual iclk status */
1145 return 0x7ffffff9;
1146 case 0x224: /* CM_IDLEST2_CORE */
1147 /* TODO: check the actual iclk status */
1148 return 0x00000007;
1149 case 0x22c: /* CM_IDLEST4_CORE */
1150 /* TODO: check the actual iclk status */
1151 return 0x0000001f;
1152
1153 case 0x230: /* CM_AUTOIDLE1_CORE */
1154 return s->clkidle[0];
1155 case 0x234: /* CM_AUTOIDLE2_CORE */
1156 return s->clkidle[1];
1157 case 0x238: /* CM_AUTOIDLE3_CORE */
1158 return s->clkidle[2];
1159 case 0x23c: /* CM_AUTOIDLE4_CORE */
1160 return s->clkidle[3];
1161
1162 case 0x240: /* CM_CLKSEL1_CORE */
1163 return s->clksel[1];
1164 case 0x244: /* CM_CLKSEL2_CORE */
1165 return s->clksel[2];
1166
1167 case 0x248: /* CM_CLKSTCTRL_CORE */
1168 return s->clkctrl[1];
1169
1170 case 0x2a0: /* PM_WKEN1_CORE */
1171 return s->wken[0];
1172 case 0x2a4: /* PM_WKEN2_CORE */
1173 return s->wken[1];
1174
1175 case 0x2b0: /* PM_WKST1_CORE */
1176 return s->wkst[0];
1177 case 0x2b4: /* PM_WKST2_CORE */
1178 return s->wkst[1];
1179 case 0x2c8: /* PM_WKDEP_CORE */
1180 return 0x1e;
1181
1182 case 0x2e0: /* PM_PWSTCTRL_CORE */
1183 return s->power[1];
1184 case 0x2e4: /* PM_PWSTST_CORE */
1185 return 0x000030 | (s->power[1] & 0xfc00);
1186
1187 case 0x300: /* CM_FCLKEN_GFX */
1188 return s->clken[5];
1189 case 0x310: /* CM_ICLKEN_GFX */
1190 return s->clken[6];
1191 case 0x320: /* CM_IDLEST_GFX */
1192 /* TODO: check the actual iclk status */
1193 return 0x00000001;
1194 case 0x340: /* CM_CLKSEL_GFX */
1195 return s->clksel[3];
1196 case 0x348: /* CM_CLKSTCTRL_GFX */
1197 return s->clkctrl[2];
1198 case 0x350: /* RM_RSTCTRL_GFX */
1199 return s->rstctrl[0];
1200 case 0x358: /* RM_RSTST_GFX */
1201 return s->rst[1];
1202 case 0x3c8: /* PM_WKDEP_GFX */
1203 return s->wkup[1];
1204
1205 case 0x3e0: /* PM_PWSTCTRL_GFX */
1206 return s->power[2];
1207 case 0x3e4: /* PM_PWSTST_GFX */
1208 return s->power[2] & 3;
1209
1210 case 0x400: /* CM_FCLKEN_WKUP */
1211 return s->clken[7];
1212 case 0x410: /* CM_ICLKEN_WKUP */
1213 return s->clken[8];
1214 case 0x420: /* CM_IDLEST_WKUP */
1215 /* TODO: check the actual iclk status */
1216 return 0x0000003f;
1217 case 0x430: /* CM_AUTOIDLE_WKUP */
1218 return s->clkidle[4];
1219 case 0x440: /* CM_CLKSEL_WKUP */
1220 return s->clksel[4];
1221 case 0x450: /* RM_RSTCTRL_WKUP */
1222 return 0;
1223 case 0x454: /* RM_RSTTIME_WKUP */
1224 return s->rsttime_wkup;
1225 case 0x458: /* RM_RSTST_WKUP */
1226 return s->rst[2];
1227 case 0x4a0: /* PM_WKEN_WKUP */
1228 return s->wken[2];
1229 case 0x4b0: /* PM_WKST_WKUP */
1230 return s->wkst[2];
1231
1232 case 0x500: /* CM_CLKEN_PLL */
1233 return s->clken[9];
1234 case 0x520: /* CM_IDLEST_CKGEN */
1235 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1236 if (!(s->clksel[6] & 3))
1237 /* Core uses 32-kHz clock */
1238 ret |= 3 << 0;
1239 else if (!s->dpll_lock)
1240 /* DPLL not locked, core uses ref_clk */
1241 ret |= 1 << 0;
1242 else
1243 /* Core uses DPLL */
1244 ret |= 2 << 0;
1245 return ret;
1246 case 0x530: /* CM_AUTOIDLE_PLL */
1247 return s->clkidle[5];
1248 case 0x540: /* CM_CLKSEL1_PLL */
1249 return s->clksel[5];
1250 case 0x544: /* CM_CLKSEL2_PLL */
1251 return s->clksel[6];
1252
1253 case 0x800: /* CM_FCLKEN_DSP */
1254 return s->clken[10];
1255 case 0x810: /* CM_ICLKEN_DSP */
1256 return s->clken[11];
1257 case 0x820: /* CM_IDLEST_DSP */
1258 /* TODO: check the actual iclk status */
1259 return 0x00000103;
1260 case 0x830: /* CM_AUTOIDLE_DSP */
1261 return s->clkidle[6];
1262 case 0x840: /* CM_CLKSEL_DSP */
1263 return s->clksel[7];
1264 case 0x848: /* CM_CLKSTCTRL_DSP */
1265 return s->clkctrl[3];
1266 case 0x850: /* RM_RSTCTRL_DSP */
1267 return 0;
1268 case 0x858: /* RM_RSTST_DSP */
1269 return s->rst[3];
1270 case 0x8c8: /* PM_WKDEP_DSP */
1271 return s->wkup[2];
1272 case 0x8e0: /* PM_PWSTCTRL_DSP */
1273 return s->power[3];
1274 case 0x8e4: /* PM_PWSTST_DSP */
1275 return 0x008030 | (s->power[3] & 0x3003);
1276
1277 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1278 return s->irqst[1];
1279 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1280 return s->irqen[1];
1281
1282 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1283 return s->irqst[2];
1284 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1285 return s->irqen[2];
1286 }
1287
1288 OMAP_BAD_REG(addr);
1289 return 0;
1290 }
1291
1292 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1293 {
1294 int mode[2];
1295
1296 mode[0] = (s->clken[9] >> 6) & 3;
1297 s->apll_lock[0] = (mode[0] == 3);
1298 mode[1] = (s->clken[9] >> 2) & 3;
1299 s->apll_lock[1] = (mode[1] == 3);
1300 /* TODO: update clocks */
1301
1302 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1303 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1304 __FUNCTION__);
1305 }
1306
1307 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1308 {
1309 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1310 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1311 omap_clk core = omap_findclk(s->mpu, "core_clk");
1312 int mode = (s->clken[9] >> 0) & 3;
1313 int mult, div;
1314
1315 mult = (s->clksel[5] >> 12) & 0x3ff;
1316 div = (s->clksel[5] >> 8) & 0xf;
1317 if (mult == 0 || mult == 1)
1318 mode = 1; /* Bypass */
1319
1320 s->dpll_lock = 0;
1321 switch (mode) {
1322 case 0:
1323 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
1324 break;
1325 case 1: /* Low-power bypass mode (Default) */
1326 case 2: /* Fast-relock bypass mode */
1327 omap_clk_setrate(dpll, 1, 1);
1328 omap_clk_setrate(dpll_x2, 1, 1);
1329 break;
1330 case 3: /* Lock mode */
1331 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1332
1333 omap_clk_setrate(dpll, div + 1, mult);
1334 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1335 break;
1336 }
1337
1338 switch ((s->clksel[6] >> 0) & 3) {
1339 case 0:
1340 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1341 break;
1342 case 1:
1343 omap_clk_reparent(core, dpll);
1344 break;
1345 case 2:
1346 /* Default */
1347 omap_clk_reparent(core, dpll_x2);
1348 break;
1349 case 3:
1350 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
1351 break;
1352 }
1353 }
1354
1355 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
1356 uint64_t value, unsigned size)
1357 {
1358 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1359
1360 if (size != 4) {
1361 return omap_badwidth_write32(opaque, addr, value);
1362 }
1363
1364 switch (addr) {
1365 case 0x000: /* PRCM_REVISION */
1366 case 0x054: /* PRCM_VOLTST */
1367 case 0x084: /* PRCM_CLKCFG_STATUS */
1368 case 0x1e4: /* PM_PWSTST_MPU */
1369 case 0x220: /* CM_IDLEST1_CORE */
1370 case 0x224: /* CM_IDLEST2_CORE */
1371 case 0x22c: /* CM_IDLEST4_CORE */
1372 case 0x2c8: /* PM_WKDEP_CORE */
1373 case 0x2e4: /* PM_PWSTST_CORE */
1374 case 0x320: /* CM_IDLEST_GFX */
1375 case 0x3e4: /* PM_PWSTST_GFX */
1376 case 0x420: /* CM_IDLEST_WKUP */
1377 case 0x520: /* CM_IDLEST_CKGEN */
1378 case 0x820: /* CM_IDLEST_DSP */
1379 case 0x8e4: /* PM_PWSTST_DSP */
1380 OMAP_RO_REG(addr);
1381 return;
1382
1383 case 0x010: /* PRCM_SYSCONFIG */
1384 s->sysconfig = value & 1;
1385 break;
1386
1387 case 0x018: /* PRCM_IRQSTATUS_MPU */
1388 s->irqst[0] &= ~value;
1389 omap_prcm_int_update(s, 0);
1390 break;
1391 case 0x01c: /* PRCM_IRQENABLE_MPU */
1392 s->irqen[0] = value & 0x3f;
1393 omap_prcm_int_update(s, 0);
1394 break;
1395
1396 case 0x050: /* PRCM_VOLTCTRL */
1397 s->voltctrl = value & 0xf1c3;
1398 break;
1399
1400 case 0x060: /* PRCM_CLKSRC_CTRL */
1401 s->clksrc[0] = value & 0xdb;
1402 /* TODO update clocks */
1403 break;
1404
1405 case 0x070: /* PRCM_CLKOUT_CTRL */
1406 s->clkout[0] = value & 0xbbbb;
1407 /* TODO update clocks */
1408 break;
1409
1410 case 0x078: /* PRCM_CLKEMUL_CTRL */
1411 s->clkemul[0] = value & 1;
1412 /* TODO update clocks */
1413 break;
1414
1415 case 0x080: /* PRCM_CLKCFG_CTRL */
1416 break;
1417
1418 case 0x090: /* PRCM_VOLTSETUP */
1419 s->setuptime[0] = value & 0xffff;
1420 break;
1421 case 0x094: /* PRCM_CLKSSETUP */
1422 s->setuptime[1] = value & 0xffff;
1423 break;
1424
1425 case 0x098: /* PRCM_POLCTRL */
1426 s->clkpol[0] = value & 0x701;
1427 break;
1428
1429 case 0x0b0: /* GENERAL_PURPOSE1 */
1430 case 0x0b4: /* GENERAL_PURPOSE2 */
1431 case 0x0b8: /* GENERAL_PURPOSE3 */
1432 case 0x0bc: /* GENERAL_PURPOSE4 */
1433 case 0x0c0: /* GENERAL_PURPOSE5 */
1434 case 0x0c4: /* GENERAL_PURPOSE6 */
1435 case 0x0c8: /* GENERAL_PURPOSE7 */
1436 case 0x0cc: /* GENERAL_PURPOSE8 */
1437 case 0x0d0: /* GENERAL_PURPOSE9 */
1438 case 0x0d4: /* GENERAL_PURPOSE10 */
1439 case 0x0d8: /* GENERAL_PURPOSE11 */
1440 case 0x0dc: /* GENERAL_PURPOSE12 */
1441 case 0x0e0: /* GENERAL_PURPOSE13 */
1442 case 0x0e4: /* GENERAL_PURPOSE14 */
1443 case 0x0e8: /* GENERAL_PURPOSE15 */
1444 case 0x0ec: /* GENERAL_PURPOSE16 */
1445 case 0x0f0: /* GENERAL_PURPOSE17 */
1446 case 0x0f4: /* GENERAL_PURPOSE18 */
1447 case 0x0f8: /* GENERAL_PURPOSE19 */
1448 case 0x0fc: /* GENERAL_PURPOSE20 */
1449 s->scratch[(addr - 0xb0) >> 2] = value;
1450 break;
1451
1452 case 0x140: /* CM_CLKSEL_MPU */
1453 s->clksel[0] = value & 0x1f;
1454 /* TODO update clocks */
1455 break;
1456 case 0x148: /* CM_CLKSTCTRL_MPU */
1457 s->clkctrl[0] = value & 0x1f;
1458 break;
1459
1460 case 0x158: /* RM_RSTST_MPU */
1461 s->rst[0] &= ~value;
1462 break;
1463 case 0x1c8: /* PM_WKDEP_MPU */
1464 s->wkup[0] = value & 0x15;
1465 break;
1466
1467 case 0x1d4: /* PM_EVGENCTRL_MPU */
1468 s->ev = value & 0x1f;
1469 break;
1470 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1471 s->evtime[0] = value;
1472 break;
1473 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1474 s->evtime[1] = value;
1475 break;
1476
1477 case 0x1e0: /* PM_PWSTCTRL_MPU */
1478 s->power[0] = value & 0xc0f;
1479 break;
1480
1481 case 0x200: /* CM_FCLKEN1_CORE */
1482 s->clken[0] = value & 0xbfffffff;
1483 /* TODO update clocks */
1484 /* The EN_EAC bit only gets/puts func_96m_clk. */
1485 break;
1486 case 0x204: /* CM_FCLKEN2_CORE */
1487 s->clken[1] = value & 0x00000007;
1488 /* TODO update clocks */
1489 break;
1490 case 0x210: /* CM_ICLKEN1_CORE */
1491 s->clken[2] = value & 0xfffffff9;
1492 /* TODO update clocks */
1493 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1494 break;
1495 case 0x214: /* CM_ICLKEN2_CORE */
1496 s->clken[3] = value & 0x00000007;
1497 /* TODO update clocks */
1498 break;
1499 case 0x21c: /* CM_ICLKEN4_CORE */
1500 s->clken[4] = value & 0x0000001f;
1501 /* TODO update clocks */
1502 break;
1503
1504 case 0x230: /* CM_AUTOIDLE1_CORE */
1505 s->clkidle[0] = value & 0xfffffff9;
1506 /* TODO update clocks */
1507 break;
1508 case 0x234: /* CM_AUTOIDLE2_CORE */
1509 s->clkidle[1] = value & 0x00000007;
1510 /* TODO update clocks */
1511 break;
1512 case 0x238: /* CM_AUTOIDLE3_CORE */
1513 s->clkidle[2] = value & 0x00000007;
1514 /* TODO update clocks */
1515 break;
1516 case 0x23c: /* CM_AUTOIDLE4_CORE */
1517 s->clkidle[3] = value & 0x0000001f;
1518 /* TODO update clocks */
1519 break;
1520
1521 case 0x240: /* CM_CLKSEL1_CORE */
1522 s->clksel[1] = value & 0x0fffbf7f;
1523 /* TODO update clocks */
1524 break;
1525
1526 case 0x244: /* CM_CLKSEL2_CORE */
1527 s->clksel[2] = value & 0x00fffffc;
1528 /* TODO update clocks */
1529 break;
1530
1531 case 0x248: /* CM_CLKSTCTRL_CORE */
1532 s->clkctrl[1] = value & 0x7;
1533 break;
1534
1535 case 0x2a0: /* PM_WKEN1_CORE */
1536 s->wken[0] = value & 0x04667ff8;
1537 break;
1538 case 0x2a4: /* PM_WKEN2_CORE */
1539 s->wken[1] = value & 0x00000005;
1540 break;
1541
1542 case 0x2b0: /* PM_WKST1_CORE */
1543 s->wkst[0] &= ~value;
1544 break;
1545 case 0x2b4: /* PM_WKST2_CORE */
1546 s->wkst[1] &= ~value;
1547 break;
1548
1549 case 0x2e0: /* PM_PWSTCTRL_CORE */
1550 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1551 break;
1552
1553 case 0x300: /* CM_FCLKEN_GFX */
1554 s->clken[5] = value & 6;
1555 /* TODO update clocks */
1556 break;
1557 case 0x310: /* CM_ICLKEN_GFX */
1558 s->clken[6] = value & 1;
1559 /* TODO update clocks */
1560 break;
1561 case 0x340: /* CM_CLKSEL_GFX */
1562 s->clksel[3] = value & 7;
1563 /* TODO update clocks */
1564 break;
1565 case 0x348: /* CM_CLKSTCTRL_GFX */
1566 s->clkctrl[2] = value & 1;
1567 break;
1568 case 0x350: /* RM_RSTCTRL_GFX */
1569 s->rstctrl[0] = value & 1;
1570 /* TODO: reset */
1571 break;
1572 case 0x358: /* RM_RSTST_GFX */
1573 s->rst[1] &= ~value;
1574 break;
1575 case 0x3c8: /* PM_WKDEP_GFX */
1576 s->wkup[1] = value & 0x13;
1577 break;
1578 case 0x3e0: /* PM_PWSTCTRL_GFX */
1579 s->power[2] = (value & 0x00c0f) | (3 << 2);
1580 break;
1581
1582 case 0x400: /* CM_FCLKEN_WKUP */
1583 s->clken[7] = value & 0xd;
1584 /* TODO update clocks */
1585 break;
1586 case 0x410: /* CM_ICLKEN_WKUP */
1587 s->clken[8] = value & 0x3f;
1588 /* TODO update clocks */
1589 break;
1590 case 0x430: /* CM_AUTOIDLE_WKUP */
1591 s->clkidle[4] = value & 0x0000003f;
1592 /* TODO update clocks */
1593 break;
1594 case 0x440: /* CM_CLKSEL_WKUP */
1595 s->clksel[4] = value & 3;
1596 /* TODO update clocks */
1597 break;
1598 case 0x450: /* RM_RSTCTRL_WKUP */
1599 /* TODO: reset */
1600 if (value & 2)
1601 qemu_system_reset_request();
1602 break;
1603 case 0x454: /* RM_RSTTIME_WKUP */
1604 s->rsttime_wkup = value & 0x1fff;
1605 break;
1606 case 0x458: /* RM_RSTST_WKUP */
1607 s->rst[2] &= ~value;
1608 break;
1609 case 0x4a0: /* PM_WKEN_WKUP */
1610 s->wken[2] = value & 0x00000005;
1611 break;
1612 case 0x4b0: /* PM_WKST_WKUP */
1613 s->wkst[2] &= ~value;
1614 break;
1615
1616 case 0x500: /* CM_CLKEN_PLL */
1617 if (value & 0xffffff30)
1618 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1619 "future compatibility\n", __FUNCTION__);
1620 if ((s->clken[9] ^ value) & 0xcc) {
1621 s->clken[9] &= ~0xcc;
1622 s->clken[9] |= value & 0xcc;
1623 omap_prcm_apll_update(s);
1624 }
1625 if ((s->clken[9] ^ value) & 3) {
1626 s->clken[9] &= ~3;
1627 s->clken[9] |= value & 3;
1628 omap_prcm_dpll_update(s);
1629 }
1630 break;
1631 case 0x530: /* CM_AUTOIDLE_PLL */
1632 s->clkidle[5] = value & 0x000000cf;
1633 /* TODO update clocks */
1634 break;
1635 case 0x540: /* CM_CLKSEL1_PLL */
1636 if (value & 0xfc4000d7)
1637 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1638 "future compatibility\n", __FUNCTION__);
1639 if ((s->clksel[5] ^ value) & 0x003fff00) {
1640 s->clksel[5] = value & 0x03bfff28;
1641 omap_prcm_dpll_update(s);
1642 }
1643 /* TODO update the other clocks */
1644
1645 s->clksel[5] = value & 0x03bfff28;
1646 break;
1647 case 0x544: /* CM_CLKSEL2_PLL */
1648 if (value & ~3)
1649 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1650 "future compatibility\n", __FUNCTION__);
1651 if (s->clksel[6] != (value & 3)) {
1652 s->clksel[6] = value & 3;
1653 omap_prcm_dpll_update(s);
1654 }
1655 break;
1656
1657 case 0x800: /* CM_FCLKEN_DSP */
1658 s->clken[10] = value & 0x501;
1659 /* TODO update clocks */
1660 break;
1661 case 0x810: /* CM_ICLKEN_DSP */
1662 s->clken[11] = value & 0x2;
1663 /* TODO update clocks */
1664 break;
1665 case 0x830: /* CM_AUTOIDLE_DSP */
1666 s->clkidle[6] = value & 0x2;
1667 /* TODO update clocks */
1668 break;
1669 case 0x840: /* CM_CLKSEL_DSP */
1670 s->clksel[7] = value & 0x3fff;
1671 /* TODO update clocks */
1672 break;
1673 case 0x848: /* CM_CLKSTCTRL_DSP */
1674 s->clkctrl[3] = value & 0x101;
1675 break;
1676 case 0x850: /* RM_RSTCTRL_DSP */
1677 /* TODO: reset */
1678 break;
1679 case 0x858: /* RM_RSTST_DSP */
1680 s->rst[3] &= ~value;
1681 break;
1682 case 0x8c8: /* PM_WKDEP_DSP */
1683 s->wkup[2] = value & 0x13;
1684 break;
1685 case 0x8e0: /* PM_PWSTCTRL_DSP */
1686 s->power[3] = (value & 0x03017) | (3 << 2);
1687 break;
1688
1689 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1690 s->irqst[1] &= ~value;
1691 omap_prcm_int_update(s, 1);
1692 break;
1693 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1694 s->irqen[1] = value & 0x7;
1695 omap_prcm_int_update(s, 1);
1696 break;
1697
1698 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1699 s->irqst[2] &= ~value;
1700 omap_prcm_int_update(s, 2);
1701 break;
1702 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1703 s->irqen[2] = value & 0x7;
1704 omap_prcm_int_update(s, 2);
1705 break;
1706
1707 default:
1708 OMAP_BAD_REG(addr);
1709 return;
1710 }
1711 }
1712
1713 static const MemoryRegionOps omap_prcm_ops = {
1714 .read = omap_prcm_read,
1715 .write = omap_prcm_write,
1716 .endianness = DEVICE_NATIVE_ENDIAN,
1717 };
1718
1719 static void omap_prcm_reset(struct omap_prcm_s *s)
1720 {
1721 s->sysconfig = 0;
1722 s->irqst[0] = 0;
1723 s->irqst[1] = 0;
1724 s->irqst[2] = 0;
1725 s->irqen[0] = 0;
1726 s->irqen[1] = 0;
1727 s->irqen[2] = 0;
1728 s->voltctrl = 0x1040;
1729 s->ev = 0x14;
1730 s->evtime[0] = 0;
1731 s->evtime[1] = 0;
1732 s->clkctrl[0] = 0;
1733 s->clkctrl[1] = 0;
1734 s->clkctrl[2] = 0;
1735 s->clkctrl[3] = 0;
1736 s->clken[1] = 7;
1737 s->clken[3] = 7;
1738 s->clken[4] = 0;
1739 s->clken[5] = 0;
1740 s->clken[6] = 0;
1741 s->clken[7] = 0xc;
1742 s->clken[8] = 0x3e;
1743 s->clken[9] = 0x0d;
1744 s->clken[10] = 0;
1745 s->clken[11] = 0;
1746 s->clkidle[0] = 0;
1747 s->clkidle[2] = 7;
1748 s->clkidle[3] = 0;
1749 s->clkidle[4] = 0;
1750 s->clkidle[5] = 0x0c;
1751 s->clkidle[6] = 0;
1752 s->clksel[0] = 0x01;
1753 s->clksel[1] = 0x02100121;
1754 s->clksel[2] = 0x00000000;
1755 s->clksel[3] = 0x01;
1756 s->clksel[4] = 0;
1757 s->clksel[7] = 0x0121;
1758 s->wkup[0] = 0x15;
1759 s->wkup[1] = 0x13;
1760 s->wkup[2] = 0x13;
1761 s->wken[0] = 0x04667ff8;
1762 s->wken[1] = 0x00000005;
1763 s->wken[2] = 5;
1764 s->wkst[0] = 0;
1765 s->wkst[1] = 0;
1766 s->wkst[2] = 0;
1767 s->power[0] = 0x00c;
1768 s->power[1] = 4;
1769 s->power[2] = 0x0000c;
1770 s->power[3] = 0x14;
1771 s->rstctrl[0] = 1;
1772 s->rst[3] = 1;
1773 omap_prcm_apll_update(s);
1774 omap_prcm_dpll_update(s);
1775 }
1776
1777 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1778 {
1779 s->setuptime[0] = 0;
1780 s->setuptime[1] = 0;
1781 memset(&s->scratch, 0, sizeof(s->scratch));
1782 s->rst[0] = 0x01;
1783 s->rst[1] = 0x00;
1784 s->rst[2] = 0x01;
1785 s->clken[0] = 0;
1786 s->clken[2] = 0;
1787 s->clkidle[1] = 0;
1788 s->clksel[5] = 0;
1789 s->clksel[6] = 2;
1790 s->clksrc[0] = 0x43;
1791 s->clkout[0] = 0x0303;
1792 s->clkemul[0] = 0;
1793 s->clkpol[0] = 0x100;
1794 s->rsttime_wkup = 0x1002;
1795
1796 omap_prcm_reset(s);
1797 }
1798
1799 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1800 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1801 struct omap_mpu_state_s *mpu)
1802 {
1803 struct omap_prcm_s *s = (struct omap_prcm_s *)
1804 g_malloc0(sizeof(struct omap_prcm_s));
1805
1806 s->irq[0] = mpu_int;
1807 s->irq[1] = dsp_int;
1808 s->irq[2] = iva_int;
1809 s->mpu = mpu;
1810 omap_prcm_coldreset(s);
1811
1812 memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
1813 omap_l4_region_size(ta, 0));
1814 memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
1815 omap_l4_region_size(ta, 1));
1816 omap_l4_attach(ta, 0, &s->iomem0);
1817 omap_l4_attach(ta, 1, &s->iomem1);
1818
1819 return s;
1820 }
1821
1822 /* System and Pinout control */
1823 struct omap_sysctl_s {
1824 struct omap_mpu_state_s *mpu;
1825 MemoryRegion iomem;
1826
1827 uint32_t sysconfig;
1828 uint32_t devconfig;
1829 uint32_t psaconfig;
1830 uint32_t padconf[0x45];
1831 uint8_t obs;
1832 uint32_t msuspendmux[5];
1833 };
1834
1835 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
1836 {
1837
1838 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1839 int pad_offset, byte_offset;
1840 int value;
1841
1842 switch (addr) {
1843 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1844 pad_offset = (addr - 0x30) >> 2;
1845 byte_offset = (addr - 0x30) & (4 - 1);
1846
1847 value = s->padconf[pad_offset];
1848 value = (value >> (byte_offset * 8)) & 0xff;
1849
1850 return value;
1851
1852 default:
1853 break;
1854 }
1855
1856 OMAP_BAD_REG(addr);
1857 return 0;
1858 }
1859
1860 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
1861 {
1862 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1863
1864 switch (addr) {
1865 case 0x000: /* CONTROL_REVISION */
1866 return 0x20;
1867
1868 case 0x010: /* CONTROL_SYSCONFIG */
1869 return s->sysconfig;
1870
1871 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1872 return s->padconf[(addr - 0x30) >> 2];
1873
1874 case 0x270: /* CONTROL_DEBOBS */
1875 return s->obs;
1876
1877 case 0x274: /* CONTROL_DEVCONF */
1878 return s->devconfig;
1879
1880 case 0x28c: /* CONTROL_EMU_SUPPORT */
1881 return 0;
1882
1883 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1884 return s->msuspendmux[0];
1885 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1886 return s->msuspendmux[1];
1887 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1888 return s->msuspendmux[2];
1889 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1890 return s->msuspendmux[3];
1891 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1892 return s->msuspendmux[4];
1893 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1894 return 0;
1895
1896 case 0x2b8: /* CONTROL_PSA_CTRL */
1897 return s->psaconfig;
1898 case 0x2bc: /* CONTROL_PSA_CMD */
1899 case 0x2c0: /* CONTROL_PSA_VALUE */
1900 return 0;
1901
1902 case 0x2b0: /* CONTROL_SEC_CTRL */
1903 return 0x800000f1;
1904 case 0x2d0: /* CONTROL_SEC_EMU */
1905 return 0x80000015;
1906 case 0x2d4: /* CONTROL_SEC_TAP */
1907 return 0x8000007f;
1908 case 0x2b4: /* CONTROL_SEC_TEST */
1909 case 0x2f0: /* CONTROL_SEC_STATUS */
1910 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1911 /* Secure mode is not present on general-pusrpose device. Outside
1912 * secure mode these values cannot be read or written. */
1913 return 0;
1914
1915 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1916 return 0xff;
1917 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1918 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1919 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1920 /* No secure mode so no Extended Secure RAM present. */
1921 return 0;
1922
1923 case 0x2f8: /* CONTROL_STATUS */
1924 /* Device Type => General-purpose */
1925 return 0x0300;
1926 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1927
1928 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1929 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1930 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1931 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1932 return 0xdecafbad;
1933
1934 case 0x310: /* CONTROL_RAND_KEY_0 */
1935 case 0x314: /* CONTROL_RAND_KEY_1 */
1936 case 0x318: /* CONTROL_RAND_KEY_2 */
1937 case 0x31c: /* CONTROL_RAND_KEY_3 */
1938 case 0x320: /* CONTROL_CUST_KEY_0 */
1939 case 0x324: /* CONTROL_CUST_KEY_1 */
1940 case 0x330: /* CONTROL_TEST_KEY_0 */
1941 case 0x334: /* CONTROL_TEST_KEY_1 */
1942 case 0x338: /* CONTROL_TEST_KEY_2 */
1943 case 0x33c: /* CONTROL_TEST_KEY_3 */
1944 case 0x340: /* CONTROL_TEST_KEY_4 */
1945 case 0x344: /* CONTROL_TEST_KEY_5 */
1946 case 0x348: /* CONTROL_TEST_KEY_6 */
1947 case 0x34c: /* CONTROL_TEST_KEY_7 */
1948 case 0x350: /* CONTROL_TEST_KEY_8 */
1949 case 0x354: /* CONTROL_TEST_KEY_9 */
1950 /* Can only be accessed in secure mode and when C_FieldAccEnable
1951 * bit is set in CONTROL_SEC_CTRL.
1952 * TODO: otherwise an interconnect access error is generated. */
1953 return 0;
1954 }
1955
1956 OMAP_BAD_REG(addr);
1957 return 0;
1958 }
1959
1960 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
1961 uint32_t value)
1962 {
1963 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1964 int pad_offset, byte_offset;
1965 int prev_value;
1966
1967 switch (addr) {
1968 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1969 pad_offset = (addr - 0x30) >> 2;
1970 byte_offset = (addr - 0x30) & (4 - 1);
1971
1972 prev_value = s->padconf[pad_offset];
1973 prev_value &= ~(0xff << (byte_offset * 8));
1974 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1975 s->padconf[pad_offset] = prev_value;
1976 break;
1977
1978 default:
1979 OMAP_BAD_REG(addr);
1980 break;
1981 }
1982 }
1983
1984 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
1985 uint32_t value)
1986 {
1987 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1988
1989 switch (addr) {
1990 case 0x000: /* CONTROL_REVISION */
1991 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1992 case 0x2c0: /* CONTROL_PSA_VALUE */
1993 case 0x2f8: /* CONTROL_STATUS */
1994 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1995 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1996 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1997 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1998 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1999 case 0x310: /* CONTROL_RAND_KEY_0 */
2000 case 0x314: /* CONTROL_RAND_KEY_1 */
2001 case 0x318: /* CONTROL_RAND_KEY_2 */
2002 case 0x31c: /* CONTROL_RAND_KEY_3 */
2003 case 0x320: /* CONTROL_CUST_KEY_0 */
2004 case 0x324: /* CONTROL_CUST_KEY_1 */
2005 case 0x330: /* CONTROL_TEST_KEY_0 */
2006 case 0x334: /* CONTROL_TEST_KEY_1 */
2007 case 0x338: /* CONTROL_TEST_KEY_2 */
2008 case 0x33c: /* CONTROL_TEST_KEY_3 */
2009 case 0x340: /* CONTROL_TEST_KEY_4 */
2010 case 0x344: /* CONTROL_TEST_KEY_5 */
2011 case 0x348: /* CONTROL_TEST_KEY_6 */
2012 case 0x34c: /* CONTROL_TEST_KEY_7 */
2013 case 0x350: /* CONTROL_TEST_KEY_8 */
2014 case 0x354: /* CONTROL_TEST_KEY_9 */
2015 OMAP_RO_REG(addr);
2016 return;
2017
2018 case 0x010: /* CONTROL_SYSCONFIG */
2019 s->sysconfig = value & 0x1e;
2020 break;
2021
2022 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2023 /* XXX: should check constant bits */
2024 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2025 break;
2026
2027 case 0x270: /* CONTROL_DEBOBS */
2028 s->obs = value & 0xff;
2029 break;
2030
2031 case 0x274: /* CONTROL_DEVCONF */
2032 s->devconfig = value & 0xffffc7ff;
2033 break;
2034
2035 case 0x28c: /* CONTROL_EMU_SUPPORT */
2036 break;
2037
2038 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2039 s->msuspendmux[0] = value & 0x3fffffff;
2040 break;
2041 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2042 s->msuspendmux[1] = value & 0x3fffffff;
2043 break;
2044 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2045 s->msuspendmux[2] = value & 0x3fffffff;
2046 break;
2047 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2048 s->msuspendmux[3] = value & 0x3fffffff;
2049 break;
2050 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2051 s->msuspendmux[4] = value & 0x3fffffff;
2052 break;
2053
2054 case 0x2b8: /* CONTROL_PSA_CTRL */
2055 s->psaconfig = value & 0x1c;
2056 s->psaconfig |= (value & 0x20) ? 2 : 1;
2057 break;
2058 case 0x2bc: /* CONTROL_PSA_CMD */
2059 break;
2060
2061 case 0x2b0: /* CONTROL_SEC_CTRL */
2062 case 0x2b4: /* CONTROL_SEC_TEST */
2063 case 0x2d0: /* CONTROL_SEC_EMU */
2064 case 0x2d4: /* CONTROL_SEC_TAP */
2065 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2066 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2067 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2068 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2069 case 0x2f0: /* CONTROL_SEC_STATUS */
2070 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2071 break;
2072
2073 default:
2074 OMAP_BAD_REG(addr);
2075 return;
2076 }
2077 }
2078
2079 static const MemoryRegionOps omap_sysctl_ops = {
2080 .old_mmio = {
2081 .read = {
2082 omap_sysctl_read8,
2083 omap_badwidth_read32, /* TODO */
2084 omap_sysctl_read,
2085 },
2086 .write = {
2087 omap_sysctl_write8,
2088 omap_badwidth_write32, /* TODO */
2089 omap_sysctl_write,
2090 },
2091 },
2092 .endianness = DEVICE_NATIVE_ENDIAN,
2093 };
2094
2095 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2096 {
2097 /* (power-on reset) */
2098 s->sysconfig = 0;
2099 s->obs = 0;
2100 s->devconfig = 0x0c000000;
2101 s->msuspendmux[0] = 0x00000000;
2102 s->msuspendmux[1] = 0x00000000;
2103 s->msuspendmux[2] = 0x00000000;
2104 s->msuspendmux[3] = 0x00000000;
2105 s->msuspendmux[4] = 0x00000000;
2106 s->psaconfig = 1;
2107
2108 s->padconf[0x00] = 0x000f0f0f;
2109 s->padconf[0x01] = 0x00000000;
2110 s->padconf[0x02] = 0x00000000;
2111 s->padconf[0x03] = 0x00000000;
2112 s->padconf[0x04] = 0x00000000;
2113 s->padconf[0x05] = 0x00000000;
2114 s->padconf[0x06] = 0x00000000;
2115 s->padconf[0x07] = 0x00000000;
2116 s->padconf[0x08] = 0x08080800;
2117 s->padconf[0x09] = 0x08080808;
2118 s->padconf[0x0a] = 0x08080808;
2119 s->padconf[0x0b] = 0x08080808;
2120 s->padconf[0x0c] = 0x08080808;
2121 s->padconf[0x0d] = 0x08080800;
2122 s->padconf[0x0e] = 0x08080808;
2123 s->padconf[0x0f] = 0x08080808;
2124 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2125 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2126 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2127 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2128 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2129 s->padconf[0x15] = 0x18181818;
2130 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2131 s->padconf[0x17] = 0x1f001f00;
2132 s->padconf[0x18] = 0x1f1f1f1f;
2133 s->padconf[0x19] = 0x00000000;
2134 s->padconf[0x1a] = 0x1f180000;
2135 s->padconf[0x1b] = 0x00001f1f;
2136 s->padconf[0x1c] = 0x1f001f00;
2137 s->padconf[0x1d] = 0x00000000;
2138 s->padconf[0x1e] = 0x00000000;
2139 s->padconf[0x1f] = 0x08000000;
2140 s->padconf[0x20] = 0x08080808;
2141 s->padconf[0x21] = 0x08080808;
2142 s->padconf[0x22] = 0x0f080808;
2143 s->padconf[0x23] = 0x0f0f0f0f;
2144 s->padconf[0x24] = 0x000f0f0f;
2145 s->padconf[0x25] = 0x1f1f1f0f;
2146 s->padconf[0x26] = 0x080f0f1f;
2147 s->padconf[0x27] = 0x070f1808;
2148 s->padconf[0x28] = 0x0f070707;
2149 s->padconf[0x29] = 0x000f0f1f;
2150 s->padconf[0x2a] = 0x0f0f0f1f;
2151 s->padconf[0x2b] = 0x08000000;
2152 s->padconf[0x2c] = 0x0000001f;
2153 s->padconf[0x2d] = 0x0f0f1f00;
2154 s->padconf[0x2e] = 0x1f1f0f0f;
2155 s->padconf[0x2f] = 0x0f1f1f1f;
2156 s->padconf[0x30] = 0x0f0f0f0f;
2157 s->padconf[0x31] = 0x0f1f0f1f;
2158 s->padconf[0x32] = 0x0f0f0f0f;
2159 s->padconf[0x33] = 0x0f1f0f1f;
2160 s->padconf[0x34] = 0x1f1f0f0f;
2161 s->padconf[0x35] = 0x0f0f1f1f;
2162 s->padconf[0x36] = 0x0f0f1f0f;
2163 s->padconf[0x37] = 0x0f0f0f0f;
2164 s->padconf[0x38] = 0x1f18180f;
2165 s->padconf[0x39] = 0x1f1f1f1f;
2166 s->padconf[0x3a] = 0x00001f1f;
2167 s->padconf[0x3b] = 0x00000000;
2168 s->padconf[0x3c] = 0x00000000;
2169 s->padconf[0x3d] = 0x0f0f0f0f;
2170 s->padconf[0x3e] = 0x18000f0f;
2171 s->padconf[0x3f] = 0x00070000;
2172 s->padconf[0x40] = 0x00000707;
2173 s->padconf[0x41] = 0x0f1f0700;
2174 s->padconf[0x42] = 0x1f1f070f;
2175 s->padconf[0x43] = 0x0008081f;
2176 s->padconf[0x44] = 0x00000800;
2177 }
2178
2179 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2180 omap_clk iclk, struct omap_mpu_state_s *mpu)
2181 {
2182 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
2183 g_malloc0(sizeof(struct omap_sysctl_s));
2184
2185 s->mpu = mpu;
2186 omap_sysctl_reset(s);
2187
2188 memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
2189 omap_l4_region_size(ta, 0));
2190 omap_l4_attach(ta, 0, &s->iomem);
2191
2192 return s;
2193 }
2194
2195 /* General chip reset */
2196 static void omap2_mpu_reset(void *opaque)
2197 {
2198 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2199
2200 omap_dma_reset(mpu->dma);
2201 omap_prcm_reset(mpu->prcm);
2202 omap_sysctl_reset(mpu->sysc);
2203 omap_gp_timer_reset(mpu->gptimer[0]);
2204 omap_gp_timer_reset(mpu->gptimer[1]);
2205 omap_gp_timer_reset(mpu->gptimer[2]);
2206 omap_gp_timer_reset(mpu->gptimer[3]);
2207 omap_gp_timer_reset(mpu->gptimer[4]);
2208 omap_gp_timer_reset(mpu->gptimer[5]);
2209 omap_gp_timer_reset(mpu->gptimer[6]);
2210 omap_gp_timer_reset(mpu->gptimer[7]);
2211 omap_gp_timer_reset(mpu->gptimer[8]);
2212 omap_gp_timer_reset(mpu->gptimer[9]);
2213 omap_gp_timer_reset(mpu->gptimer[10]);
2214 omap_gp_timer_reset(mpu->gptimer[11]);
2215 omap_synctimer_reset(mpu->synctimer);
2216 omap_sdrc_reset(mpu->sdrc);
2217 omap_gpmc_reset(mpu->gpmc);
2218 omap_dss_reset(mpu->dss);
2219 omap_uart_reset(mpu->uart[0]);
2220 omap_uart_reset(mpu->uart[1]);
2221 omap_uart_reset(mpu->uart[2]);
2222 omap_mmc_reset(mpu->mmc);
2223 omap_mcspi_reset(mpu->mcspi[0]);
2224 omap_mcspi_reset(mpu->mcspi[1]);
2225 omap_i2c_reset(mpu->i2c[0]);
2226 omap_i2c_reset(mpu->i2c[1]);
2227 cpu_state_reset(mpu->env);
2228 }
2229
2230 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2231 target_phys_addr_t addr)
2232 {
2233 return 1;
2234 }
2235
2236 static const struct dma_irq_map omap2_dma_irq_map[] = {
2237 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2238 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2239 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2240 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2241 };
2242
2243 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
2244 unsigned long sdram_size,
2245 const char *core)
2246 {
2247 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
2248 g_malloc0(sizeof(struct omap_mpu_state_s));
2249 qemu_irq *cpu_irq;
2250 qemu_irq dma_irqs[4];
2251 DriveInfo *dinfo;
2252 int i;
2253 SysBusDevice *busdev;
2254 struct omap_target_agent_s *ta;
2255
2256 /* Core */
2257 s->mpu_model = omap2420;
2258 s->env = cpu_init(core ?: "arm1136-r2");
2259 if (!s->env) {
2260 fprintf(stderr, "Unable to find CPU definition\n");
2261 exit(1);
2262 }
2263 s->sdram_size = sdram_size;
2264 s->sram_size = OMAP242X_SRAM_SIZE;
2265
2266 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
2267
2268 /* Clocks */
2269 omap_clk_init(s);
2270
2271 /* Memory-mapped stuff */
2272 memory_region_init_ram(&s->sdram, "omap2.dram", s->sdram_size);
2273 vmstate_register_ram_global(&s->sdram);
2274 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
2275 memory_region_init_ram(&s->sram, "omap2.sram", s->sram_size);
2276 vmstate_register_ram_global(&s->sram);
2277 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2278
2279 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2280
2281 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2282 cpu_irq = arm_pic_init_cpu(s->env);
2283 s->ih[0] = qdev_create(NULL, "omap2-intc");
2284 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2285 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
2286 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
2287 qdev_init_nofail(s->ih[0]);
2288 busdev = sysbus_from_qdev(s->ih[0]);
2289 sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
2290 sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
2291 sysbus_mmio_map(busdev, 0, 0x480fe000);
2292 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2293 qdev_get_gpio_in(s->ih[0],
2294 OMAP_INT_24XX_PRCM_MPU_IRQ),
2295 NULL, NULL, s);
2296
2297 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2298 omap_findclk(s, "omapctrl_iclk"), s);
2299
2300 for (i = 0; i < 4; i++) {
2301 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2302 omap2_dma_irq_map[i].intr);
2303 }
2304 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2305 omap_findclk(s, "sdma_iclk"),
2306 omap_findclk(s, "sdma_fclk"));
2307 s->port->addr_valid = omap2_validate_addr;
2308
2309 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2310 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
2311 OMAP2_Q2_BASE, s->sdram_size);
2312 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2313 OMAP2_SRAM_BASE, s->sram_size);
2314
2315 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2316 qdev_get_gpio_in(s->ih[0],
2317 OMAP_INT_24XX_UART1_IRQ),
2318 omap_findclk(s, "uart1_fclk"),
2319 omap_findclk(s, "uart1_iclk"),
2320 s->drq[OMAP24XX_DMA_UART1_TX],
2321 s->drq[OMAP24XX_DMA_UART1_RX],
2322 "uart1",
2323 serial_hds[0]);
2324 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2325 qdev_get_gpio_in(s->ih[0],
2326 OMAP_INT_24XX_UART2_IRQ),
2327 omap_findclk(s, "uart2_fclk"),
2328 omap_findclk(s, "uart2_iclk"),
2329 s->drq[OMAP24XX_DMA_UART2_TX],
2330 s->drq[OMAP24XX_DMA_UART2_RX],
2331 "uart2",
2332 serial_hds[0] ? serial_hds[1] : NULL);
2333 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2334 qdev_get_gpio_in(s->ih[0],
2335 OMAP_INT_24XX_UART3_IRQ),
2336 omap_findclk(s, "uart3_fclk"),
2337 omap_findclk(s, "uart3_iclk"),
2338 s->drq[OMAP24XX_DMA_UART3_TX],
2339 s->drq[OMAP24XX_DMA_UART3_RX],
2340 "uart3",
2341 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
2342
2343 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2344 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2345 omap_findclk(s, "wu_gpt1_clk"),
2346 omap_findclk(s, "wu_l4_iclk"));
2347 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2348 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2349 omap_findclk(s, "core_gpt2_clk"),
2350 omap_findclk(s, "core_l4_iclk"));
2351 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2352 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2353 omap_findclk(s, "core_gpt3_clk"),
2354 omap_findclk(s, "core_l4_iclk"));
2355 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2356 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2357 omap_findclk(s, "core_gpt4_clk"),
2358 omap_findclk(s, "core_l4_iclk"));
2359 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2360 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2361 omap_findclk(s, "core_gpt5_clk"),
2362 omap_findclk(s, "core_l4_iclk"));
2363 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2364 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2365 omap_findclk(s, "core_gpt6_clk"),
2366 omap_findclk(s, "core_l4_iclk"));
2367 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2368 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2369 omap_findclk(s, "core_gpt7_clk"),
2370 omap_findclk(s, "core_l4_iclk"));
2371 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2372 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2373 omap_findclk(s, "core_gpt8_clk"),
2374 omap_findclk(s, "core_l4_iclk"));
2375 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2376 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2377 omap_findclk(s, "core_gpt9_clk"),
2378 omap_findclk(s, "core_l4_iclk"));
2379 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2380 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2381 omap_findclk(s, "core_gpt10_clk"),
2382 omap_findclk(s, "core_l4_iclk"));
2383 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2384 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2385 omap_findclk(s, "core_gpt11_clk"),
2386 omap_findclk(s, "core_l4_iclk"));
2387 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2388 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2389 omap_findclk(s, "core_gpt12_clk"),
2390 omap_findclk(s, "core_l4_iclk"));
2391
2392 omap_tap_init(omap_l4ta(s->l4, 2), s);
2393
2394 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2395 omap_findclk(s, "clk32-kHz"),
2396 omap_findclk(s, "core_l4_iclk"));
2397
2398 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
2399 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ),
2400 &s->drq[OMAP24XX_DMA_I2C1_TX],
2401 omap_findclk(s, "i2c1.fclk"),
2402 omap_findclk(s, "i2c1.iclk"));
2403 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
2404 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ),
2405 &s->drq[OMAP24XX_DMA_I2C2_TX],
2406 omap_findclk(s, "i2c2.fclk"),
2407 omap_findclk(s, "i2c2.iclk"));
2408
2409 s->gpio = qdev_create(NULL, "omap2-gpio");
2410 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2411 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2412 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2413 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2414 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2415 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2416 if (s->mpu_model == omap2430) {
2417 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2418 }
2419 qdev_init_nofail(s->gpio);
2420 busdev = sysbus_from_qdev(s->gpio);
2421 sysbus_connect_irq(busdev, 0,
2422 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2423 sysbus_connect_irq(busdev, 3,
2424 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2425 sysbus_connect_irq(busdev, 6,
2426 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2427 sysbus_connect_irq(busdev, 9,
2428 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2429 if (s->mpu_model == omap2430) {
2430 sysbus_connect_irq(busdev, 12,
2431 qdev_get_gpio_in(s->ih[0],
2432 OMAP_INT_243X_GPIO_BANK5));
2433 }
2434 ta = omap_l4ta(s->l4, 3);
2435 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2436 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2437 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2438 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2439 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2440
2441 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2442 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2443 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2444 s->drq[OMAP24XX_DMA_GPMC]);
2445
2446 dinfo = drive_get(IF_SD, 0, 0);
2447 if (!dinfo) {
2448 fprintf(stderr, "qemu: missing SecureDigital device\n");
2449 exit(1);
2450 }
2451 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
2452 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2453 &s->drq[OMAP24XX_DMA_MMC1_TX],
2454 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2455
2456 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2457 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2458 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2459 omap_findclk(s, "spi1_fclk"),
2460 omap_findclk(s, "spi1_iclk"));
2461 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2462 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2463 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2464 omap_findclk(s, "spi2_fclk"),
2465 omap_findclk(s, "spi2_iclk"));
2466
2467 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2468 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2469 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2470 s->drq[OMAP24XX_DMA_DSS],
2471 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2472 omap_findclk(s, "dss_54m_clk"),
2473 omap_findclk(s, "dss_l3_iclk"),
2474 omap_findclk(s, "dss_l4_iclk"));
2475
2476 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2477 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2478 omap_findclk(s, "emul_ck"),
2479 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
2480 serial_hds[3] : NULL);
2481
2482 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2483 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2484 /* Ten consecutive lines */
2485 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2486 omap_findclk(s, "func_96m_clk"),
2487 omap_findclk(s, "core_l4_iclk"));
2488
2489 /* All register mappings (includin those not currenlty implemented):
2490 * SystemControlMod 48000000 - 48000fff
2491 * SystemControlL4 48001000 - 48001fff
2492 * 32kHz Timer Mod 48004000 - 48004fff
2493 * 32kHz Timer L4 48005000 - 48005fff
2494 * PRCM ModA 48008000 - 480087ff
2495 * PRCM ModB 48008800 - 48008fff
2496 * PRCM L4 48009000 - 48009fff
2497 * TEST-BCM Mod 48012000 - 48012fff
2498 * TEST-BCM L4 48013000 - 48013fff
2499 * TEST-TAP Mod 48014000 - 48014fff
2500 * TEST-TAP L4 48015000 - 48015fff
2501 * GPIO1 Mod 48018000 - 48018fff
2502 * GPIO Top 48019000 - 48019fff
2503 * GPIO2 Mod 4801a000 - 4801afff
2504 * GPIO L4 4801b000 - 4801bfff
2505 * GPIO3 Mod 4801c000 - 4801cfff
2506 * GPIO4 Mod 4801e000 - 4801efff
2507 * WDTIMER1 Mod 48020000 - 48010fff
2508 * WDTIMER Top 48021000 - 48011fff
2509 * WDTIMER2 Mod 48022000 - 48012fff
2510 * WDTIMER L4 48023000 - 48013fff
2511 * WDTIMER3 Mod 48024000 - 48014fff
2512 * WDTIMER3 L4 48025000 - 48015fff
2513 * WDTIMER4 Mod 48026000 - 48016fff
2514 * WDTIMER4 L4 48027000 - 48017fff
2515 * GPTIMER1 Mod 48028000 - 48018fff
2516 * GPTIMER1 L4 48029000 - 48019fff
2517 * GPTIMER2 Mod 4802a000 - 4801afff
2518 * GPTIMER2 L4 4802b000 - 4801bfff
2519 * L4-Config AP 48040000 - 480407ff
2520 * L4-Config IP 48040800 - 48040fff
2521 * L4-Config LA 48041000 - 48041fff
2522 * ARM11ETB Mod 48048000 - 48049fff
2523 * ARM11ETB L4 4804a000 - 4804afff
2524 * DISPLAY Top 48050000 - 480503ff
2525 * DISPLAY DISPC 48050400 - 480507ff
2526 * DISPLAY RFBI 48050800 - 48050bff
2527 * DISPLAY VENC 48050c00 - 48050fff
2528 * DISPLAY L4 48051000 - 48051fff
2529 * CAMERA Top 48052000 - 480523ff
2530 * CAMERA core 48052400 - 480527ff
2531 * CAMERA DMA 48052800 - 48052bff
2532 * CAMERA MMU 48052c00 - 48052fff
2533 * CAMERA L4 48053000 - 48053fff
2534 * SDMA Mod 48056000 - 48056fff
2535 * SDMA L4 48057000 - 48057fff
2536 * SSI Top 48058000 - 48058fff
2537 * SSI GDD 48059000 - 48059fff
2538 * SSI Port1 4805a000 - 4805afff
2539 * SSI Port2 4805b000 - 4805bfff
2540 * SSI L4 4805c000 - 4805cfff
2541 * USB Mod 4805e000 - 480fefff
2542 * USB L4 4805f000 - 480fffff
2543 * WIN_TRACER1 Mod 48060000 - 48060fff
2544 * WIN_TRACER1 L4 48061000 - 48061fff
2545 * WIN_TRACER2 Mod 48062000 - 48062fff
2546 * WIN_TRACER2 L4 48063000 - 48063fff
2547 * WIN_TRACER3 Mod 48064000 - 48064fff
2548 * WIN_TRACER3 L4 48065000 - 48065fff
2549 * WIN_TRACER4 Top 48066000 - 480660ff
2550 * WIN_TRACER4 ETT 48066100 - 480661ff
2551 * WIN_TRACER4 WT 48066200 - 480662ff
2552 * WIN_TRACER4 L4 48067000 - 48067fff
2553 * XTI Mod 48068000 - 48068fff
2554 * XTI L4 48069000 - 48069fff
2555 * UART1 Mod 4806a000 - 4806afff
2556 * UART1 L4 4806b000 - 4806bfff
2557 * UART2 Mod 4806c000 - 4806cfff
2558 * UART2 L4 4806d000 - 4806dfff
2559 * UART3 Mod 4806e000 - 4806efff
2560 * UART3 L4 4806f000 - 4806ffff
2561 * I2C1 Mod 48070000 - 48070fff
2562 * I2C1 L4 48071000 - 48071fff
2563 * I2C2 Mod 48072000 - 48072fff
2564 * I2C2 L4 48073000 - 48073fff
2565 * McBSP1 Mod 48074000 - 48074fff
2566 * McBSP1 L4 48075000 - 48075fff
2567 * McBSP2 Mod 48076000 - 48076fff
2568 * McBSP2 L4 48077000 - 48077fff
2569 * GPTIMER3 Mod 48078000 - 48078fff
2570 * GPTIMER3 L4 48079000 - 48079fff
2571 * GPTIMER4 Mod 4807a000 - 4807afff
2572 * GPTIMER4 L4 4807b000 - 4807bfff
2573 * GPTIMER5 Mod 4807c000 - 4807cfff
2574 * GPTIMER5 L4 4807d000 - 4807dfff
2575 * GPTIMER6 Mod 4807e000 - 4807efff
2576 * GPTIMER6 L4 4807f000 - 4807ffff
2577 * GPTIMER7 Mod 48080000 - 48080fff
2578 * GPTIMER7 L4 48081000 - 48081fff
2579 * GPTIMER8 Mod 48082000 - 48082fff
2580 * GPTIMER8 L4 48083000 - 48083fff
2581 * GPTIMER9 Mod 48084000 - 48084fff
2582 * GPTIMER9 L4 48085000 - 48085fff
2583 * GPTIMER10 Mod 48086000 - 48086fff
2584 * GPTIMER10 L4 48087000 - 48087fff
2585 * GPTIMER11 Mod 48088000 - 48088fff
2586 * GPTIMER11 L4 48089000 - 48089fff
2587 * GPTIMER12 Mod 4808a000 - 4808afff
2588 * GPTIMER12 L4 4808b000 - 4808bfff
2589 * EAC Mod 48090000 - 48090fff
2590 * EAC L4 48091000 - 48091fff
2591 * FAC Mod 48092000 - 48092fff
2592 * FAC L4 48093000 - 48093fff
2593 * MAILBOX Mod 48094000 - 48094fff
2594 * MAILBOX L4 48095000 - 48095fff
2595 * SPI1 Mod 48098000 - 48098fff
2596 * SPI1 L4 48099000 - 48099fff
2597 * SPI2 Mod 4809a000 - 4809afff
2598 * SPI2 L4 4809b000 - 4809bfff
2599 * MMC/SDIO Mod 4809c000 - 4809cfff
2600 * MMC/SDIO L4 4809d000 - 4809dfff
2601 * MS_PRO Mod 4809e000 - 4809efff
2602 * MS_PRO L4 4809f000 - 4809ffff
2603 * RNG Mod 480a0000 - 480a0fff
2604 * RNG L4 480a1000 - 480a1fff
2605 * DES3DES Mod 480a2000 - 480a2fff
2606 * DES3DES L4 480a3000 - 480a3fff
2607 * SHA1MD5 Mod 480a4000 - 480a4fff
2608 * SHA1MD5 L4 480a5000 - 480a5fff
2609 * AES Mod 480a6000 - 480a6fff
2610 * AES L4 480a7000 - 480a7fff
2611 * PKA Mod 480a8000 - 480a9fff
2612 * PKA L4 480aa000 - 480aafff
2613 * MG Mod 480b0000 - 480b0fff
2614 * MG L4 480b1000 - 480b1fff
2615 * HDQ/1-wire Mod 480b2000 - 480b2fff
2616 * HDQ/1-wire L4 480b3000 - 480b3fff
2617 * MPU interrupt 480fe000 - 480fefff
2618 * STI channel base 54000000 - 5400ffff
2619 * IVA RAM 5c000000 - 5c01ffff
2620 * IVA ROM 5c020000 - 5c027fff
2621 * IMG_BUF_A 5c040000 - 5c040fff
2622 * IMG_BUF_B 5c042000 - 5c042fff
2623 * VLCDS 5c048000 - 5c0487ff
2624 * IMX_COEF 5c049000 - 5c04afff
2625 * IMX_CMD 5c051000 - 5c051fff
2626 * VLCDQ 5c053000 - 5c0533ff
2627 * VLCDH 5c054000 - 5c054fff
2628 * SEQ_CMD 5c055000 - 5c055fff
2629 * IMX_REG 5c056000 - 5c0560ff
2630 * VLCD_REG 5c056100 - 5c0561ff
2631 * SEQ_REG 5c056200 - 5c0562ff
2632 * IMG_BUF_REG 5c056300 - 5c0563ff
2633 * SEQIRQ_REG 5c056400 - 5c0564ff
2634 * OCP_REG 5c060000 - 5c060fff
2635 * SYSC_REG 5c070000 - 5c070fff
2636 * MMU_REG 5d000000 - 5d000fff
2637 * sDMA R 68000400 - 680005ff
2638 * sDMA W 68000600 - 680007ff
2639 * Display Control 68000800 - 680009ff
2640 * DSP subsystem 68000a00 - 68000bff
2641 * MPU subsystem 68000c00 - 68000dff
2642 * IVA subsystem 68001000 - 680011ff
2643 * USB 68001200 - 680013ff
2644 * Camera 68001400 - 680015ff
2645 * VLYNQ (firewall) 68001800 - 68001bff
2646 * VLYNQ 68001e00 - 68001fff
2647 * SSI 68002000 - 680021ff
2648 * L4 68002400 - 680025ff
2649 * DSP (firewall) 68002800 - 68002bff
2650 * DSP subsystem 68002e00 - 68002fff
2651 * IVA (firewall) 68003000 - 680033ff
2652 * IVA 68003600 - 680037ff
2653 * GFX 68003a00 - 68003bff
2654 * CMDWR emulation 68003c00 - 68003dff
2655 * SMS 68004000 - 680041ff
2656 * OCM 68004200 - 680043ff
2657 * GPMC 68004400 - 680045ff
2658 * RAM (firewall) 68005000 - 680053ff
2659 * RAM (err login) 68005400 - 680057ff
2660 * ROM (firewall) 68005800 - 68005bff
2661 * ROM (err login) 68005c00 - 68005fff
2662 * GPMC (firewall) 68006000 - 680063ff
2663 * GPMC (err login) 68006400 - 680067ff
2664 * SMS (err login) 68006c00 - 68006fff
2665 * SMS registers 68008000 - 68008fff
2666 * SDRC registers 68009000 - 68009fff
2667 * GPMC registers 6800a000 6800afff
2668 */
2669
2670 qemu_register_reset(omap2_mpu_reset, s);
2671
2672 return s;
2673 }
QEmu