hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pci_bridge.h"
  27 #include "pci_internals.h"
  28 #include "monitor.h"
  29 #include "net.h"
  30 #include "sysemu.h"
  31 #include "loader.h"
  32 #include "qemu-objects.h"
  33
  34 //#define DEBUG_PCI
  35 #ifdef DEBUG_PCI
  36 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  37 #else
  38 # define PCI_DPRINTF(format, ...)       do { } while (0)
  39 #endif
  40
  41 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  42 static char *pcibus_get_dev_path(DeviceState *dev);
  43
  44 struct BusInfo pci_bus_info = {
  45     .name       = "PCI",
  46     .size       = sizeof(PCIBus),
  47     .print_dev  = pcibus_dev_print,
  48     .get_dev_path = pcibus_get_dev_path,
  49     .props      = (Property[]) {
  50         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  51         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  52         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  53         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
  54                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
  55         DEFINE_PROP_END_OF_LIST()
  56     }
  57 };
  58
  59 static void pci_update_mappings(PCIDevice *d);
  60 static void pci_set_irq(void *opaque, int irq_num, int level);
  61 static int pci_add_option_rom(PCIDevice *pdev);
  62 static void pci_del_option_rom(PCIDevice *pdev);
  63
  64 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  65 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  66
  67 struct PCIHostBus {
  68     int domain;
  69     struct PCIBus *bus;
  70     QLIST_ENTRY(PCIHostBus) next;
  71 };
  72 static QLIST_HEAD(, PCIHostBus) host_buses;
  73
  74 static const VMStateDescription vmstate_pcibus = {
  75     .name = "PCIBUS",
  76     .version_id = 1,
  77     .minimum_version_id = 1,
  78     .minimum_version_id_old = 1,
  79     .fields      = (VMStateField []) {
  80         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  81         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  82         VMSTATE_END_OF_LIST()
  83     }
  84 };
  85
  86 static int pci_bar(PCIDevice *d, int reg)
  87 {
  88     uint8_t type;
  89
  90     if (reg != PCI_ROM_SLOT)
  91         return PCI_BASE_ADDRESS_0 + reg * 4;
  92
  93     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
  94     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
  95 }
  96
  97 static inline int pci_irq_state(PCIDevice *d, int irq_num)
  98 {
  99         return (d->irq_state >> irq_num) & 0x1;
 100 }
 101
 102 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 103 {
 104         d->irq_state &= ~(0x1 << irq_num);
 105         d->irq_state |= level << irq_num;
 106 }
 107
 108 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 109 {
 110     PCIBus *bus;
 111     for (;;) {
 112         bus = pci_dev->bus;
 113         irq_num = bus->map_irq(pci_dev, irq_num);
 114         if (bus->set_irq)
 115             break;
 116         pci_dev = bus->parent_dev;
 117     }
 118     bus->irq_count[irq_num] += change;
 119     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 120 }
 121
 122 /* Update interrupt status bit in config space on interrupt
 123  * state change. */
 124 static void pci_update_irq_status(PCIDevice *dev)
 125 {
 126     if (dev->irq_state) {
 127         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 128     } else {
 129         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 130     }
 131 }
 132
 133 static void pci_device_reset(PCIDevice *dev)
 134 {
 135     int r;
 136
 137     dev->irq_state = 0;
 138     pci_update_irq_status(dev);
 139     /* Clear all writeable bits */
 140     pci_set_word(dev->config + PCI_COMMAND,
 141                  pci_get_word(dev->config + PCI_COMMAND) &
 142                  ~pci_get_word(dev->wmask + PCI_COMMAND));
 143     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 144     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 145     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 146         PCIIORegion *region = &dev->io_regions[r];
 147         if (!region->size) {
 148             continue;
 149         }
 150
 151         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 152             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 153             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
 154         } else {
 155             pci_set_long(dev->config + pci_bar(dev, r), region->type);
 156         }
 157     }
 158     pci_update_mappings(dev);
 159 }
 160
 161 static void pci_bus_reset(void *opaque)
 162 {
 163     PCIBus *bus = opaque;
 164     int i;
 165
 166     for (i = 0; i < bus->nirq; i++) {
 167         bus->irq_count[i] = 0;
 168     }
 169     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 170         if (bus->devices[i]) {
 171             pci_device_reset(bus->devices[i]);
 172         }
 173     }
 174 }
 175
 176 static void pci_host_bus_register(int domain, PCIBus *bus)
 177 {
 178     struct PCIHostBus *host;
 179     host = qemu_mallocz(sizeof(*host));
 180     host->domain = domain;
 181     host->bus = bus;
 182     QLIST_INSERT_HEAD(&host_buses, host, next);
 183 }
 184
 185 PCIBus *pci_find_root_bus(int domain)
 186 {
 187     struct PCIHostBus *host;
 188
 189     QLIST_FOREACH(host, &host_buses, next) {
 190         if (host->domain == domain) {
 191             return host->bus;
 192         }
 193     }
 194
 195     return NULL;
 196 }
 197
 198 int pci_find_domain(const PCIBus *bus)
 199 {
 200     PCIDevice *d;
 201     struct PCIHostBus *host;
 202
 203     /* obtain root bus */
 204     while ((d = bus->parent_dev) != NULL) {
 205         bus = d->bus;
 206     }
 207
 208     QLIST_FOREACH(host, &host_buses, next) {
 209         if (host->bus == bus) {
 210             return host->domain;
 211         }
 212     }
 213
 214     abort();    /* should not be reached */
 215     return -1;
 216 }
 217
 218 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 219                          const char *name, int devfn_min)
 220 {
 221     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 222     assert(PCI_FUNC(devfn_min) == 0);
 223     bus->devfn_min = devfn_min;
 224
 225     /* host bridge */
 226     QLIST_INIT(&bus->child);
 227     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 228
 229     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 230     qemu_register_reset(pci_bus_reset, bus);
 231 }
 232
 233 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 234 {
 235     PCIBus *bus;
 236
 237     bus = qemu_mallocz(sizeof(*bus));
 238     bus->qbus.qdev_allocated = 1;
 239     pci_bus_new_inplace(bus, parent, name, devfn_min);
 240     return bus;
 241 }
 242
 243 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 244                   void *irq_opaque, int nirq)
 245 {
 246     bus->set_irq = set_irq;
 247     bus->map_irq = map_irq;
 248     bus->irq_opaque = irq_opaque;
 249     bus->nirq = nirq;
 250     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 251 }
 252
 253 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 254 {
 255     bus->qbus.allow_hotplug = 1;
 256     bus->hotplug = hotplug;
 257     bus->hotplug_qdev = qdev;
 258 }
 259
 260 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 261 {
 262     bus->mem_base = base;
 263 }
 264
 265 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 266                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 267                          void *irq_opaque, int devfn_min, int nirq)
 268 {
 269     PCIBus *bus;
 270
 271     bus = pci_bus_new(parent, name, devfn_min);
 272     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 273     return bus;
 274 }
 275
 276 int pci_bus_num(PCIBus *s)
 277 {
 278     if (!s->parent_dev)
 279         return 0;       /* pci host bridge */
 280     return s->parent_dev->config[PCI_SECONDARY_BUS];
 281 }
 282
 283 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 284 {
 285     PCIDevice *s = container_of(pv, PCIDevice, config);
 286     uint8_t *config;
 287     int i;
 288
 289     assert(size == pci_config_size(s));
 290     config = qemu_malloc(size);
 291
 292     qemu_get_buffer(f, config, size);
 293     for (i = 0; i < size; ++i) {
 294         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 295             qemu_free(config);
 296             return -EINVAL;
 297         }
 298     }
 299     memcpy(s->config, config, size);
 300
 301     pci_update_mappings(s);
 302
 303     qemu_free(config);
 304     return 0;
 305 }
 306
 307 /* just put buffer */
 308 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 309 {
 310     const uint8_t **v = pv;
 311     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 312     qemu_put_buffer(f, *v, size);
 313 }
 314
 315 static VMStateInfo vmstate_info_pci_config = {
 316     .name = "pci config",
 317     .get  = get_pci_config_device,
 318     .put  = put_pci_config_device,
 319 };
 320
 321 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 322 {
 323     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 324     uint32_t irq_state[PCI_NUM_PINS];
 325     int i;
 326     for (i = 0; i < PCI_NUM_PINS; ++i) {
 327         irq_state[i] = qemu_get_be32(f);
 328         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 329             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 330                     irq_state[i]);
 331             return -EINVAL;
 332         }
 333     }
 334
 335     for (i = 0; i < PCI_NUM_PINS; ++i) {
 336         pci_set_irq_state(s, i, irq_state[i]);
 337     }
 338
 339     return 0;
 340 }
 341
 342 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 343 {
 344     int i;
 345     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 346
 347     for (i = 0; i < PCI_NUM_PINS; ++i) {
 348         qemu_put_be32(f, pci_irq_state(s, i));
 349     }
 350 }
 351
 352 static VMStateInfo vmstate_info_pci_irq_state = {
 353     .name = "pci irq state",
 354     .get  = get_pci_irq_state,
 355     .put  = put_pci_irq_state,
 356 };
 357
 358 const VMStateDescription vmstate_pci_device = {
 359     .name = "PCIDevice",
 360     .version_id = 2,
 361     .minimum_version_id = 1,
 362     .minimum_version_id_old = 1,
 363     .fields      = (VMStateField []) {
 364         VMSTATE_INT32_LE(version_id, PCIDevice),
 365         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 366                                    vmstate_info_pci_config,
 367                                    PCI_CONFIG_SPACE_SIZE),
 368         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 369                                    vmstate_info_pci_irq_state,
 370                                    PCI_NUM_PINS * sizeof(int32_t)),
 371         VMSTATE_END_OF_LIST()
 372     }
 373 };
 374
 375 const VMStateDescription vmstate_pcie_device = {
 376     .name = "PCIDevice",
 377     .version_id = 2,
 378     .minimum_version_id = 1,
 379     .minimum_version_id_old = 1,
 380     .fields      = (VMStateField []) {
 381         VMSTATE_INT32_LE(version_id, PCIDevice),
 382         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 383                                    vmstate_info_pci_config,
 384                                    PCIE_CONFIG_SPACE_SIZE),
 385         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 386                                    vmstate_info_pci_irq_state,
 387                                    PCI_NUM_PINS * sizeof(int32_t)),
 388         VMSTATE_END_OF_LIST()
 389     }
 390 };
 391
 392 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 393 {
 394     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 395 }
 396
 397 void pci_device_save(PCIDevice *s, QEMUFile *f)
 398 {
 399     /* Clear interrupt status bit: it is implicit
 400      * in irq_state which we are saving.
 401      * This makes us compatible with old devices
 402      * which never set or clear this bit. */
 403     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 404     vmstate_save_state(f, pci_get_vmstate(s), s);
 405     /* Restore the interrupt status bit. */
 406     pci_update_irq_status(s);
 407 }
 408
 409 int pci_device_load(PCIDevice *s, QEMUFile *f)
 410 {
 411     int ret;
 412     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 413     /* Restore the interrupt status bit. */
 414     pci_update_irq_status(s);
 415     return ret;
 416 }
 417
 418 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 419 {
 420     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 421                  pci_default_sub_vendor_id);
 422     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 423                  pci_default_sub_device_id);
 424 }
 425
 426 /*
 427  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 428  */
 429 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 430 {
 431     const char *p;
 432     char *e;
 433     unsigned long val;
 434     unsigned long dom = 0, bus = 0;
 435     unsigned slot = 0;
 436
 437     p = addr;
 438     val = strtoul(p, &e, 16);
 439     if (e == p)
 440         return -1;
 441     if (*e == ':') {
 442         bus = val;
 443         p = e + 1;
 444         val = strtoul(p, &e, 16);
 445         if (e == p)
 446             return -1;
 447         if (*e == ':') {
 448             dom = bus;
 449             bus = val;
 450             p = e + 1;
 451             val = strtoul(p, &e, 16);
 452             if (e == p)
 453                 return -1;
 454         }
 455     }
 456
 457     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 458         return -1;
 459
 460     slot = val;
 461
 462     if (*e)
 463         return -1;
 464
 465     /* Note: QEMU doesn't implement domains other than 0 */
 466     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 467         return -1;
 468
 469     *domp = dom;
 470     *busp = bus;
 471     *slotp = slot;
 472     return 0;
 473 }
 474
 475 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 476                      unsigned *slotp)
 477 {
 478     /* strip legacy tag */
 479     if (!strncmp(addr, "pci_addr=", 9)) {
 480         addr += 9;
 481     }
 482     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 483         monitor_printf(mon, "Invalid pci address\n");
 484         return -1;
 485     }
 486     return 0;
 487 }
 488
 489 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 490 {
 491     int dom, bus;
 492     unsigned slot;
 493
 494     if (!devaddr) {
 495         *devfnp = -1;
 496         return pci_find_bus(pci_find_root_bus(0), 0);
 497     }
 498
 499     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 500         return NULL;
 501     }
 502
 503     *devfnp = slot << 3;
 504     return pci_find_bus(pci_find_root_bus(dom), bus);
 505 }
 506
 507 static void pci_init_cmask(PCIDevice *dev)
 508 {
 509     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 510     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 511     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 512     dev->cmask[PCI_REVISION_ID] = 0xff;
 513     dev->cmask[PCI_CLASS_PROG] = 0xff;
 514     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 515     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 516     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 517 }
 518
 519 static void pci_init_wmask(PCIDevice *dev)
 520 {
 521     int config_size = pci_config_size(dev);
 522
 523     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 524     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 525     pci_set_word(dev->wmask + PCI_COMMAND,
 526                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 527                  PCI_COMMAND_INTX_DISABLE);
 528
 529     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 530            config_size - PCI_CONFIG_HEADER_SIZE);
 531 }
 532
 533 static void pci_init_wmask_bridge(PCIDevice *d)
 534 {
 535     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 536        PCI_SEC_LETENCY_TIMER */
 537     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 538
 539     /* base and limit */
 540     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 541     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 542     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 543                  PCI_MEMORY_RANGE_MASK & 0xffff);
 544     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 545                  PCI_MEMORY_RANGE_MASK & 0xffff);
 546     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 547                  PCI_PREF_RANGE_MASK & 0xffff);
 548     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 549                  PCI_PREF_RANGE_MASK & 0xffff);
 550
 551     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 552     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 553
 554     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 555 }
 556
 557 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
 558 {
 559     uint8_t slot = PCI_SLOT(dev->devfn);
 560     uint8_t func;
 561
 562     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 563         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
 564     }
 565
 566     /*
 567      * multifuction bit is interpreted in two ways as follows.
 568      *   - all functions must set the bit to 1.
 569      *     Example: Intel X53
 570      *   - function 0 must set the bit, but the rest function (> 0)
 571      *     is allowed to leave the bit to 0.
 572      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
 573      *
 574      * So OS (at least Linux) checks the bit of only function 0,
 575      * and doesn't see the bit of function > 0.
 576      *
 577      * The below check allows both interpretation.
 578      */
 579     if (PCI_FUNC(dev->devfn)) {
 580         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
 581         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
 582             /* function 0 should set multifunction bit */
 583             error_report("PCI: single function device can't be populated "
 584                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
 585             return -1;
 586         }
 587         return 0;
 588     }
 589
 590     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
 591         return 0;
 592     }
 593     /* function 0 indicates single function, so function > 0 must be NULL */
 594     for (func = 1; func < PCI_FUNC_MAX; ++func) {
 595         if (bus->devices[PCI_DEVFN(slot, func)]) {
 596             error_report("PCI: %x.0 indicates single function, "
 597                          "but %x.%x is already populated.",
 598                          slot, slot, func);
 599             return -1;
 600         }
 601     }
 602     return 0;
 603 }
 604
 605 static void pci_config_alloc(PCIDevice *pci_dev)
 606 {
 607     int config_size = pci_config_size(pci_dev);
 608
 609     pci_dev->config = qemu_mallocz(config_size);
 610     pci_dev->cmask = qemu_mallocz(config_size);
 611     pci_dev->wmask = qemu_mallocz(config_size);
 612     pci_dev->used = qemu_mallocz(config_size);
 613 }
 614
 615 static void pci_config_free(PCIDevice *pci_dev)
 616 {
 617     qemu_free(pci_dev->config);
 618     qemu_free(pci_dev->cmask);
 619     qemu_free(pci_dev->wmask);
 620     qemu_free(pci_dev->used);
 621 }
 622
 623 /* -1 for devfn means auto assign */
 624 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 625                                          const char *name, int devfn,
 626                                          PCIConfigReadFunc *config_read,
 627                                          PCIConfigWriteFunc *config_write,
 628                                          bool is_bridge)
 629 {
 630     if (devfn < 0) {
 631         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 632             devfn += PCI_FUNC_MAX) {
 633             if (!bus->devices[devfn])
 634                 goto found;
 635         }
 636         error_report("PCI: no slot/function available for %s, all in use", name);
 637         return NULL;
 638     found: ;
 639     } else if (bus->devices[devfn]) {
 640         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 641                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 642         return NULL;
 643     }
 644     pci_dev->bus = bus;
 645     pci_dev->devfn = devfn;
 646     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 647     pci_dev->irq_state = 0;
 648     pci_config_alloc(pci_dev);
 649
 650     if (!is_bridge) {
 651         pci_set_default_subsystem_id(pci_dev);
 652     }
 653     pci_init_cmask(pci_dev);
 654     pci_init_wmask(pci_dev);
 655     if (is_bridge) {
 656         pci_init_wmask_bridge(pci_dev);
 657     }
 658     if (pci_init_multifunction(bus, pci_dev)) {
 659         pci_config_free(pci_dev);
 660         return NULL;
 661     }
 662
 663     if (!config_read)
 664         config_read = pci_default_read_config;
 665     if (!config_write)
 666         config_write = pci_default_write_config;
 667     pci_dev->config_read = config_read;
 668     pci_dev->config_write = config_write;
 669     bus->devices[devfn] = pci_dev;
 670     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 671     pci_dev->version_id = 2; /* Current pci device vmstate version */
 672     return pci_dev;
 673 }
 674
 675 static void do_pci_unregister_device(PCIDevice *pci_dev)
 676 {
 677     qemu_free_irqs(pci_dev->irq);
 678     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 679     pci_config_free(pci_dev);
 680 }
 681
 682 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 683                                int instance_size, int devfn,
 684                                PCIConfigReadFunc *config_read,
 685                                PCIConfigWriteFunc *config_write)
 686 {
 687     PCIDevice *pci_dev;
 688
 689     pci_dev = qemu_mallocz(instance_size);
 690     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 691                                      config_read, config_write,
 692                                      PCI_HEADER_TYPE_NORMAL);
 693     if (pci_dev == NULL) {
 694         hw_error("PCI: can't register device\n");
 695     }
 696     return pci_dev;
 697 }
 698
 699 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 700                                           target_phys_addr_t addr)
 701 {
 702     return addr + bus->mem_base;
 703 }
 704
 705 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 706 {
 707     PCIIORegion *r;
 708     int i;
 709
 710     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 711         r = &pci_dev->io_regions[i];
 712         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 713             continue;
 714         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 715             isa_unassign_ioport(r->addr, r->filtered_size);
 716         } else {
 717             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 718                                                          r->addr),
 719                                          r->filtered_size,
 720                                          IO_MEM_UNASSIGNED);
 721         }
 722     }
 723 }
 724
 725 static int pci_unregister_device(DeviceState *dev)
 726 {
 727     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 728     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 729     int ret = 0;
 730
 731     if (info->exit)
 732         ret = info->exit(pci_dev);
 733     if (ret)
 734         return ret;
 735
 736     pci_unregister_io_regions(pci_dev);
 737     pci_del_option_rom(pci_dev);
 738     do_pci_unregister_device(pci_dev);
 739     return 0;
 740 }
 741
 742 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 743                             pcibus_t size, int type,
 744                             PCIMapIORegionFunc *map_func)
 745 {
 746     PCIIORegion *r;
 747     uint32_t addr;
 748     pcibus_t wmask;
 749
 750     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 751         return;
 752
 753     if (size & (size-1)) {
 754         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 755                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 756         exit(1);
 757     }
 758
 759     r = &pci_dev->io_regions[region_num];
 760     r->addr = PCI_BAR_UNMAPPED;
 761     r->size = size;
 762     r->filtered_size = size;
 763     r->type = type;
 764     r->map_func = map_func;
 765
 766     wmask = ~(size - 1);
 767     addr = pci_bar(pci_dev, region_num);
 768     if (region_num == PCI_ROM_SLOT) {
 769         /* ROM enable bit is writeable */
 770         wmask |= PCI_ROM_ADDRESS_ENABLE;
 771     }
 772     pci_set_long(pci_dev->config + addr, type);
 773     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 774         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 775         pci_set_quad(pci_dev->wmask + addr, wmask);
 776         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 777     } else {
 778         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 779         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 780     }
 781 }
 782
 783 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 784                               uint8_t type)
 785 {
 786     pcibus_t base = *addr;
 787     pcibus_t limit = *addr + *size - 1;
 788     PCIDevice *br;
 789
 790     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 791         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 792
 793         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 794             if (!(cmd & PCI_COMMAND_IO)) {
 795                 goto no_map;
 796             }
 797         } else {
 798             if (!(cmd & PCI_COMMAND_MEMORY)) {
 799                 goto no_map;
 800             }
 801         }
 802
 803         base = MAX(base, pci_bridge_get_base(br, type));
 804         limit = MIN(limit, pci_bridge_get_limit(br, type));
 805     }
 806
 807     if (base > limit) {
 808         goto no_map;
 809     }
 810     *addr = base;
 811     *size = limit - base + 1;
 812     return;
 813 no_map:
 814     *addr = PCI_BAR_UNMAPPED;
 815     *size = 0;
 816 }
 817
 818 static pcibus_t pci_bar_address(PCIDevice *d,
 819                                 int reg, uint8_t type, pcibus_t size)
 820 {
 821     pcibus_t new_addr, last_addr;
 822     int bar = pci_bar(d, reg);
 823     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 824
 825     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 826         if (!(cmd & PCI_COMMAND_IO)) {
 827             return PCI_BAR_UNMAPPED;
 828         }
 829         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 830         last_addr = new_addr + size - 1;
 831         /* NOTE: we have only 64K ioports on PC */
 832         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 833             return PCI_BAR_UNMAPPED;
 834         }
 835         return new_addr;
 836     }
 837
 838     if (!(cmd & PCI_COMMAND_MEMORY)) {
 839         return PCI_BAR_UNMAPPED;
 840     }
 841     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 842         new_addr = pci_get_quad(d->config + bar);
 843     } else {
 844         new_addr = pci_get_long(d->config + bar);
 845     }
 846     /* the ROM slot has a specific enable bit */
 847     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 848         return PCI_BAR_UNMAPPED;
 849     }
 850     new_addr &= ~(size - 1);
 851     last_addr = new_addr + size - 1;
 852     /* NOTE: we do not support wrapping */
 853     /* XXX: as we cannot support really dynamic
 854        mappings, we handle specific values as invalid
 855        mappings. */
 856     if (last_addr <= new_addr || new_addr == 0 ||
 857         last_addr == PCI_BAR_UNMAPPED) {
 858         return PCI_BAR_UNMAPPED;
 859     }
 860
 861     /* Now pcibus_t is 64bit.
 862      * Check if 32 bit BAR wraps around explicitly.
 863      * Without this, PC ide doesn't work well.
 864      * TODO: remove this work around.
 865      */
 866     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 867         return PCI_BAR_UNMAPPED;
 868     }
 869
 870     /*
 871      * OS is allowed to set BAR beyond its addressable
 872      * bits. For example, 32 bit OS can set 64bit bar
 873      * to >4G. Check it. TODO: we might need to support
 874      * it in the future for e.g. PAE.
 875      */
 876     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 877         return PCI_BAR_UNMAPPED;
 878     }
 879
 880     return new_addr;
 881 }
 882
 883 static void pci_update_mappings(PCIDevice *d)
 884 {
 885     PCIIORegion *r;
 886     int i;
 887     pcibus_t new_addr, filtered_size;
 888
 889     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 890         r = &d->io_regions[i];
 891
 892         /* this region isn't registered */
 893         if (!r->size)
 894             continue;
 895
 896         new_addr = pci_bar_address(d, i, r->type, r->size);
 897
 898         /* bridge filtering */
 899         filtered_size = r->size;
 900         if (new_addr != PCI_BAR_UNMAPPED) {
 901             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 902         }
 903
 904         /* This bar isn't changed */
 905         if (new_addr == r->addr && filtered_size == r->filtered_size)
 906             continue;
 907
 908         /* now do the real mapping */
 909         if (r->addr != PCI_BAR_UNMAPPED) {
 910             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 911                 int class;
 912                 /* NOTE: specific hack for IDE in PC case:
 913                    only one byte must be mapped. */
 914                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 915                 if (class == 0x0101 && r->size == 4) {
 916                     isa_unassign_ioport(r->addr + 2, 1);
 917                 } else {
 918                     isa_unassign_ioport(r->addr, r->filtered_size);
 919                 }
 920             } else {
 921                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
 922                                              r->filtered_size,
 923                                              IO_MEM_UNASSIGNED);
 924                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 925             }
 926         }
 927         r->addr = new_addr;
 928         r->filtered_size = filtered_size;
 929         if (r->addr != PCI_BAR_UNMAPPED) {
 930             /*
 931              * TODO: currently almost all the map funcions assumes
 932              * filtered_size == size and addr & ~(size - 1) == addr.
 933              * However with bridge filtering, they aren't always true.
 934              * Teach them such cases, such that filtered_size < size and
 935              * addr & (size - 1) != 0.
 936              */
 937             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 938                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
 939             } else {
 940                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
 941                             r->filtered_size, r->type);
 942             }
 943         }
 944     }
 945 }
 946
 947 static inline int pci_irq_disabled(PCIDevice *d)
 948 {
 949     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
 950 }
 951
 952 /* Called after interrupt disabled field update in config space,
 953  * assert/deassert interrupts if necessary.
 954  * Gets original interrupt disable bit value (before update). */
 955 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
 956 {
 957     int i, disabled = pci_irq_disabled(d);
 958     if (disabled == was_irq_disabled)
 959         return;
 960     for (i = 0; i < PCI_NUM_PINS; ++i) {
 961         int state = pci_irq_state(d, i);
 962         pci_change_irq_level(d, i, disabled ? -state : state);
 963     }
 964 }
 965
 966 uint32_t pci_default_read_config(PCIDevice *d,
 967                                  uint32_t address, int len)
 968 {
 969     uint32_t val = 0;
 970     assert(len == 1 || len == 2 || len == 4);
 971     len = MIN(len, pci_config_size(d) - address);
 972     memcpy(&val, d->config + address, len);
 973     return le32_to_cpu(val);
 974 }
 975
 976 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 977 {
 978     int i, was_irq_disabled = pci_irq_disabled(d);
 979     uint32_t config_size = pci_config_size(d);
 980
 981     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 982         uint8_t wmask = d->wmask[addr + i];
 983         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
 984     }
 985     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
 986         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
 987         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
 988         range_covers_byte(addr, l, PCI_COMMAND))
 989         pci_update_mappings(d);
 990
 991     if (range_covers_byte(addr, l, PCI_COMMAND))
 992         pci_update_irq_disabled(d, was_irq_disabled);
 993 }
 994
 995 /***********************************************************/
 996 /* generic PCI irq support */
 997
 998 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 999 static void pci_set_irq(void *opaque, int irq_num, int level)
1000 {
1001     PCIDevice *pci_dev = opaque;
1002     int change;
1003
1004     change = level - pci_irq_state(pci_dev, irq_num);
1005     if (!change)
1006         return;
1007
1008     pci_set_irq_state(pci_dev, irq_num, level);
1009     pci_update_irq_status(pci_dev);
1010     if (pci_irq_disabled(pci_dev))
1011         return;
1012     pci_change_irq_level(pci_dev, irq_num, change);
1013 }
1014
1015 /***********************************************************/
1016 /* monitor info on PCI */
1017
1018 typedef struct {
1019     uint16_t class;
1020     const char *desc;
1021 } pci_class_desc;
1022
1023 static const pci_class_desc pci_class_descriptions[] =
1024 {
1025     { 0x0100, "SCSI controller"},
1026     { 0x0101, "IDE controller"},
1027     { 0x0102, "Floppy controller"},
1028     { 0x0103, "IPI controller"},
1029     { 0x0104, "RAID controller"},
1030     { 0x0106, "SATA controller"},
1031     { 0x0107, "SAS controller"},
1032     { 0x0180, "Storage controller"},
1033     { 0x0200, "Ethernet controller"},
1034     { 0x0201, "Token Ring controller"},
1035     { 0x0202, "FDDI controller"},
1036     { 0x0203, "ATM controller"},
1037     { 0x0280, "Network controller"},
1038     { 0x0300, "VGA controller"},
1039     { 0x0301, "XGA controller"},
1040     { 0x0302, "3D controller"},
1041     { 0x0380, "Display controller"},
1042     { 0x0400, "Video controller"},
1043     { 0x0401, "Audio controller"},
1044     { 0x0402, "Phone"},
1045     { 0x0480, "Multimedia controller"},
1046     { 0x0500, "RAM controller"},
1047     { 0x0501, "Flash controller"},
1048     { 0x0580, "Memory controller"},
1049     { 0x0600, "Host bridge"},
1050     { 0x0601, "ISA bridge"},
1051     { 0x0602, "EISA bridge"},
1052     { 0x0603, "MC bridge"},
1053     { 0x0604, "PCI bridge"},
1054     { 0x0605, "PCMCIA bridge"},
1055     { 0x0606, "NUBUS bridge"},
1056     { 0x0607, "CARDBUS bridge"},
1057     { 0x0608, "RACEWAY bridge"},
1058     { 0x0680, "Bridge"},
1059     { 0x0c03, "USB controller"},
1060     { 0, NULL}
1061 };
1062
1063 static void pci_for_each_device_under_bus(PCIBus *bus,
1064                                           void (*fn)(PCIBus *b, PCIDevice *d))
1065 {
1066     PCIDevice *d;
1067     int devfn;
1068
1069     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1070         d = bus->devices[devfn];
1071         if (d) {
1072             fn(bus, d);
1073         }
1074     }
1075 }
1076
1077 void pci_for_each_device(PCIBus *bus, int bus_num,
1078                          void (*fn)(PCIBus *b, PCIDevice *d))
1079 {
1080     bus = pci_find_bus(bus, bus_num);
1081
1082     if (bus) {
1083         pci_for_each_device_under_bus(bus, fn);
1084     }
1085 }
1086
1087 static void pci_device_print(Monitor *mon, QDict *device)
1088 {
1089     QDict *qdict;
1090     QListEntry *entry;
1091     uint64_t addr, size;
1092
1093     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1094     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1095                         qdict_get_int(device, "slot"),
1096                         qdict_get_int(device, "function"));
1097     monitor_printf(mon, "    ");
1098
1099     qdict = qdict_get_qdict(device, "class_info");
1100     if (qdict_haskey(qdict, "desc")) {
1101         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1102     } else {
1103         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1104     }
1105
1106     qdict = qdict_get_qdict(device, "id");
1107     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1108                         qdict_get_int(qdict, "device"),
1109                         qdict_get_int(qdict, "vendor"));
1110
1111     if (qdict_haskey(device, "irq")) {
1112         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1113                             qdict_get_int(device, "irq"));
1114     }
1115
1116     if (qdict_haskey(device, "pci_bridge")) {
1117         QDict *info;
1118
1119         qdict = qdict_get_qdict(device, "pci_bridge");
1120
1121         info = qdict_get_qdict(qdict, "bus");
1122         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1123                             qdict_get_int(info, "number"));
1124         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1125                             qdict_get_int(info, "secondary"));
1126         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1127                             qdict_get_int(info, "subordinate"));
1128
1129         info = qdict_get_qdict(qdict, "io_range");
1130         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1131                        qdict_get_int(info, "base"),
1132                        qdict_get_int(info, "limit"));
1133
1134         info = qdict_get_qdict(qdict, "memory_range");
1135         monitor_printf(mon,
1136                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1137                        qdict_get_int(info, "base"),
1138                        qdict_get_int(info, "limit"));
1139
1140         info = qdict_get_qdict(qdict, "prefetchable_range");
1141         monitor_printf(mon, "      prefetchable memory range "
1142                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1143                        qdict_get_int(info, "base"),
1144         qdict_get_int(info, "limit"));
1145     }
1146
1147     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1148         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1149         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1150
1151         addr = qdict_get_int(qdict, "address");
1152         size = qdict_get_int(qdict, "size");
1153
1154         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1155             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1156                                 " [0x%04"FMT_PCIBUS"].\n",
1157                                 addr, addr + size - 1);
1158         } else {
1159             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1160                                " [0x%08"FMT_PCIBUS"].\n",
1161                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1162                                 qdict_get_bool(qdict, "prefetch") ?
1163                                 " prefetchable" : "", addr, addr + size - 1);
1164         }
1165     }
1166
1167     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1168
1169     if (qdict_haskey(device, "pci_bridge")) {
1170         qdict = qdict_get_qdict(device, "pci_bridge");
1171         if (qdict_haskey(qdict, "devices")) {
1172             QListEntry *dev;
1173             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1174                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1175             }
1176         }
1177     }
1178 }
1179
1180 void do_pci_info_print(Monitor *mon, const QObject *data)
1181 {
1182     QListEntry *bus, *dev;
1183
1184     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1185         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1186         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1187             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1188         }
1189     }
1190 }
1191
1192 static QObject *pci_get_dev_class(const PCIDevice *dev)
1193 {
1194     int class;
1195     const pci_class_desc *desc;
1196
1197     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1198     desc = pci_class_descriptions;
1199     while (desc->desc && class != desc->class)
1200         desc++;
1201
1202     if (desc->desc) {
1203         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1204                                   desc->desc, class);
1205     } else {
1206         return qobject_from_jsonf("{ 'class': %d }", class);
1207     }
1208 }
1209
1210 static QObject *pci_get_dev_id(const PCIDevice *dev)
1211 {
1212     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1213                               pci_get_word(dev->config + PCI_VENDOR_ID),
1214                               pci_get_word(dev->config + PCI_DEVICE_ID));
1215 }
1216
1217 static QObject *pci_get_regions_list(const PCIDevice *dev)
1218 {
1219     int i;
1220     QList *regions_list;
1221
1222     regions_list = qlist_new();
1223
1224     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1225         QObject *obj;
1226         const PCIIORegion *r = &dev->io_regions[i];
1227
1228         if (!r->size) {
1229             continue;
1230         }
1231
1232         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1233             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1234                                      "'address': %" PRId64 ", "
1235                                      "'size': %" PRId64 " }",
1236                                      i, r->addr, r->size);
1237         } else {
1238             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1239
1240             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1241                                      "'mem_type_64': %i, 'prefetch': %i, "
1242                                      "'address': %" PRId64 ", "
1243                                      "'size': %" PRId64 " }",
1244                                      i, mem_type_64,
1245                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1246                                      r->addr, r->size);
1247         }
1248
1249         qlist_append_obj(regions_list, obj);
1250     }
1251
1252     return QOBJECT(regions_list);
1253 }
1254
1255 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1256
1257 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1258 {
1259     uint8_t type;
1260     QObject *obj;
1261
1262     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1263                               " 'qdev_id': %s }",
1264                               bus_num,
1265                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1266                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1267                               pci_get_regions_list(dev),
1268                               dev->qdev.id ? dev->qdev.id : "");
1269
1270     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1271         QDict *qdict = qobject_to_qdict(obj);
1272         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1273     }
1274
1275     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1276     if (type == PCI_HEADER_TYPE_BRIDGE) {
1277         QDict *qdict;
1278         QObject *pci_bridge;
1279
1280         pci_bridge = qobject_from_jsonf("{ 'bus': "
1281         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1282         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1283         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1284         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1285         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1286         dev->config[PCI_SUBORDINATE_BUS],
1287         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1288         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1289         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1290         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1291         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1292                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1293         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1294                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1295
1296         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1297             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1298
1299             if (child_bus) {
1300                 qdict = qobject_to_qdict(pci_bridge);
1301                 qdict_put_obj(qdict, "devices",
1302                               pci_get_devices_list(child_bus,
1303                                                    dev->config[PCI_SECONDARY_BUS]));
1304             }
1305         }
1306         qdict = qobject_to_qdict(obj);
1307         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1308     }
1309
1310     return obj;
1311 }
1312
1313 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1314 {
1315     int devfn;
1316     PCIDevice *dev;
1317     QList *dev_list;
1318
1319     dev_list = qlist_new();
1320
1321     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1322         dev = bus->devices[devfn];
1323         if (dev) {
1324             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1325         }
1326     }
1327
1328     return QOBJECT(dev_list);
1329 }
1330
1331 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1332 {
1333     bus = pci_find_bus(bus, bus_num);
1334     if (bus) {
1335         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1336                                   bus_num, pci_get_devices_list(bus, bus_num));
1337     }
1338
1339     return NULL;
1340 }
1341
1342 void do_pci_info(Monitor *mon, QObject **ret_data)
1343 {
1344     QList *bus_list;
1345     struct PCIHostBus *host;
1346
1347     bus_list = qlist_new();
1348
1349     QLIST_FOREACH(host, &host_buses, next) {
1350         QObject *obj = pci_get_bus_dict(host->bus, 0);
1351         if (obj) {
1352             qlist_append_obj(bus_list, obj);
1353         }
1354     }
1355
1356     *ret_data = QOBJECT(bus_list);
1357 }
1358
1359 static const char * const pci_nic_models[] = {
1360     "ne2k_pci",
1361     "i82551",
1362     "i82557b",
1363     "i82559er",
1364     "rtl8139",
1365     "e1000",
1366     "pcnet",
1367     "virtio",
1368     NULL
1369 };
1370
1371 static const char * const pci_nic_names[] = {
1372     "ne2k_pci",
1373     "i82551",
1374     "i82557b",
1375     "i82559er",
1376     "rtl8139",
1377     "e1000",
1378     "pcnet",
1379     "virtio-net-pci",
1380     NULL
1381 };
1382
1383 /* Initialize a PCI NIC.  */
1384 /* FIXME callers should check for failure, but don't */
1385 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1386                         const char *default_devaddr)
1387 {
1388     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1389     PCIBus *bus;
1390     int devfn;
1391     PCIDevice *pci_dev;
1392     DeviceState *dev;
1393     int i;
1394
1395     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1396     if (i < 0)
1397         return NULL;
1398
1399     bus = pci_get_bus_devfn(&devfn, devaddr);
1400     if (!bus) {
1401         error_report("Invalid PCI device address %s for device %s",
1402                      devaddr, pci_nic_names[i]);
1403         return NULL;
1404     }
1405
1406     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1407     dev = &pci_dev->qdev;
1408     qdev_set_nic_properties(dev, nd);
1409     if (qdev_init(dev) < 0)
1410         return NULL;
1411     return pci_dev;
1412 }
1413
1414 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1415                                const char *default_devaddr)
1416 {
1417     PCIDevice *res;
1418
1419     if (qemu_show_nic_models(nd->model, pci_nic_models))
1420         exit(0);
1421
1422     res = pci_nic_init(nd, default_model, default_devaddr);
1423     if (!res)
1424         exit(1);
1425     return res;
1426 }
1427
1428 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1429 {
1430     pci_update_mappings(d);
1431 }
1432
1433 void pci_bridge_update_mappings(PCIBus *b)
1434 {
1435     PCIBus *child;
1436
1437     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1438
1439     QLIST_FOREACH(child, &b->child, sibling) {
1440         pci_bridge_update_mappings(child);
1441     }
1442 }
1443
1444 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1445 {
1446     PCIBus *sec;
1447
1448     if (!bus) {
1449         return NULL;
1450     }
1451
1452     if (pci_bus_num(bus) == bus_num) {
1453         return bus;
1454     }
1455
1456     /* try child bus */
1457     if (!bus->parent_dev /* host pci bridge */ ||
1458         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1459          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1460         for (; bus; bus = sec) {
1461             QLIST_FOREACH(sec, &bus->child, sibling) {
1462                 assert(sec->parent_dev);
1463                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1464                     return sec;
1465                 }
1466                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1467                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1468                     break;
1469                 }
1470             }
1471         }
1472     }
1473
1474     return NULL;
1475 }
1476
1477 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1478 {
1479     bus = pci_find_bus(bus, bus_num);
1480
1481     if (!bus)
1482         return NULL;
1483
1484     return bus->devices[PCI_DEVFN(slot, function)];
1485 }
1486
1487 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1488 {
1489     PCIDevice *pci_dev = (PCIDevice *)qdev;
1490     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1491     PCIBus *bus;
1492     int devfn, rc;
1493
1494     /* initialize cap_present for pci_is_express() and pci_config_size() */
1495     if (info->is_express) {
1496         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1497     }
1498
1499     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1500     devfn = pci_dev->devfn;
1501     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1502                                      info->config_read, info->config_write,
1503                                      info->is_bridge);
1504     if (pci_dev == NULL)
1505         return -1;
1506     rc = info->init(pci_dev);
1507     if (rc != 0) {
1508         do_pci_unregister_device(pci_dev);
1509         return rc;
1510     }
1511
1512     /* rom loading */
1513     if (pci_dev->romfile == NULL && info->romfile != NULL)
1514         pci_dev->romfile = qemu_strdup(info->romfile);
1515     pci_add_option_rom(pci_dev);
1516
1517     if (bus->hotplug) {
1518         /* lower layer must check qdev->hotplugged */
1519         rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1520         if (rc != 0) {
1521             int r = pci_unregister_device(&pci_dev->qdev);
1522             assert(!r);
1523             return rc;
1524         }
1525     }
1526     return 0;
1527 }
1528
1529 static int pci_unplug_device(DeviceState *qdev)
1530 {
1531     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1532
1533     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1534 }
1535
1536 void pci_qdev_register(PCIDeviceInfo *info)
1537 {
1538     info->qdev.init = pci_qdev_init;
1539     info->qdev.unplug = pci_unplug_device;
1540     info->qdev.exit = pci_unregister_device;
1541     info->qdev.bus_info = &pci_bus_info;
1542     qdev_register(&info->qdev);
1543 }
1544
1545 void pci_qdev_register_many(PCIDeviceInfo *info)
1546 {
1547     while (info->qdev.name) {
1548         pci_qdev_register(info);
1549         info++;
1550     }
1551 }
1552
1553 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1554                                     const char *name)
1555 {
1556     DeviceState *dev;
1557
1558     dev = qdev_create(&bus->qbus, name);
1559     qdev_prop_set_uint32(dev, "addr", devfn);
1560     qdev_prop_set_bit(dev, "multifunction", multifunction);
1561     return DO_UPCAST(PCIDevice, qdev, dev);
1562 }
1563
1564 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1565                                            bool multifunction,
1566                                            const char *name)
1567 {
1568     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1569     qdev_init_nofail(&dev->qdev);
1570     return dev;
1571 }
1572
1573 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1574 {
1575     return pci_create_multifunction(bus, devfn, false, name);
1576 }
1577
1578 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1579 {
1580     return pci_create_simple_multifunction(bus, devfn, false, name);
1581 }
1582
1583 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1584 {
1585     int config_size = pci_config_size(pdev);
1586     int offset = PCI_CONFIG_HEADER_SIZE;
1587     int i;
1588     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1589         if (pdev->used[i])
1590             offset = i + 1;
1591         else if (i - offset + 1 == size)
1592             return offset;
1593     return 0;
1594 }
1595
1596 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1597                                         uint8_t *prev_p)
1598 {
1599     uint8_t next, prev;
1600
1601     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1602         return 0;
1603
1604     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1605          prev = next + PCI_CAP_LIST_NEXT)
1606         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1607             break;
1608
1609     if (prev_p)
1610         *prev_p = prev;
1611     return next;
1612 }
1613
1614 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1615 {
1616     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1617 }
1618
1619 /* Add an option rom for the device */
1620 static int pci_add_option_rom(PCIDevice *pdev)
1621 {
1622     int size;
1623     char *path;
1624     void *ptr;
1625     char name[32];
1626
1627     if (!pdev->romfile)
1628         return 0;
1629     if (strlen(pdev->romfile) == 0)
1630         return 0;
1631
1632     if (!pdev->rom_bar) {
1633         /*
1634          * Load rom via fw_cfg instead of creating a rom bar,
1635          * for 0.11 compatibility.
1636          */
1637         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1638         if (class == 0x0300) {
1639             rom_add_vga(pdev->romfile);
1640         } else {
1641             rom_add_option(pdev->romfile);
1642         }
1643         return 0;
1644     }
1645
1646     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1647     if (path == NULL) {
1648         path = qemu_strdup(pdev->romfile);
1649     }
1650
1651     size = get_image_size(path);
1652     if (size < 0) {
1653         error_report("%s: failed to find romfile \"%s\"",
1654                      __FUNCTION__, pdev->romfile);
1655         return -1;
1656     }
1657     if (size & (size - 1)) {
1658         size = 1 << qemu_fls(size);
1659     }
1660
1661     if (pdev->qdev.info->vmsd)
1662         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1663     else
1664         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1665     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1666
1667     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1668     load_image(path, ptr);
1669     qemu_free(path);
1670
1671     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1672                      0, pci_map_option_rom);
1673
1674     return 0;
1675 }
1676
1677 static void pci_del_option_rom(PCIDevice *pdev)
1678 {
1679     if (!pdev->rom_offset)
1680         return;
1681
1682     qemu_ram_free(pdev->rom_offset);
1683     pdev->rom_offset = 0;
1684 }
1685
1686 /*
1687  * if !offset
1688  * Reserve space and add capability to the linked list in pci config space
1689  *
1690  * if offset = 0,
1691  * Find and reserve space and add capability to the linked list
1692  * in pci config space */
1693 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1694                        uint8_t offset, uint8_t size)
1695 {
1696     uint8_t *config;
1697     if (!offset) {
1698         offset = pci_find_space(pdev, size);
1699         if (!offset) {
1700             return -ENOSPC;
1701         }
1702     }
1703
1704     config = pdev->config + offset;
1705     config[PCI_CAP_LIST_ID] = cap_id;
1706     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1707     pdev->config[PCI_CAPABILITY_LIST] = offset;
1708     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1709     memset(pdev->used + offset, 0xFF, size);
1710     /* Make capability read-only by default */
1711     memset(pdev->wmask + offset, 0, size);
1712     /* Check capability by default */
1713     memset(pdev->cmask + offset, 0xFF, size);
1714     return offset;
1715 }
1716
1717 /* Unlink capability from the pci config space. */
1718 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1719 {
1720     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1721     if (!offset)
1722         return;
1723     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1724     /* Make capability writeable again */
1725     memset(pdev->wmask + offset, 0xff, size);
1726     /* Clear cmask as device-specific registers can't be checked */
1727     memset(pdev->cmask + offset, 0, size);
1728     memset(pdev->used + offset, 0, size);
1729
1730     if (!pdev->config[PCI_CAPABILITY_LIST])
1731         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1732 }
1733
1734 /* Reserve space for capability at a known offset (to call after load). */
1735 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1736 {
1737     memset(pdev->used + offset, 0xff, size);
1738 }
1739
1740 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1741 {
1742     return pci_find_capability_list(pdev, cap_id, NULL);
1743 }
1744
1745 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1746 {
1747     PCIDevice *d = (PCIDevice *)dev;
1748     const pci_class_desc *desc;
1749     char ctxt[64];
1750     PCIIORegion *r;
1751     int i, class;
1752
1753     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1754     desc = pci_class_descriptions;
1755     while (desc->desc && class != desc->class)
1756         desc++;
1757     if (desc->desc) {
1758         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1759     } else {
1760         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1761     }
1762
1763     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1764                    "pci id %04x:%04x (sub %04x:%04x)\n",
1765                    indent, "", ctxt,
1766                    d->config[PCI_SECONDARY_BUS],
1767                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1768                    pci_get_word(d->config + PCI_VENDOR_ID),
1769                    pci_get_word(d->config + PCI_DEVICE_ID),
1770                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1771                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1772     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1773         r = &d->io_regions[i];
1774         if (!r->size)
1775             continue;
1776         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1777                        " [0x%"FMT_PCIBUS"]\n",
1778                        indent, "",
1779                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1780                        r->addr, r->addr + r->size - 1);
1781     }
1782 }
1783
1784 static char *pcibus_get_dev_path(DeviceState *dev)
1785 {
1786     PCIDevice *d = (PCIDevice *)dev;
1787     char path[16];
1788
1789     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1790              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1791              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1792
1793     return strdup(path);
1794 }
1795