2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
26 #if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28 # define TARGET_LONG_BITS 64
30 # define TARGET_LONG_BITS 32
33 /* ARM processors have a weak memory model */
34 #define TCG_GUEST_DEFAULT_MO (0)
36 #define CPUArchState struct CPUARMState
38 #include "qemu-common.h"
40 #include "exec/cpu-defs.h"
42 #include "fpu/softfloat.h"
44 #define EXCP_UDEF 1 /* undefined instruction */
45 #define EXCP_SWI 2 /* software interrupt */
46 #define EXCP_PREFETCH_ABORT 3
47 #define EXCP_DATA_ABORT 4
51 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
52 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
53 #define EXCP_HVC 11 /* HyperVisor Call */
54 #define EXCP_HYP_TRAP 12
55 #define EXCP_SMC 13 /* Secure Monitor Call */
58 #define EXCP_SEMIHOST 16 /* semihosting call */
59 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
60 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
61 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
63 #define ARMV7M_EXCP_RESET 1
64 #define ARMV7M_EXCP_NMI 2
65 #define ARMV7M_EXCP_HARD 3
66 #define ARMV7M_EXCP_MEM 4
67 #define ARMV7M_EXCP_BUS 5
68 #define ARMV7M_EXCP_USAGE 6
69 #define ARMV7M_EXCP_SECURE 7
70 #define ARMV7M_EXCP_SVC 11
71 #define ARMV7M_EXCP_DEBUG 12
72 #define ARMV7M_EXCP_PENDSV 14
73 #define ARMV7M_EXCP_SYSTICK 15
75 /* For M profile, some registers are banked secure vs non-secure;
76 * these are represented as a 2-element array where the first element
77 * is the non-secure copy and the second is the secure copy.
78 * When the CPU does not have implement the security extension then
79 * only the first element is used.
80 * This means that the copy for the current security state can be
81 * accessed via env->registerfield[env->v7m.secure] (whether the security
82 * extension is implemented or not).
90 /* ARM-specific interrupt pending bits. */
91 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
92 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
93 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
95 /* The usual mapping for an AArch64 system register to its AArch32
96 * counterpart is for the 32 bit world to have access to the lower
97 * half only (with writes leaving the upper half untouched). It's
98 * therefore useful to be able to pass TCG the offset of the least
99 * significant half of a uint64_t struct member.
101 #ifdef HOST_WORDS_BIGENDIAN
102 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103 #define offsetofhigh32(S, M) offsetof(S, M)
105 #define offsetoflow32(S, M) offsetof(S, M)
106 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
109 /* Meanings of the ARMCPU object's four inbound GPIO lines */
110 #define ARM_CPU_IRQ 0
111 #define ARM_CPU_FIQ 1
112 #define ARM_CPU_VIRQ 2
113 #define ARM_CPU_VFIQ 3
115 #define NB_MMU_MODES 8
116 /* ARM-specific extra insn start words:
117 * 1: Conditional execution bits
118 * 2: Partial exception syndrome for data aborts
120 #define TARGET_INSN_START_EXTRA_WORDS 2
122 /* The 2nd extra word holding syndrome info for data aborts does not use
123 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
124 * help the sleb128 encoder do a better job.
125 * When restoring the CPU state, we shift it back up.
127 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
128 #define ARM_INSN_START_WORD2_SHIFT 14
130 /* We currently assume float and double are IEEE single and double
131 precision respectively.
132 Doing runtime conversions is tricky because VFP registers may contain
133 integer values (eg. as the result of a FTOSI instruction).
134 s<2n> maps to the least significant half of d<n>
135 s<2n+1> maps to the most significant half of d<n>
138 /* CPU state for each instance of a generic timer (in cp15 c14) */
139 typedef struct ARMGenericTimer
{
140 uint64_t cval
; /* Timer CompareValue register */
141 uint64_t ctl
; /* Timer Control register */
144 #define GTIMER_PHYS 0
145 #define GTIMER_VIRT 1
148 #define NUM_GTIMERS 4
156 /* Define a maximum sized vector register.
157 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
158 * For 64-bit, this is a 2048-bit SVE register.
160 * Note that the mapping between S, D, and Q views of the register bank
161 * differs between AArch64 and AArch32.
163 * Qn = regs[n].d[1]:regs[n].d[0]
164 * Dn = regs[n / 2].d[n & 1]
165 * Sn = regs[n / 4].d[n % 4 / 2],
166 * bits 31..0 for even n, and bits 63..32 for odd n
167 * (and regs[16] to regs[31] are inaccessible)
170 * Qn = regs[n].d[1]:regs[n].d[0]
172 * Sn = regs[n].d[0] bits 31..0
174 * This corresponds to the architecturally defined mapping between
175 * the two execution states, and means we do not need to explicitly
176 * map these registers when changing states.
178 * Align the data for use with TCG host vector operations.
181 #ifdef TARGET_AARCH64
182 # define ARM_MAX_VQ 16
184 # define ARM_MAX_VQ 1
187 typedef struct ARMVectorReg
{
188 uint64_t d
[2 * ARM_MAX_VQ
] QEMU_ALIGNED(16);
191 /* In AArch32 mode, predicate registers do not exist at all. */
192 #ifdef TARGET_AARCH64
193 typedef struct ARMPredicateReg
{
194 uint64_t p
[2 * ARM_MAX_VQ
/ 8] QEMU_ALIGNED(16);
199 typedef struct CPUARMState
{
200 /* Regs for current mode. */
203 /* 32/64 switch only happens when taking and returning from
204 * exceptions so the overlap semantics are taken care of then
205 * instead of having a complicated union.
207 /* Regs for A64 mode. */
210 /* PSTATE isn't an architectural register for ARMv8. However, it is
211 * convenient for us to assemble the underlying state into a 32 bit format
212 * identical to the architectural format used for the SPSR. (This is also
213 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
214 * 'pstate' register are.) Of the PSTATE bits:
215 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
216 * semantics as for AArch32, as described in the comments on each field)
217 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
218 * DAIF (exception masks) are kept in env->daif
219 * all other bits are stored in their correct places in env->pstate
222 uint32_t aarch64
; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
224 /* Frequently accessed CPSR bits are stored separately for efficiency.
225 This contains all the other bits. Use cpsr_{read,write} to access
227 uint32_t uncached_cpsr
;
230 /* Banked registers. */
231 uint64_t banked_spsr
[8];
232 uint32_t banked_r13
[8];
233 uint32_t banked_r14
[8];
235 /* These hold r8-r12. */
236 uint32_t usr_regs
[5];
237 uint32_t fiq_regs
[5];
239 /* cpsr flag cache for faster execution */
240 uint32_t CF
; /* 0 or 1 */
241 uint32_t VF
; /* V is the bit 31. All other bits are undefined */
242 uint32_t NF
; /* N is bit 31. All other bits are undefined. */
243 uint32_t ZF
; /* Z set if zero. */
244 uint32_t QF
; /* 0 or 1 */
245 uint32_t GE
; /* cpsr[19:16] */
246 uint32_t thumb
; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
247 uint32_t condexec_bits
; /* IT bits. cpsr[15:10,26:25]. */
248 uint64_t daif
; /* exception masks, in the bits they are in PSTATE */
250 uint64_t elr_el
[4]; /* AArch64 exception link regs */
251 uint64_t sp_el
[4]; /* AArch64 banked stack pointers */
253 /* System control coprocessor (cp15) */
256 union { /* Cache size selection */
258 uint64_t _unused_csselr0
;
260 uint64_t _unused_csselr1
;
263 uint64_t csselr_el
[4];
265 union { /* System control register. */
267 uint64_t _unused_sctlr
;
272 uint64_t sctlr_el
[4];
274 uint64_t cpacr_el1
; /* Architectural feature access control register */
275 uint64_t cptr_el
[4]; /* ARMv8 feature trap registers */
276 uint32_t c1_xscaleauxcr
; /* XScale auxiliary control register. */
277 uint64_t sder
; /* Secure debug enable register. */
278 uint32_t nsacr
; /* Non-secure access control register. */
279 union { /* MMU translation table base 0. */
281 uint64_t _unused_ttbr0_0
;
283 uint64_t _unused_ttbr0_1
;
286 uint64_t ttbr0_el
[4];
288 union { /* MMU translation table base 1. */
290 uint64_t _unused_ttbr1_0
;
292 uint64_t _unused_ttbr1_1
;
295 uint64_t ttbr1_el
[4];
297 uint64_t vttbr_el2
; /* Virtualization Translation Table Base. */
298 /* MMU translation table base control. */
300 TCR vtcr_el2
; /* Virtualization Translation Control. */
301 uint32_t c2_data
; /* MPU data cacheable bits. */
302 uint32_t c2_insn
; /* MPU instruction cacheable bits. */
303 union { /* MMU domain access control register
304 * MPU write buffer control.
314 uint32_t pmsav5_data_ap
; /* PMSAv5 MPU data access permissions */
315 uint32_t pmsav5_insn_ap
; /* PMSAv5 MPU insn access permissions */
316 uint64_t hcr_el2
; /* Hypervisor configuration register */
317 uint64_t scr_el3
; /* Secure configuration register. */
318 union { /* Fault status registers. */
329 uint64_t _unused_dfsr
;
336 uint32_t c6_region
[8]; /* MPU base/size registers. */
337 union { /* Fault address registers. */
339 uint64_t _unused_far0
;
340 #ifdef HOST_WORDS_BIGENDIAN
351 uint64_t _unused_far3
;
357 union { /* Translation result. */
359 uint64_t _unused_par_0
;
361 uint64_t _unused_par_1
;
367 uint32_t c9_insn
; /* Cache lockdown registers. */
369 uint64_t c9_pmcr
; /* performance monitor control register */
370 uint64_t c9_pmcnten
; /* perf monitor counter enables */
371 uint32_t c9_pmovsr
; /* perf monitor overflow status */
372 uint32_t c9_pmuserenr
; /* perf monitor user enable */
373 uint64_t c9_pmselr
; /* perf monitor counter selection register */
374 uint64_t c9_pminten
; /* perf monitor interrupt enables */
375 union { /* Memory attribute redirection */
377 #ifdef HOST_WORDS_BIGENDIAN
378 uint64_t _unused_mair_0
;
381 uint64_t _unused_mair_1
;
385 uint64_t _unused_mair_0
;
388 uint64_t _unused_mair_1
;
395 union { /* vector base address register */
397 uint64_t _unused_vbar
;
404 uint32_t mvbar
; /* (monitor) vector base address register */
405 struct { /* FCSE PID. */
409 union { /* Context ID. */
411 uint64_t _unused_contextidr_0
;
412 uint64_t contextidr_ns
;
413 uint64_t _unused_contextidr_1
;
414 uint64_t contextidr_s
;
416 uint64_t contextidr_el
[4];
418 union { /* User RW Thread register. */
420 uint64_t tpidrurw_ns
;
421 uint64_t tpidrprw_ns
;
425 uint64_t tpidr_el
[4];
427 /* The secure banks of these registers don't map anywhere */
432 union { /* User RO Thread register. */
433 uint64_t tpidruro_ns
;
434 uint64_t tpidrro_el
[1];
436 uint64_t c14_cntfrq
; /* Counter Frequency register */
437 uint64_t c14_cntkctl
; /* Timer Control register */
438 uint32_t cnthctl_el2
; /* Counter/Timer Hyp Control register */
439 uint64_t cntvoff_el2
; /* Counter Virtual Offset register */
440 ARMGenericTimer c14_timer
[NUM_GTIMERS
];
441 uint32_t c15_cpar
; /* XScale Coprocessor Access Register */
442 uint32_t c15_ticonfig
; /* TI925T configuration byte. */
443 uint32_t c15_i_max
; /* Maximum D-cache dirty line index. */
444 uint32_t c15_i_min
; /* Minimum D-cache dirty line index. */
445 uint32_t c15_threadid
; /* TI debugger thread-ID. */
446 uint32_t c15_config_base_address
; /* SCU base address. */
447 uint32_t c15_diagnostic
; /* diagnostic register */
448 uint32_t c15_power_diagnostic
;
449 uint32_t c15_power_control
; /* power control */
450 uint64_t dbgbvr
[16]; /* breakpoint value registers */
451 uint64_t dbgbcr
[16]; /* breakpoint control registers */
452 uint64_t dbgwvr
[16]; /* watchpoint value registers */
453 uint64_t dbgwcr
[16]; /* watchpoint control registers */
455 uint64_t oslsr_el1
; /* OS Lock Status */
458 /* If the counter is enabled, this stores the last time the counter
459 * was reset. Otherwise it stores the counter value
462 uint64_t pmccfiltr_el0
; /* Performance Monitor Filter Register */
463 uint64_t vpidr_el2
; /* Virtualization Processor ID Register */
464 uint64_t vmpidr_el2
; /* Virtualization Multiprocessor ID Register */
468 /* M profile has up to 4 stack pointers:
469 * a Main Stack Pointer and a Process Stack Pointer for each
470 * of the Secure and Non-Secure states. (If the CPU doesn't support
471 * the security extension then it has only two SPs.)
472 * In QEMU we always store the currently active SP in regs[13],
473 * and the non-active SP for the current security state in
474 * v7m.other_sp. The stack pointers for the inactive security state
475 * are stored in other_ss_msp and other_ss_psp.
476 * switch_v7m_security_state() is responsible for rearranging them
477 * when we change security state.
480 uint32_t other_ss_msp
;
481 uint32_t other_ss_psp
;
482 uint32_t vecbase
[M_REG_NUM_BANKS
];
483 uint32_t basepri
[M_REG_NUM_BANKS
];
484 uint32_t control
[M_REG_NUM_BANKS
];
485 uint32_t ccr
[M_REG_NUM_BANKS
]; /* Configuration and Control */
486 uint32_t cfsr
[M_REG_NUM_BANKS
]; /* Configurable Fault Status */
487 uint32_t hfsr
; /* HardFault Status */
488 uint32_t dfsr
; /* Debug Fault Status Register */
489 uint32_t sfsr
; /* Secure Fault Status Register */
490 uint32_t mmfar
[M_REG_NUM_BANKS
]; /* MemManage Fault Address */
491 uint32_t bfar
; /* BusFault Address */
492 uint32_t sfar
; /* Secure Fault Address Register */
493 unsigned mpu_ctrl
[M_REG_NUM_BANKS
]; /* MPU_CTRL */
495 uint32_t primask
[M_REG_NUM_BANKS
];
496 uint32_t faultmask
[M_REG_NUM_BANKS
];
497 uint32_t aircr
; /* only holds r/w state if security extn implemented */
498 uint32_t secure
; /* Is CPU in Secure state? (not guest visible) */
501 /* Information associated with an exception about to be taken:
502 * code which raises an exception must set cs->exception_index and
503 * the relevant parts of this structure; the cpu_do_interrupt function
504 * will then set the guest-visible registers as part of the exception
508 uint32_t syndrome
; /* AArch64 format syndrome register */
509 uint32_t fsr
; /* AArch32 format fault status register info */
510 uint64_t vaddress
; /* virtual addr associated with exception, if any */
511 uint32_t target_el
; /* EL the exception should be targeted for */
512 /* If we implement EL2 we will also need to store information
513 * about the intermediate physical address for stage 2 faults.
517 /* Thumb-2 EE state. */
521 /* VFP coprocessor state. */
523 ARMVectorReg zregs
[32];
525 #ifdef TARGET_AARCH64
526 /* Store FFR as pregs[16] to make it easier to treat as any other. */
527 ARMPredicateReg pregs
[17];
531 /* We store these fpcsr fields separately for convenience. */
535 /* scratch space when Tn are not sufficient. */
538 /* fp_status is the "normal" fp status. standard_fp_status retains
539 * values corresponding to the ARM "Standard FPSCR Value", ie
540 * default-NaN, flush-to-zero, round-to-nearest and is used by
541 * any operations (generally Neon) which the architecture defines
542 * as controlled by the standard FPSCR value rather than the FPSCR.
544 * To avoid having to transfer exception bits around, we simply
545 * say that the FPSCR cumulative exception flags are the logical
546 * OR of the flags in the two fp statuses. This relies on the
547 * only thing which needs to read the exception flags being
548 * an explicit FPSCR read.
550 float_status fp_status
;
551 float_status standard_fp_status
;
556 uint64_t exclusive_addr
;
557 uint64_t exclusive_val
;
558 uint64_t exclusive_high
;
560 /* iwMMXt coprocessor state. */
568 #if defined(CONFIG_USER_ONLY)
569 /* For usermode syscall translation. */
573 struct CPUBreakpoint
*cpu_breakpoint
[16];
574 struct CPUWatchpoint
*cpu_watchpoint
[16];
576 /* Fields up to this point are cleared by a CPU reset */
577 struct {} end_reset_fields
;
581 /* Fields after CPU_COMMON are preserved across CPU reset. */
583 /* Internal CPU feature flags. */
591 uint32_t rnr
[M_REG_NUM_BANKS
];
596 /* The PMSAv8 implementation also shares some PMSAv7 config
598 * pmsav7.rnr (region number register)
599 * pmsav7_dregion (number of configured regions)
601 uint32_t *rbar
[M_REG_NUM_BANKS
];
602 uint32_t *rlar
[M_REG_NUM_BANKS
];
603 uint32_t mair0
[M_REG_NUM_BANKS
];
604 uint32_t mair1
[M_REG_NUM_BANKS
];
616 const struct arm_boot_info
*boot_info
;
617 /* Store GICv3CPUState to access from this struct */
623 * type of a function which can be registered via arm_register_el_change_hook()
624 * to get callbacks when the CPU changes its exception level or mode.
626 typedef void ARMELChangeHook(ARMCPU
*cpu
, void *opaque
);
629 /* These values map onto the return values for
630 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
631 typedef enum ARMPSCIState
{
650 /* Coprocessor information */
652 /* For marshalling (mostly coprocessor) register state between the
653 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
654 * we use these arrays.
656 /* List of register indexes managed via these arrays; (full KVM style
657 * 64 bit indexes, not CPRegInfo 32 bit indexes)
659 uint64_t *cpreg_indexes
;
660 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
661 uint64_t *cpreg_values
;
662 /* Length of the indexes, values, reset_values arrays */
663 int32_t cpreg_array_len
;
664 /* These are used only for migration: incoming data arrives in
665 * these fields and is sanity checked in post_load before copying
666 * to the working data structures above.
668 uint64_t *cpreg_vmstate_indexes
;
669 uint64_t *cpreg_vmstate_values
;
670 int32_t cpreg_vmstate_array_len
;
672 /* Timers used by the generic (architected) timer */
673 QEMUTimer
*gt_timer
[NUM_GTIMERS
];
674 /* GPIO outputs for generic timer */
675 qemu_irq gt_timer_outputs
[NUM_GTIMERS
];
676 /* GPIO output for GICv3 maintenance interrupt signal */
677 qemu_irq gicv3_maintenance_interrupt
;
678 /* GPIO output for the PMU interrupt */
679 qemu_irq pmu_interrupt
;
681 /* MemoryRegion to use for secure physical accesses */
682 MemoryRegion
*secure_memory
;
684 /* 'compatible' string for this CPU for Linux device trees */
685 const char *dtb_compatible
;
687 /* PSCI version for this CPU
688 * Bits[31:16] = Major Version
689 * Bits[15:0] = Minor Version
691 uint32_t psci_version
;
693 /* Should CPU start in PSCI powered-off state? */
694 bool start_powered_off
;
696 /* Current power state, access guarded by BQL */
697 ARMPSCIState power_state
;
699 /* CPU has virtualization extension */
701 /* CPU has security extension */
703 /* CPU has PMU (Performance Monitor Unit) */
706 /* CPU has memory protection unit */
708 /* PMSAv7 MPU number of supported regions */
709 uint32_t pmsav7_dregion
;
710 /* v8M SAU number of supported regions */
711 uint32_t sau_sregion
;
713 /* PSCI conduit used to invoke PSCI methods
714 * 0 - disabled, 1 - smc, 2 - hvc
716 uint32_t psci_conduit
;
718 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
719 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
723 /* KVM init features for this CPU */
724 uint32_t kvm_init_features
[7];
726 /* Uniprocessor system with MP extensions */
729 /* The instance init functions for implementation-specific subclasses
730 * set these fields to specify the implementation-dependent values of
731 * various constant registers and reset values of non-constant
733 * Some of these might become QOM properties eventually.
734 * Field names match the official register names as defined in the
735 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
736 * is used for reset values of non-constant registers; no reset_
737 * prefix means a constant register.
741 uint32_t reset_fpsid
;
746 uint32_t reset_sctlr
;
764 uint64_t id_aa64pfr0
;
765 uint64_t id_aa64pfr1
;
766 uint64_t id_aa64dfr0
;
767 uint64_t id_aa64dfr1
;
768 uint64_t id_aa64afr0
;
769 uint64_t id_aa64afr1
;
770 uint64_t id_aa64isar0
;
771 uint64_t id_aa64isar1
;
772 uint64_t id_aa64mmfr0
;
773 uint64_t id_aa64mmfr1
;
776 uint64_t mp_affinity
; /* MP ID without feature bits */
777 /* The elements of this array are the CCSIDR values for each cache,
778 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
782 uint32_t reset_auxcr
;
784 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
785 uint32_t dcz_blocksize
;
788 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
789 int gic_num_lrs
; /* number of list registers */
790 int gic_vpribits
; /* number of virtual priority bits */
791 int gic_vprebits
; /* number of virtual preemption bits */
793 /* Whether the cfgend input is high (i.e. this CPU should reset into
794 * big-endian mode). This setting isn't used directly: instead it modifies
795 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
796 * architecture version.
800 ARMELChangeHook
*el_change_hook
;
801 void *el_change_hook_opaque
;
803 int32_t node_id
; /* NUMA node this CPU belongs to */
805 /* Used to synchronize KVM and QEMU in-kernel device levels */
806 uint8_t device_irq_level
;
809 static inline ARMCPU
*arm_env_get_cpu(CPUARMState
*env
)
811 return container_of(env
, ARMCPU
, env
);
814 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
);
816 #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
818 #define ENV_OFFSET offsetof(ARMCPU, env)
820 #ifndef CONFIG_USER_ONLY
821 extern const struct VMStateDescription vmstate_arm_cpu
;
824 void arm_cpu_do_interrupt(CPUState
*cpu
);
825 void arm_v7m_cpu_do_interrupt(CPUState
*cpu
);
826 bool arm_cpu_exec_interrupt(CPUState
*cpu
, int int_req
);
828 void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
831 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cpu
, vaddr addr
,
834 int arm_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
835 int arm_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
837 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f
, CPUState
*cs
,
838 int cpuid
, void *opaque
);
839 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f
, CPUState
*cs
,
840 int cpuid
, void *opaque
);
842 #ifdef TARGET_AARCH64
843 int aarch64_cpu_gdb_read_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
844 int aarch64_cpu_gdb_write_register(CPUState
*cpu
, uint8_t *buf
, int reg
);
847 target_ulong
do_arm_semihosting(CPUARMState
*env
);
848 void aarch64_sync_32_to_64(CPUARMState
*env
);
849 void aarch64_sync_64_to_32(CPUARMState
*env
);
851 static inline bool is_a64(CPUARMState
*env
)
856 /* you can call this signal handler from your SIGBUS and SIGSEGV
857 signal handlers to inform the virtual CPU of exceptions. non zero
858 is returned if the signal was handled by the virtual CPU. */
859 int cpu_arm_signal_handler(int host_signum
, void *pinfo
,
866 * Synchronises the counter in the PMCCNTR. This must always be called twice,
867 * once before any action that might affect the timer and again afterwards.
868 * The function is used to swap the state of the register if required.
869 * This only happens when not in user mode (!CONFIG_USER_ONLY)
871 void pmccntr_sync(CPUARMState
*env
);
873 /* SCTLR bit meanings. Several bits have been reused in newer
874 * versions of the architecture; in that case we define constants
875 * for both old and new bit meanings. Code which tests against those
876 * bits should probably check or otherwise arrange that the CPU
877 * is the architectural version it expects.
879 #define SCTLR_M (1U << 0)
880 #define SCTLR_A (1U << 1)
881 #define SCTLR_C (1U << 2)
882 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
883 #define SCTLR_SA (1U << 3)
884 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
885 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
886 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
887 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
888 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
889 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
890 #define SCTLR_ITD (1U << 7) /* v8 onward */
891 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
892 #define SCTLR_SED (1U << 8) /* v8 onward */
893 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
894 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
895 #define SCTLR_F (1U << 10) /* up to v6 */
896 #define SCTLR_SW (1U << 10) /* v7 onward */
897 #define SCTLR_Z (1U << 11)
898 #define SCTLR_I (1U << 12)
899 #define SCTLR_V (1U << 13)
900 #define SCTLR_RR (1U << 14) /* up to v7 */
901 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
902 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
903 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
904 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
905 #define SCTLR_nTWI (1U << 16) /* v8 onward */
906 #define SCTLR_HA (1U << 17)
907 #define SCTLR_BR (1U << 17) /* PMSA only */
908 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
909 #define SCTLR_nTWE (1U << 18) /* v8 onward */
910 #define SCTLR_WXN (1U << 19)
911 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
912 #define SCTLR_UWXN (1U << 20) /* v7 onward */
913 #define SCTLR_FI (1U << 21)
914 #define SCTLR_U (1U << 22)
915 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
916 #define SCTLR_VE (1U << 24) /* up to v7 */
917 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
918 #define SCTLR_EE (1U << 25)
919 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
920 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
921 #define SCTLR_NMFI (1U << 27)
922 #define SCTLR_TRE (1U << 28)
923 #define SCTLR_AFE (1U << 29)
924 #define SCTLR_TE (1U << 30)
926 #define CPTR_TCPAC (1U << 31)
927 #define CPTR_TTA (1U << 20)
928 #define CPTR_TFP (1U << 10)
929 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
930 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
932 #define MDCR_EPMAD (1U << 21)
933 #define MDCR_EDAD (1U << 20)
934 #define MDCR_SPME (1U << 17)
935 #define MDCR_SDD (1U << 16)
936 #define MDCR_SPD (3U << 14)
937 #define MDCR_TDRA (1U << 11)
938 #define MDCR_TDOSA (1U << 10)
939 #define MDCR_TDA (1U << 9)
940 #define MDCR_TDE (1U << 8)
941 #define MDCR_HPME (1U << 7)
942 #define MDCR_TPM (1U << 6)
943 #define MDCR_TPMCR (1U << 5)
945 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
946 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
948 #define CPSR_M (0x1fU)
949 #define CPSR_T (1U << 5)
950 #define CPSR_F (1U << 6)
951 #define CPSR_I (1U << 7)
952 #define CPSR_A (1U << 8)
953 #define CPSR_E (1U << 9)
954 #define CPSR_IT_2_7 (0xfc00U)
955 #define CPSR_GE (0xfU << 16)
956 #define CPSR_IL (1U << 20)
957 /* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
958 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
959 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
960 * where it is live state but not accessible to the AArch32 code.
962 #define CPSR_RESERVED (0x7U << 21)
963 #define CPSR_J (1U << 24)
964 #define CPSR_IT_0_1 (3U << 25)
965 #define CPSR_Q (1U << 27)
966 #define CPSR_V (1U << 28)
967 #define CPSR_C (1U << 29)
968 #define CPSR_Z (1U << 30)
969 #define CPSR_N (1U << 31)
970 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
971 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
973 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
974 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
976 /* Bits writable in user mode. */
977 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
978 /* Execution state bits. MRS read as zero, MSR writes ignored. */
979 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
980 /* Mask of bits which may be set by exception return copying them from SPSR */
981 #define CPSR_ERET_MASK (~CPSR_RESERVED)
983 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
984 #define XPSR_EXCP 0x1ffU
985 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
986 #define XPSR_IT_2_7 CPSR_IT_2_7
987 #define XPSR_GE CPSR_GE
988 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
989 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
990 #define XPSR_IT_0_1 CPSR_IT_0_1
991 #define XPSR_Q CPSR_Q
992 #define XPSR_V CPSR_V
993 #define XPSR_C CPSR_C
994 #define XPSR_Z CPSR_Z
995 #define XPSR_N CPSR_N
996 #define XPSR_NZCV CPSR_NZCV
997 #define XPSR_IT CPSR_IT
999 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1000 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1001 #define TTBCR_PD0 (1U << 4)
1002 #define TTBCR_PD1 (1U << 5)
1003 #define TTBCR_EPD0 (1U << 7)
1004 #define TTBCR_IRGN0 (3U << 8)
1005 #define TTBCR_ORGN0 (3U << 10)
1006 #define TTBCR_SH0 (3U << 12)
1007 #define TTBCR_T1SZ (3U << 16)
1008 #define TTBCR_A1 (1U << 22)
1009 #define TTBCR_EPD1 (1U << 23)
1010 #define TTBCR_IRGN1 (3U << 24)
1011 #define TTBCR_ORGN1 (3U << 26)
1012 #define TTBCR_SH1 (1U << 28)
1013 #define TTBCR_EAE (1U << 31)
1015 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1016 * Only these are valid when in AArch64 mode; in
1017 * AArch32 mode SPSRs are basically CPSR-format.
1019 #define PSTATE_SP (1U)
1020 #define PSTATE_M (0xFU)
1021 #define PSTATE_nRW (1U << 4)
1022 #define PSTATE_F (1U << 6)
1023 #define PSTATE_I (1U << 7)
1024 #define PSTATE_A (1U << 8)
1025 #define PSTATE_D (1U << 9)
1026 #define PSTATE_IL (1U << 20)
1027 #define PSTATE_SS (1U << 21)
1028 #define PSTATE_V (1U << 28)
1029 #define PSTATE_C (1U << 29)
1030 #define PSTATE_Z (1U << 30)
1031 #define PSTATE_N (1U << 31)
1032 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1033 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1034 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
1035 /* Mode values for AArch64 */
1036 #define PSTATE_MODE_EL3h 13
1037 #define PSTATE_MODE_EL3t 12
1038 #define PSTATE_MODE_EL2h 9
1039 #define PSTATE_MODE_EL2t 8
1040 #define PSTATE_MODE_EL1h 5
1041 #define PSTATE_MODE_EL1t 4
1042 #define PSTATE_MODE_EL0t 0
1044 /* Write a new value to v7m.exception, thus transitioning into or out
1045 * of Handler mode; this may result in a change of active stack pointer.
1047 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
);
1049 /* Map EL and handler into a PSTATE_MODE. */
1050 static inline unsigned int aarch64_pstate_mode(unsigned int el
, bool handler
)
1052 return (el
<< 2) | handler
;
1055 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1056 * interprocessing, so we don't attempt to sync with the cpsr state used by
1057 * the 32 bit decoder.
1059 static inline uint32_t pstate_read(CPUARMState
*env
)
1063 ZF
= (env
->ZF
== 0);
1064 return (env
->NF
& 0x80000000) | (ZF
<< 30)
1065 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3)
1066 | env
->pstate
| env
->daif
;
1069 static inline void pstate_write(CPUARMState
*env
, uint32_t val
)
1071 env
->ZF
= (~val
) & PSTATE_Z
;
1073 env
->CF
= (val
>> 29) & 1;
1074 env
->VF
= (val
<< 3) & 0x80000000;
1075 env
->daif
= val
& PSTATE_DAIF
;
1076 env
->pstate
= val
& ~CACHED_PSTATE_BITS
;
1079 /* Return the current CPSR value. */
1080 uint32_t cpsr_read(CPUARMState
*env
);
1082 typedef enum CPSRWriteType
{
1083 CPSRWriteByInstr
= 0, /* from guest MSR or CPS */
1084 CPSRWriteExceptionReturn
= 1, /* from guest exception return insn */
1085 CPSRWriteRaw
= 2, /* trust values, do not switch reg banks */
1086 CPSRWriteByGDBStub
= 3, /* from the GDB stub */
1089 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1090 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
1091 CPSRWriteType write_type
);
1093 /* Return the current xPSR value. */
1094 static inline uint32_t xpsr_read(CPUARMState
*env
)
1097 ZF
= (env
->ZF
== 0);
1098 return (env
->NF
& 0x80000000) | (ZF
<< 30)
1099 | (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1100 | (env
->thumb
<< 24) | ((env
->condexec_bits
& 3) << 25)
1101 | ((env
->condexec_bits
& 0xfc) << 8)
1102 | env
->v7m
.exception
;
1105 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1106 static inline void xpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1108 if (mask
& XPSR_NZCV
) {
1109 env
->ZF
= (~val
) & XPSR_Z
;
1111 env
->CF
= (val
>> 29) & 1;
1112 env
->VF
= (val
<< 3) & 0x80000000;
1114 if (mask
& XPSR_Q
) {
1115 env
->QF
= ((val
& XPSR_Q
) != 0);
1117 if (mask
& XPSR_T
) {
1118 env
->thumb
= ((val
& XPSR_T
) != 0);
1120 if (mask
& XPSR_IT_0_1
) {
1121 env
->condexec_bits
&= ~3;
1122 env
->condexec_bits
|= (val
>> 25) & 3;
1124 if (mask
& XPSR_IT_2_7
) {
1125 env
->condexec_bits
&= 3;
1126 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1128 if (mask
& XPSR_EXCP
) {
1129 /* Note that this only happens on exception exit */
1130 write_v7m_exception(env
, val
& XPSR_EXCP
);
1134 #define HCR_VM (1ULL << 0)
1135 #define HCR_SWIO (1ULL << 1)
1136 #define HCR_PTW (1ULL << 2)
1137 #define HCR_FMO (1ULL << 3)
1138 #define HCR_IMO (1ULL << 4)
1139 #define HCR_AMO (1ULL << 5)
1140 #define HCR_VF (1ULL << 6)
1141 #define HCR_VI (1ULL << 7)
1142 #define HCR_VSE (1ULL << 8)
1143 #define HCR_FB (1ULL << 9)
1144 #define HCR_BSU_MASK (3ULL << 10)
1145 #define HCR_DC (1ULL << 12)
1146 #define HCR_TWI (1ULL << 13)
1147 #define HCR_TWE (1ULL << 14)
1148 #define HCR_TID0 (1ULL << 15)
1149 #define HCR_TID1 (1ULL << 16)
1150 #define HCR_TID2 (1ULL << 17)
1151 #define HCR_TID3 (1ULL << 18)
1152 #define HCR_TSC (1ULL << 19)
1153 #define HCR_TIDCP (1ULL << 20)
1154 #define HCR_TACR (1ULL << 21)
1155 #define HCR_TSW (1ULL << 22)
1156 #define HCR_TPC (1ULL << 23)
1157 #define HCR_TPU (1ULL << 24)
1158 #define HCR_TTLB (1ULL << 25)
1159 #define HCR_TVM (1ULL << 26)
1160 #define HCR_TGE (1ULL << 27)
1161 #define HCR_TDZ (1ULL << 28)
1162 #define HCR_HCD (1ULL << 29)
1163 #define HCR_TRVM (1ULL << 30)
1164 #define HCR_RW (1ULL << 31)
1165 #define HCR_CD (1ULL << 32)
1166 #define HCR_ID (1ULL << 33)
1167 #define HCR_MASK ((1ULL << 34) - 1)
1169 #define SCR_NS (1U << 0)
1170 #define SCR_IRQ (1U << 1)
1171 #define SCR_FIQ (1U << 2)
1172 #define SCR_EA (1U << 3)
1173 #define SCR_FW (1U << 4)
1174 #define SCR_AW (1U << 5)
1175 #define SCR_NET (1U << 6)
1176 #define SCR_SMD (1U << 7)
1177 #define SCR_HCE (1U << 8)
1178 #define SCR_SIF (1U << 9)
1179 #define SCR_RW (1U << 10)
1180 #define SCR_ST (1U << 11)
1181 #define SCR_TWI (1U << 12)
1182 #define SCR_TWE (1U << 13)
1183 #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
1184 #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
1186 /* Return the current FPSCR value. */
1187 uint32_t vfp_get_fpscr(CPUARMState
*env
);
1188 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
);
1190 /* For A64 the FPSCR is split into two logically distinct registers,
1191 * FPCR and FPSR. However since they still use non-overlapping bits
1192 * we store the underlying state in fpscr and just mask on read/write.
1194 #define FPSR_MASK 0xf800009f
1195 #define FPCR_MASK 0x07f79f00
1196 static inline uint32_t vfp_get_fpsr(CPUARMState
*env
)
1198 return vfp_get_fpscr(env
) & FPSR_MASK
;
1201 static inline void vfp_set_fpsr(CPUARMState
*env
, uint32_t val
)
1203 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPSR_MASK
) | (val
& FPSR_MASK
);
1204 vfp_set_fpscr(env
, new_fpscr
);
1207 static inline uint32_t vfp_get_fpcr(CPUARMState
*env
)
1209 return vfp_get_fpscr(env
) & FPCR_MASK
;
1212 static inline void vfp_set_fpcr(CPUARMState
*env
, uint32_t val
)
1214 uint32_t new_fpscr
= (vfp_get_fpscr(env
) & ~FPCR_MASK
) | (val
& FPCR_MASK
);
1215 vfp_set_fpscr(env
, new_fpscr
);
1219 ARM_CPU_MODE_USR
= 0x10,
1220 ARM_CPU_MODE_FIQ
= 0x11,
1221 ARM_CPU_MODE_IRQ
= 0x12,
1222 ARM_CPU_MODE_SVC
= 0x13,
1223 ARM_CPU_MODE_MON
= 0x16,
1224 ARM_CPU_MODE_ABT
= 0x17,
1225 ARM_CPU_MODE_HYP
= 0x1a,
1226 ARM_CPU_MODE_UND
= 0x1b,
1227 ARM_CPU_MODE_SYS
= 0x1f
1230 /* VFP system registers. */
1231 #define ARM_VFP_FPSID 0
1232 #define ARM_VFP_FPSCR 1
1233 #define ARM_VFP_MVFR2 5
1234 #define ARM_VFP_MVFR1 6
1235 #define ARM_VFP_MVFR0 7
1236 #define ARM_VFP_FPEXC 8
1237 #define ARM_VFP_FPINST 9
1238 #define ARM_VFP_FPINST2 10
1240 /* iwMMXt coprocessor control registers. */
1241 #define ARM_IWMMXT_wCID 0
1242 #define ARM_IWMMXT_wCon 1
1243 #define ARM_IWMMXT_wCSSF 2
1244 #define ARM_IWMMXT_wCASF 3
1245 #define ARM_IWMMXT_wCGR0 8
1246 #define ARM_IWMMXT_wCGR1 9
1247 #define ARM_IWMMXT_wCGR2 10
1248 #define ARM_IWMMXT_wCGR3 11
1251 FIELD(V7M_CCR
, NONBASETHRDENA
, 0, 1)
1252 FIELD(V7M_CCR
, USERSETMPEND
, 1, 1)
1253 FIELD(V7M_CCR
, UNALIGN_TRP
, 3, 1)
1254 FIELD(V7M_CCR
, DIV_0_TRP
, 4, 1)
1255 FIELD(V7M_CCR
, BFHFNMIGN
, 8, 1)
1256 FIELD(V7M_CCR
, STKALIGN
, 9, 1)
1257 FIELD(V7M_CCR
, DC
, 16, 1)
1258 FIELD(V7M_CCR
, IC
, 17, 1)
1260 /* V7M AIRCR bits */
1261 FIELD(V7M_AIRCR
, VECTRESET
, 0, 1)
1262 FIELD(V7M_AIRCR
, VECTCLRACTIVE
, 1, 1)
1263 FIELD(V7M_AIRCR
, SYSRESETREQ
, 2, 1)
1264 FIELD(V7M_AIRCR
, SYSRESETREQS
, 3, 1)
1265 FIELD(V7M_AIRCR
, PRIGROUP
, 8, 3)
1266 FIELD(V7M_AIRCR
, BFHFNMINS
, 13, 1)
1267 FIELD(V7M_AIRCR
, PRIS
, 14, 1)
1268 FIELD(V7M_AIRCR
, ENDIANNESS
, 15, 1)
1269 FIELD(V7M_AIRCR
, VECTKEY
, 16, 16)
1271 /* V7M CFSR bits for MMFSR */
1272 FIELD(V7M_CFSR
, IACCVIOL
, 0, 1)
1273 FIELD(V7M_CFSR
, DACCVIOL
, 1, 1)
1274 FIELD(V7M_CFSR
, MUNSTKERR
, 3, 1)
1275 FIELD(V7M_CFSR
, MSTKERR
, 4, 1)
1276 FIELD(V7M_CFSR
, MLSPERR
, 5, 1)
1277 FIELD(V7M_CFSR
, MMARVALID
, 7, 1)
1279 /* V7M CFSR bits for BFSR */
1280 FIELD(V7M_CFSR
, IBUSERR
, 8 + 0, 1)
1281 FIELD(V7M_CFSR
, PRECISERR
, 8 + 1, 1)
1282 FIELD(V7M_CFSR
, IMPRECISERR
, 8 + 2, 1)
1283 FIELD(V7M_CFSR
, UNSTKERR
, 8 + 3, 1)
1284 FIELD(V7M_CFSR
, STKERR
, 8 + 4, 1)
1285 FIELD(V7M_CFSR
, LSPERR
, 8 + 5, 1)
1286 FIELD(V7M_CFSR
, BFARVALID
, 8 + 7, 1)
1288 /* V7M CFSR bits for UFSR */
1289 FIELD(V7M_CFSR
, UNDEFINSTR
, 16 + 0, 1)
1290 FIELD(V7M_CFSR
, INVSTATE
, 16 + 1, 1)
1291 FIELD(V7M_CFSR
, INVPC
, 16 + 2, 1)
1292 FIELD(V7M_CFSR
, NOCP
, 16 + 3, 1)
1293 FIELD(V7M_CFSR
, UNALIGNED
, 16 + 8, 1)
1294 FIELD(V7M_CFSR
, DIVBYZERO
, 16 + 9, 1)
1296 /* V7M CFSR bit masks covering all of the subregister bits */
1297 FIELD(V7M_CFSR
, MMFSR
, 0, 8)
1298 FIELD(V7M_CFSR
, BFSR
, 8, 8)
1299 FIELD(V7M_CFSR
, UFSR
, 16, 16)
1302 FIELD(V7M_HFSR
, VECTTBL
, 1, 1)
1303 FIELD(V7M_HFSR
, FORCED
, 30, 1)
1304 FIELD(V7M_HFSR
, DEBUGEVT
, 31, 1)
1307 FIELD(V7M_DFSR
, HALTED
, 0, 1)
1308 FIELD(V7M_DFSR
, BKPT
, 1, 1)
1309 FIELD(V7M_DFSR
, DWTTRAP
, 2, 1)
1310 FIELD(V7M_DFSR
, VCATCH
, 3, 1)
1311 FIELD(V7M_DFSR
, EXTERNAL
, 4, 1)
1314 FIELD(V7M_SFSR
, INVEP
, 0, 1)
1315 FIELD(V7M_SFSR
, INVIS
, 1, 1)
1316 FIELD(V7M_SFSR
, INVER
, 2, 1)
1317 FIELD(V7M_SFSR
, AUVIOL
, 3, 1)
1318 FIELD(V7M_SFSR
, INVTRAN
, 4, 1)
1319 FIELD(V7M_SFSR
, LSPERR
, 5, 1)
1320 FIELD(V7M_SFSR
, SFARVALID
, 6, 1)
1321 FIELD(V7M_SFSR
, LSERR
, 7, 1)
1323 /* v7M MPU_CTRL bits */
1324 FIELD(V7M_MPU_CTRL
, ENABLE
, 0, 1)
1325 FIELD(V7M_MPU_CTRL
, HFNMIENA
, 1, 1)
1326 FIELD(V7M_MPU_CTRL
, PRIVDEFENA
, 2, 1)
1328 /* If adding a feature bit which corresponds to a Linux ELF
1329 * HWCAP bit, remember to update the feature-bit-to-hwcap
1330 * mapping in linux-user/elfload.c:get_elf_hwcap().
1334 ARM_FEATURE_AUXCR
, /* ARM1026 Auxiliary control register. */
1335 ARM_FEATURE_XSCALE
, /* Intel XScale extensions. */
1336 ARM_FEATURE_IWMMXT
, /* Intel iwMMXt extension. */
1341 ARM_FEATURE_PMSA
, /* no MMU; may have Memory Protection Unit */
1343 ARM_FEATURE_VFP_FP16
,
1345 ARM_FEATURE_THUMB_DIV
, /* divide supported in Thumb encoding */
1346 ARM_FEATURE_M
, /* Microcontroller profile. */
1347 ARM_FEATURE_OMAPCP
, /* OMAP specific CP15 ops handling. */
1348 ARM_FEATURE_THUMB2EE
,
1349 ARM_FEATURE_V7MP
, /* v7 Multiprocessing Extensions */
1352 ARM_FEATURE_STRONGARM
,
1353 ARM_FEATURE_VAPA
, /* cp15 VA to PA lookups */
1354 ARM_FEATURE_ARM_DIV
, /* divide supported in ARM encoding */
1355 ARM_FEATURE_VFP4
, /* VFPv4 (implies that NEON is v2) */
1356 ARM_FEATURE_GENERIC_TIMER
,
1357 ARM_FEATURE_MVFR
, /* Media and VFP Feature Registers 0 and 1 */
1358 ARM_FEATURE_DUMMY_C15_REGS
, /* RAZ/WI all of cp15 crn=15 */
1359 ARM_FEATURE_CACHE_TEST_CLEAN
, /* 926/1026 style test-and-clean ops */
1360 ARM_FEATURE_CACHE_DIRTY_REG
, /* 1136/1176 cache dirty status register */
1361 ARM_FEATURE_CACHE_BLOCK_OPS
, /* v6 optional cache block operations */
1362 ARM_FEATURE_MPIDR
, /* has cp15 MPIDR */
1363 ARM_FEATURE_PXN
, /* has Privileged Execute Never bit */
1364 ARM_FEATURE_LPAE
, /* has Large Physical Address Extension */
1366 ARM_FEATURE_AARCH64
, /* supports 64 bit mode */
1367 ARM_FEATURE_V8_AES
, /* implements AES part of v8 Crypto Extensions */
1368 ARM_FEATURE_CBAR
, /* has cp15 CBAR */
1369 ARM_FEATURE_CRC
, /* ARMv8 CRC instructions */
1370 ARM_FEATURE_CBAR_RO
, /* has cp15 CBAR and it is read-only */
1371 ARM_FEATURE_EL2
, /* has EL2 Virtualization support */
1372 ARM_FEATURE_EL3
, /* has EL3 Secure monitor support */
1373 ARM_FEATURE_V8_SHA1
, /* implements SHA1 part of v8 Crypto Extensions */
1374 ARM_FEATURE_V8_SHA256
, /* implements SHA256 part of v8 Crypto Extensions */
1375 ARM_FEATURE_V8_PMULL
, /* implements PMULL part of v8 Crypto Extensions */
1376 ARM_FEATURE_THUMB_DSP
, /* DSP insns supported in the Thumb encodings */
1377 ARM_FEATURE_PMU
, /* has PMU support */
1378 ARM_FEATURE_VBAR
, /* has cp15 VBAR */
1379 ARM_FEATURE_M_SECURITY
, /* M profile Security Extension */
1380 ARM_FEATURE_JAZELLE
, /* has (trivial) Jazelle implementation */
1381 ARM_FEATURE_SVE
, /* has Scalable Vector Extension */
1382 ARM_FEATURE_V8_SHA512
, /* implements SHA512 part of v8 Crypto Extensions */
1383 ARM_FEATURE_V8_SHA3
, /* implements SHA3 part of v8 Crypto Extensions */
1384 ARM_FEATURE_V8_SM3
, /* implements SM3 part of v8 Crypto Extensions */
1385 ARM_FEATURE_V8_SM4
, /* implements SM4 part of v8 Crypto Extensions */
1388 static inline int arm_feature(CPUARMState
*env
, int feature
)
1390 return (env
->features
& (1ULL << feature
)) != 0;
1393 #if !defined(CONFIG_USER_ONLY)
1394 /* Return true if exception levels below EL3 are in secure state,
1395 * or would be following an exception return to that level.
1396 * Unlike arm_is_secure() (which is always a question about the
1397 * _current_ state of the CPU) this doesn't care about the current
1400 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1402 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1403 return !(env
->cp15
.scr_el3
& SCR_NS
);
1405 /* If EL3 is not supported then the secure state is implementation
1406 * defined, in which case QEMU defaults to non-secure.
1412 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1413 static inline bool arm_is_el3_or_mon(CPUARMState
*env
)
1415 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1416 if (is_a64(env
) && extract32(env
->pstate
, 2, 2) == 3) {
1417 /* CPU currently in AArch64 state and EL3 */
1419 } else if (!is_a64(env
) &&
1420 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
1421 /* CPU currently in AArch32 state and monitor mode */
1428 /* Return true if the processor is in secure state */
1429 static inline bool arm_is_secure(CPUARMState
*env
)
1431 if (arm_is_el3_or_mon(env
)) {
1434 return arm_is_secure_below_el3(env
);
1438 static inline bool arm_is_secure_below_el3(CPUARMState
*env
)
1443 static inline bool arm_is_secure(CPUARMState
*env
)
1449 /* Return true if the specified exception level is running in AArch64 state. */
1450 static inline bool arm_el_is_aa64(CPUARMState
*env
, int el
)
1452 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
1453 * and if we're not in EL0 then the state of EL0 isn't well defined.)
1455 assert(el
>= 1 && el
<= 3);
1456 bool aa64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
1458 /* The highest exception level is always at the maximum supported
1459 * register width, and then lower levels have a register width controlled
1460 * by bits in the SCR or HCR registers.
1466 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1467 aa64
= aa64
&& (env
->cp15
.scr_el3
& SCR_RW
);
1474 if (arm_feature(env
, ARM_FEATURE_EL2
) && !arm_is_secure_below_el3(env
)) {
1475 aa64
= aa64
&& (env
->cp15
.hcr_el2
& HCR_RW
);
1481 /* Function for determing whether guest cp register reads and writes should
1482 * access the secure or non-secure bank of a cp register. When EL3 is
1483 * operating in AArch32 state, the NS-bit determines whether the secure
1484 * instance of a cp register should be used. When EL3 is AArch64 (or if
1485 * it doesn't exist at all) then there is no register banking, and all
1486 * accesses are to the non-secure version.
1488 static inline bool access_secure_reg(CPUARMState
*env
)
1490 bool ret
= (arm_feature(env
, ARM_FEATURE_EL3
) &&
1491 !arm_el_is_aa64(env
, 3) &&
1492 !(env
->cp15
.scr_el3
& SCR_NS
));
1497 /* Macros for accessing a specified CP register bank */
1498 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
1499 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1501 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1504 (_env)->cp15._regname##_s = (_val); \
1506 (_env)->cp15._regname##_ns = (_val); \
1510 /* Macros for automatically accessing a specific CP register bank depending on
1511 * the current secure state of the system. These macros are not intended for
1512 * supporting instruction translation reads/writes as these are dependent
1513 * solely on the SCR.NS bit and not the mode.
1515 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1516 A32_BANKED_REG_GET((_env), _regname, \
1517 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
1519 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1520 A32_BANKED_REG_SET((_env), _regname, \
1521 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
1524 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
);
1525 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
1526 uint32_t cur_el
, bool secure
);
1528 /* Interface between CPU and Interrupt controller. */
1529 #ifndef CONFIG_USER_ONLY
1530 bool armv7m_nvic_can_take_pending_exception(void *opaque
);
1532 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque
)
1538 * armv7m_nvic_set_pending: mark the specified exception as pending
1540 * @irq: the exception number to mark pending
1541 * @secure: false for non-banked exceptions or for the nonsecure
1542 * version of a banked exception, true for the secure version of a banked
1545 * Marks the specified exception as pending. Note that we will assert()
1546 * if @secure is true and @irq does not specify one of the fixed set
1547 * of architecturally banked exceptions.
1549 void armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
);
1551 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
1553 * @irq: the exception number to mark pending
1554 * @secure: false for non-banked exceptions or for the nonsecure
1555 * version of a banked exception, true for the secure version of a banked
1558 * Similar to armv7m_nvic_set_pending(), but specifically for derived
1559 * exceptions (exceptions generated in the course of trying to take
1560 * a different exception).
1562 void armv7m_nvic_set_pending_derived(void *opaque
, int irq
, bool secure
);
1564 * armv7m_nvic_get_pending_irq_info: return highest priority pending
1565 * exception, and whether it targets Secure state
1567 * @pirq: set to pending exception number
1568 * @ptargets_secure: set to whether pending exception targets Secure
1570 * This function writes the number of the highest priority pending
1571 * exception (the one which would be made active by
1572 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
1573 * to true if the current highest priority pending exception should
1574 * be taken to Secure state, false for NS.
1576 void armv7m_nvic_get_pending_irq_info(void *opaque
, int *pirq
,
1577 bool *ptargets_secure
);
1579 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
1582 * Move the current highest priority pending exception from the pending
1583 * state to the active state, and update v7m.exception to indicate that
1584 * it is the exception currently being handled.
1586 void armv7m_nvic_acknowledge_irq(void *opaque
);
1588 * armv7m_nvic_complete_irq: complete specified interrupt or exception
1590 * @irq: the exception number to complete
1591 * @secure: true if this exception was secure
1593 * Returns: -1 if the irq was not active
1594 * 1 if completing this irq brought us back to base (no active irqs)
1595 * 0 if there is still an irq active after this one was completed
1596 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
1598 int armv7m_nvic_complete_irq(void *opaque
, int irq
, bool secure
);
1600 * armv7m_nvic_raw_execution_priority: return the raw execution priority
1603 * Returns: the raw execution priority as defined by the v8M architecture.
1604 * This is the execution priority minus the effects of AIRCR.PRIS,
1605 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
1606 * (v8M ARM ARM I_PKLD.)
1608 int armv7m_nvic_raw_execution_priority(void *opaque
);
1610 * armv7m_nvic_neg_prio_requested: return true if the requested execution
1611 * priority is negative for the specified security state.
1613 * @secure: the security state to test
1614 * This corresponds to the pseudocode IsReqExecPriNeg().
1616 #ifndef CONFIG_USER_ONLY
1617 bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
);
1619 static inline bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
)
1625 /* Interface for defining coprocessor registers.
1626 * Registers are defined in tables of arm_cp_reginfo structs
1627 * which are passed to define_arm_cp_regs().
1630 /* When looking up a coprocessor register we look for it
1631 * via an integer which encodes all of:
1632 * coprocessor number
1633 * Crn, Crm, opc1, opc2 fields
1634 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1635 * or via MRRC/MCRR?)
1636 * non-secure/secure bank (AArch32 only)
1637 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1638 * (In this case crn and opc2 should be zero.)
1639 * For AArch64, there is no 32/64 bit size distinction;
1640 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1641 * and 4 bit CRn and CRm. The encoding patterns are chosen
1642 * to be easy to convert to and from the KVM encodings, and also
1643 * so that the hashtable can contain both AArch32 and AArch64
1644 * registers (to allow for interprocessing where we might run
1645 * 32 bit code on a 64 bit core).
1647 /* This bit is private to our hashtable cpreg; in KVM register
1648 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1649 * in the upper bits of the 64 bit ID.
1651 #define CP_REG_AA64_SHIFT 28
1652 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1654 /* To enable banking of coprocessor registers depending on ns-bit we
1655 * add a bit to distinguish between secure and non-secure cpregs in the
1658 #define CP_REG_NS_SHIFT 29
1659 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1661 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1662 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1663 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
1665 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1666 (CP_REG_AA64_MASK | \
1667 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1668 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1669 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1670 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1671 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1672 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1674 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
1675 * version used as a key for the coprocessor register hashtable
1677 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid
)
1679 uint32_t cpregid
= kvmid
;
1680 if ((kvmid
& CP_REG_ARCH_MASK
) == CP_REG_ARM64
) {
1681 cpregid
|= CP_REG_AA64_MASK
;
1683 if ((kvmid
& CP_REG_SIZE_MASK
) == CP_REG_SIZE_U64
) {
1684 cpregid
|= (1 << 15);
1687 /* KVM is always non-secure so add the NS flag on AArch32 register
1690 cpregid
|= 1 << CP_REG_NS_SHIFT
;
1695 /* Convert a truncated 32 bit hashtable key into the full
1696 * 64 bit KVM register ID.
1698 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid
)
1702 if (cpregid
& CP_REG_AA64_MASK
) {
1703 kvmid
= cpregid
& ~CP_REG_AA64_MASK
;
1704 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM64
;
1706 kvmid
= cpregid
& ~(1 << 15);
1707 if (cpregid
& (1 << 15)) {
1708 kvmid
|= CP_REG_SIZE_U64
| CP_REG_ARM
;
1710 kvmid
|= CP_REG_SIZE_U32
| CP_REG_ARM
;
1716 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1717 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1718 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1719 * TCG can assume the value to be constant (ie load at translate time)
1720 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1721 * indicates that the TB should not be ended after a write to this register
1722 * (the default is that the TB ends after cp writes). OVERRIDE permits
1723 * a register definition to override a previous definition for the
1724 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1725 * old must have the OVERRIDE bit set.
1726 * ALIAS indicates that this register is an alias view of some underlying
1727 * state which is also visible via another register, and that the other
1728 * register is handling migration and reset; registers marked ALIAS will not be
1729 * migrated but may have their state set by syncing of register state from KVM.
1730 * NO_RAW indicates that this register has no underlying state and does not
1731 * support raw access for state saving/loading; it will not be used for either
1732 * migration or KVM state synchronization. (Typically this is for "registers"
1733 * which are actually used as instructions for cache maintenance and so on.)
1734 * IO indicates that this register does I/O and therefore its accesses
1735 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1736 * registers which implement clocks or timers require this.
1738 #define ARM_CP_SPECIAL 1
1739 #define ARM_CP_CONST 2
1740 #define ARM_CP_64BIT 4
1741 #define ARM_CP_SUPPRESS_TB_END 8
1742 #define ARM_CP_OVERRIDE 16
1743 #define ARM_CP_ALIAS 32
1744 #define ARM_CP_IO 64
1745 #define ARM_CP_NO_RAW 128
1746 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1747 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
1748 #define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
1749 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
1750 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1751 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
1752 /* Used only as a terminator for ARMCPRegInfo lists */
1753 #define ARM_CP_SENTINEL 0xffff
1754 /* Mask of only the flag bits in a type field */
1755 #define ARM_CP_FLAG_MASK 0xff
1757 /* Valid values for ARMCPRegInfo state field, indicating which of
1758 * the AArch32 and AArch64 execution states this register is visible in.
1759 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1760 * If the reginfo is declared to be visible in both states then a second
1761 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1762 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1763 * Note that we rely on the values of these enums as we iterate through
1764 * the various states in some places.
1767 ARM_CP_STATE_AA32
= 0,
1768 ARM_CP_STATE_AA64
= 1,
1769 ARM_CP_STATE_BOTH
= 2,
1772 /* ARM CP register secure state flags. These flags identify security state
1773 * attributes for a given CP register entry.
1774 * The existence of both or neither secure and non-secure flags indicates that
1775 * the register has both a secure and non-secure hash entry. A single one of
1776 * these flags causes the register to only be hashed for the specified
1778 * Although definitions may have any combination of the S/NS bits, each
1779 * registered entry will only have one to identify whether the entry is secure
1783 ARM_CP_SECSTATE_S
= (1 << 0), /* bit[0]: Secure state register */
1784 ARM_CP_SECSTATE_NS
= (1 << 1), /* bit[1]: Non-secure state register */
1787 /* Return true if cptype is a valid type field. This is used to try to
1788 * catch errors where the sentinel has been accidentally left off the end
1789 * of a list of registers.
1791 static inline bool cptype_valid(int cptype
)
1793 return ((cptype
& ~ARM_CP_FLAG_MASK
) == 0)
1794 || ((cptype
& ARM_CP_SPECIAL
) &&
1795 ((cptype
& ~ARM_CP_FLAG_MASK
) <= ARM_LAST_SPECIAL
));
1799 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1800 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1801 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1802 * (ie any of the privileged modes in Secure state, or Monitor mode).
1803 * If a register is accessible in one privilege level it's always accessible
1804 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1805 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1806 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1807 * terminology a little and call this PL3.
1808 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1809 * with the ELx exception levels.
1811 * If access permissions for a register are more complex than can be
1812 * described with these bits, then use a laxer set of restrictions, and
1813 * do the more restrictive/complex check inside a helper function.
1817 #define PL2_R (0x20 | PL3_R)
1818 #define PL2_W (0x10 | PL3_W)
1819 #define PL1_R (0x08 | PL2_R)
1820 #define PL1_W (0x04 | PL2_W)
1821 #define PL0_R (0x02 | PL1_R)
1822 #define PL0_W (0x01 | PL1_W)
1824 #define PL3_RW (PL3_R | PL3_W)
1825 #define PL2_RW (PL2_R | PL2_W)
1826 #define PL1_RW (PL1_R | PL1_W)
1827 #define PL0_RW (PL0_R | PL0_W)
1829 /* Return the highest implemented Exception Level */
1830 static inline int arm_highest_el(CPUARMState
*env
)
1832 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1835 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
1841 /* Return true if a v7M CPU is in Handler mode */
1842 static inline bool arm_v7m_is_handler_mode(CPUARMState
*env
)
1844 return env
->v7m
.exception
!= 0;
1847 /* Return the current Exception Level (as per ARMv8; note that this differs
1848 * from the ARMv7 Privilege Level).
1850 static inline int arm_current_el(CPUARMState
*env
)
1852 if (arm_feature(env
, ARM_FEATURE_M
)) {
1853 return arm_v7m_is_handler_mode(env
) ||
1854 !(env
->v7m
.control
[env
->v7m
.secure
] & 1);
1858 return extract32(env
->pstate
, 2, 2);
1861 switch (env
->uncached_cpsr
& 0x1f) {
1862 case ARM_CPU_MODE_USR
:
1864 case ARM_CPU_MODE_HYP
:
1866 case ARM_CPU_MODE_MON
:
1869 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
1870 /* If EL3 is 32-bit then all secure privileged modes run in
1880 typedef struct ARMCPRegInfo ARMCPRegInfo
;
1882 typedef enum CPAccessResult
{
1883 /* Access is permitted */
1885 /* Access fails due to a configurable trap or enable which would
1886 * result in a categorized exception syndrome giving information about
1887 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
1888 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1889 * PL1 if in EL0, otherwise to the current EL).
1892 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1893 * Note that this is not a catch-all case -- the set of cases which may
1894 * result in this failure is specifically defined by the architecture.
1896 CP_ACCESS_TRAP_UNCATEGORIZED
= 2,
1897 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1898 CP_ACCESS_TRAP_EL2
= 3,
1899 CP_ACCESS_TRAP_EL3
= 4,
1900 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1901 CP_ACCESS_TRAP_UNCATEGORIZED_EL2
= 5,
1902 CP_ACCESS_TRAP_UNCATEGORIZED_EL3
= 6,
1903 /* Access fails and results in an exception syndrome for an FP access,
1904 * trapped directly to EL2 or EL3
1906 CP_ACCESS_TRAP_FP_EL2
= 7,
1907 CP_ACCESS_TRAP_FP_EL3
= 8,
1910 /* Access functions for coprocessor registers. These cannot fail and
1911 * may not raise exceptions.
1913 typedef uint64_t CPReadFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1914 typedef void CPWriteFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
,
1916 /* Access permission check functions for coprocessor registers. */
1917 typedef CPAccessResult
CPAccessFn(CPUARMState
*env
,
1918 const ARMCPRegInfo
*opaque
,
1920 /* Hook function for register reset */
1921 typedef void CPResetFn(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
1925 /* Definition of an ARM coprocessor register */
1926 struct ARMCPRegInfo
{
1927 /* Name of register (useful mainly for debugging, need not be unique) */
1929 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1930 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1931 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1932 * will be decoded to this register. The register read and write
1933 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1934 * used by the program, so it is possible to register a wildcard and
1935 * then behave differently on read/write if necessary.
1936 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1937 * must both be zero.
1938 * For AArch64-visible registers, opc0 is also used.
1939 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1940 * way to distinguish (for KVM's benefit) guest-visible system registers
1941 * from demuxed ones provided to preserve the "no side effects on
1942 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1943 * visible (to match KVM's encoding); cp==0 will be converted to
1944 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
1952 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1954 /* Register type: ARM_CP_* bits/values */
1956 /* Access rights: PL*_[RW] */
1958 /* Security state: ARM_CP_SECSTATE_* bits/values */
1960 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1961 * this register was defined: can be used to hand data through to the
1962 * register read/write functions, since they are passed the ARMCPRegInfo*.
1965 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1966 * fieldoffset is non-zero, the reset value of the register.
1968 uint64_t resetvalue
;
1969 /* Offset of the field in CPUARMState for this register.
1971 * This is not needed if either:
1972 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1973 * 2. both readfn and writefn are specified
1975 ptrdiff_t fieldoffset
; /* offsetof(CPUARMState, field) */
1977 /* Offsets of the secure and non-secure fields in CPUARMState for the
1978 * register if it is banked. These fields are only used during the static
1979 * registration of a register. During hashing the bank associated
1980 * with a given security state is copied to fieldoffset which is used from
1983 * It is expected that register definitions use either fieldoffset or
1984 * bank_fieldoffsets in the definition but not both. It is also expected
1985 * that both bank offsets are set when defining a banked register. This
1986 * use indicates that a register is banked.
1988 ptrdiff_t bank_fieldoffsets
[2];
1990 /* Function for making any access checks for this register in addition to
1991 * those specified by the 'access' permissions bits. If NULL, no extra
1992 * checks required. The access check is performed at runtime, not at
1995 CPAccessFn
*accessfn
;
1996 /* Function for handling reads of this register. If NULL, then reads
1997 * will be done by loading from the offset into CPUARMState specified
2001 /* Function for handling writes of this register. If NULL, then writes
2002 * will be done by writing to the offset into CPUARMState specified
2006 /* Function for doing a "raw" read; used when we need to copy
2007 * coprocessor state to the kernel for KVM or out for
2008 * migration. This only needs to be provided if there is also a
2009 * readfn and it has side effects (for instance clear-on-read bits).
2011 CPReadFn
*raw_readfn
;
2012 /* Function for doing a "raw" write; used when we need to copy KVM
2013 * kernel coprocessor state into userspace, or for inbound
2014 * migration. This only needs to be provided if there is also a
2015 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2016 * or similar behaviour.
2018 CPWriteFn
*raw_writefn
;
2019 /* Function for resetting the register. If NULL, then reset will be done
2020 * by writing resetvalue to the field specified in fieldoffset. If
2021 * fieldoffset is 0 then no reset will be done.
2026 /* Macros which are lvalues for the field in CPUARMState for the
2029 #define CPREG_FIELD32(env, ri) \
2030 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2031 #define CPREG_FIELD64(env, ri) \
2032 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2034 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2036 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
2037 const ARMCPRegInfo
*regs
, void *opaque
);
2038 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
2039 const ARMCPRegInfo
*regs
, void *opaque
);
2040 static inline void define_arm_cp_regs(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
2042 define_arm_cp_regs_with_opaque(cpu
, regs
, 0);
2044 static inline void define_one_arm_cp_reg(ARMCPU
*cpu
, const ARMCPRegInfo
*regs
)
2046 define_one_arm_cp_reg_with_opaque(cpu
, regs
, 0);
2048 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
);
2050 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2051 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2053 /* CPReadFn that can be used for read-as-zero behaviour */
2054 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
2056 /* CPResetFn that does nothing, for use if no reset is required even
2057 * if fieldoffset is non zero.
2059 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
);
2061 /* Return true if this reginfo struct's field in the cpu state struct
2064 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo
*ri
)
2066 return (ri
->state
== ARM_CP_STATE_AA64
) || (ri
->type
& ARM_CP_64BIT
);
2069 static inline bool cp_access_ok(int current_el
,
2070 const ARMCPRegInfo
*ri
, int isread
)
2072 return (ri
->access
>> ((current_el
* 2) + isread
)) & 1;
2075 /* Raw read of a coprocessor register (as needed for migration, etc) */
2076 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
);
2079 * write_list_to_cpustate
2082 * For each register listed in the ARMCPU cpreg_indexes list, write
2083 * its value from the cpreg_values list into the ARMCPUState structure.
2084 * This updates TCG's working data structures from KVM data or
2085 * from incoming migration state.
2087 * Returns: true if all register values were updated correctly,
2088 * false if some register was unknown or could not be written.
2089 * Note that we do not stop early on failure -- we will attempt
2090 * writing all registers in the list.
2092 bool write_list_to_cpustate(ARMCPU
*cpu
);
2095 * write_cpustate_to_list:
2098 * For each register listed in the ARMCPU cpreg_indexes list, write
2099 * its value from the ARMCPUState structure into the cpreg_values list.
2100 * This is used to copy info from TCG's working data structures into
2101 * KVM or for outbound migration.
2103 * Returns: true if all register values were read correctly,
2104 * false if some register was unknown or could not be read.
2105 * Note that we do not stop early on failure -- we will attempt
2106 * reading all registers in the list.
2108 bool write_cpustate_to_list(ARMCPU
*cpu
);
2110 #define ARM_CPUID_TI915T 0x54029152
2111 #define ARM_CPUID_TI925T 0x54029252
2113 #if defined(CONFIG_USER_ONLY)
2114 #define TARGET_PAGE_BITS 12
2116 /* ARMv7 and later CPUs have 4K pages minimum, but ARMv5 and v6
2117 * have to support 1K tiny pages.
2119 #define TARGET_PAGE_BITS_VARY
2120 #define TARGET_PAGE_BITS_MIN 10
2123 #if defined(TARGET_AARCH64)
2124 # define TARGET_PHYS_ADDR_SPACE_BITS 48
2125 # define TARGET_VIRT_ADDR_SPACE_BITS 64
2127 # define TARGET_PHYS_ADDR_SPACE_BITS 40
2128 # define TARGET_VIRT_ADDR_SPACE_BITS 32
2131 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
2132 unsigned int target_el
)
2134 CPUARMState
*env
= cs
->env_ptr
;
2135 unsigned int cur_el
= arm_current_el(env
);
2136 bool secure
= arm_is_secure(env
);
2137 bool pstate_unmasked
;
2138 int8_t unmasked
= 0;
2140 /* Don't take exceptions if they target a lower EL.
2141 * This check should catch any exceptions that would not be taken but left
2144 if (cur_el
> target_el
) {
2150 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
2154 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
2158 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_FMO
)) {
2159 /* VFIQs are only taken when hypervized and non-secure. */
2162 return !(env
->daif
& PSTATE_F
);
2164 if (secure
|| !(env
->cp15
.hcr_el2
& HCR_IMO
)) {
2165 /* VIRQs are only taken when hypervized and non-secure. */
2168 return !(env
->daif
& PSTATE_I
);
2170 g_assert_not_reached();
2173 /* Use the target EL, current execution state and SCR/HCR settings to
2174 * determine whether the corresponding CPSR bit is used to mask the
2177 if ((target_el
> cur_el
) && (target_el
!= 1)) {
2178 /* Exceptions targeting a higher EL may not be maskable */
2179 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2180 /* 64-bit masking rules are simple: exceptions to EL3
2181 * can't be masked, and exceptions to EL2 can only be
2182 * masked from Secure state. The HCR and SCR settings
2183 * don't affect the masking logic, only the interrupt routing.
2185 if (target_el
== 3 || !secure
) {
2189 /* The old 32-bit-only environment has a more complicated
2190 * masking setup. HCR and SCR bits not only affect interrupt
2191 * routing but also change the behaviour of masking.
2197 /* If FIQs are routed to EL3 or EL2 then there are cases where
2198 * we override the CPSR.F in determining if the exception is
2199 * masked or not. If neither of these are set then we fall back
2200 * to the CPSR.F setting otherwise we further assess the state
2203 hcr
= (env
->cp15
.hcr_el2
& HCR_FMO
);
2204 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
2206 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
2207 * CPSR.F bit masks FIQ interrupts when taken in non-secure
2208 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
2209 * when non-secure but only when FIQs are only routed to EL3.
2211 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
2214 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
2215 * we may override the CPSR.I masking when in non-secure state.
2216 * The SCR.IRQ setting has already been taken into consideration
2217 * when setting the target EL, so it does not have a further
2220 hcr
= (env
->cp15
.hcr_el2
& HCR_IMO
);
2224 g_assert_not_reached();
2227 if ((scr
|| hcr
) && !secure
) {
2233 /* The PSTATE bits only mask the interrupt if we have not overriden the
2236 return unmasked
|| pstate_unmasked
;
2239 #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)
2241 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2242 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2244 #define cpu_signal_handler cpu_arm_signal_handler
2245 #define cpu_list arm_cpu_list
2247 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2250 * + NonSecure EL1 & 0 stage 1
2251 * + NonSecure EL1 & 0 stage 2
2253 * + Secure EL1 & EL0
2256 * + NonSecure PL1 & 0 stage 1
2257 * + NonSecure PL1 & 0 stage 2
2259 * + Secure PL0 & PL1
2260 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2262 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2263 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
2264 * may differ in access permissions even if the VA->PA map is the same
2265 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2266 * translation, which means that we have one mmu_idx that deals with two
2267 * concatenated translation regimes [this sort of combined s1+2 TLB is
2268 * architecturally permitted]
2269 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2270 * handling via the TLB. The only way to do a stage 1 translation without
2271 * the immediate stage 2 translation is via the ATS or AT system insns,
2272 * which can be slow-pathed and always do a page table walk.
2273 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2274 * translation regimes, because they map reasonably well to each other
2275 * and they can't both be active at the same time.
2276 * This gives us the following list of mmu_idx values:
2278 * NS EL0 (aka NS PL0) stage 1+2
2279 * NS EL1 (aka NS PL1) stage 1+2
2280 * NS EL2 (aka NS PL2)
2283 * S EL1 (not used if EL3 is 32 bit)
2286 * (The last of these is an mmu_idx because we want to be able to use the TLB
2287 * for the accesses done as part of a stage 1 page table walk, rather than
2288 * having to walk the stage 2 page table over and over.)
2290 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2291 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2292 * NS EL2 if we ever model a Cortex-R52).
2294 * M profile CPUs are rather different as they do not have a true MMU.
2295 * They have the following different MMU indexes:
2298 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2299 * Privileged, execution priority negative (ditto)
2300 * If the CPU supports the v8M Security Extension then there are also:
2303 * Secure User, execution priority negative
2304 * Secure Privileged, execution priority negative
2306 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2307 * are not quite the same -- different CPU types (most notably M profile
2308 * vs A/R profile) would like to use MMU indexes with different semantics,
2309 * but since we don't ever need to use all of those in a single CPU we
2310 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
2311 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2312 * the same for any particular CPU.
2313 * Variables of type ARMMUIdx are always full values, and the core
2314 * index values are in variables of type 'int'.
2316 * Our enumeration includes at the end some entries which are not "true"
2317 * mmu_idx values in that they don't have corresponding TLBs and are only
2318 * valid for doing slow path page table walks.
2320 * The constant names here are patterned after the general style of the names
2321 * of the AT/ATS operations.
2322 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2323 * For M profile we arrange them to have a bit for priv, a bit for negpri
2324 * and a bit for secure.
2326 #define ARM_MMU_IDX_A 0x10 /* A profile */
2327 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2328 #define ARM_MMU_IDX_M 0x40 /* M profile */
2330 /* meanings of the bits for M profile mmu idx values */
2331 #define ARM_MMU_IDX_M_PRIV 0x1
2332 #define ARM_MMU_IDX_M_NEGPRI 0x2
2333 #define ARM_MMU_IDX_M_S 0x4
2335 #define ARM_MMU_IDX_TYPE_MASK (~0x7)
2336 #define ARM_MMU_IDX_COREIDX_MASK 0x7
2338 typedef enum ARMMMUIdx
{
2339 ARMMMUIdx_S12NSE0
= 0 | ARM_MMU_IDX_A
,
2340 ARMMMUIdx_S12NSE1
= 1 | ARM_MMU_IDX_A
,
2341 ARMMMUIdx_S1E2
= 2 | ARM_MMU_IDX_A
,
2342 ARMMMUIdx_S1E3
= 3 | ARM_MMU_IDX_A
,
2343 ARMMMUIdx_S1SE0
= 4 | ARM_MMU_IDX_A
,
2344 ARMMMUIdx_S1SE1
= 5 | ARM_MMU_IDX_A
,
2345 ARMMMUIdx_S2NS
= 6 | ARM_MMU_IDX_A
,
2346 ARMMMUIdx_MUser
= 0 | ARM_MMU_IDX_M
,
2347 ARMMMUIdx_MPriv
= 1 | ARM_MMU_IDX_M
,
2348 ARMMMUIdx_MUserNegPri
= 2 | ARM_MMU_IDX_M
,
2349 ARMMMUIdx_MPrivNegPri
= 3 | ARM_MMU_IDX_M
,
2350 ARMMMUIdx_MSUser
= 4 | ARM_MMU_IDX_M
,
2351 ARMMMUIdx_MSPriv
= 5 | ARM_MMU_IDX_M
,
2352 ARMMMUIdx_MSUserNegPri
= 6 | ARM_MMU_IDX_M
,
2353 ARMMMUIdx_MSPrivNegPri
= 7 | ARM_MMU_IDX_M
,
2354 /* Indexes below here don't have TLBs and are used only for AT system
2355 * instructions or for the first stage of an S12 page table walk.
2357 ARMMMUIdx_S1NSE0
= 0 | ARM_MMU_IDX_NOTLB
,
2358 ARMMMUIdx_S1NSE1
= 1 | ARM_MMU_IDX_NOTLB
,
2361 /* Bit macros for the core-mmu-index values for each index,
2362 * for use when calling tlb_flush_by_mmuidx() and friends.
2364 typedef enum ARMMMUIdxBit
{
2365 ARMMMUIdxBit_S12NSE0
= 1 << 0,
2366 ARMMMUIdxBit_S12NSE1
= 1 << 1,
2367 ARMMMUIdxBit_S1E2
= 1 << 2,
2368 ARMMMUIdxBit_S1E3
= 1 << 3,
2369 ARMMMUIdxBit_S1SE0
= 1 << 4,
2370 ARMMMUIdxBit_S1SE1
= 1 << 5,
2371 ARMMMUIdxBit_S2NS
= 1 << 6,
2372 ARMMMUIdxBit_MUser
= 1 << 0,
2373 ARMMMUIdxBit_MPriv
= 1 << 1,
2374 ARMMMUIdxBit_MUserNegPri
= 1 << 2,
2375 ARMMMUIdxBit_MPrivNegPri
= 1 << 3,
2376 ARMMMUIdxBit_MSUser
= 1 << 4,
2377 ARMMMUIdxBit_MSPriv
= 1 << 5,
2378 ARMMMUIdxBit_MSUserNegPri
= 1 << 6,
2379 ARMMMUIdxBit_MSPrivNegPri
= 1 << 7,
2382 #define MMU_USER_IDX 0
2384 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx
)
2386 return mmu_idx
& ARM_MMU_IDX_COREIDX_MASK
;
2389 static inline ARMMMUIdx
core_to_arm_mmu_idx(CPUARMState
*env
, int mmu_idx
)
2391 if (arm_feature(env
, ARM_FEATURE_M
)) {
2392 return mmu_idx
| ARM_MMU_IDX_M
;
2394 return mmu_idx
| ARM_MMU_IDX_A
;
2398 /* Return the exception level we're running at if this is our mmu_idx */
2399 static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
)
2401 switch (mmu_idx
& ARM_MMU_IDX_TYPE_MASK
) {
2405 return mmu_idx
& ARM_MMU_IDX_M_PRIV
;
2407 g_assert_not_reached();
2411 /* Return the MMU index for a v7M CPU in the specified security and
2414 static inline ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
2418 ARMMMUIdx mmu_idx
= ARM_MMU_IDX_M
;
2421 mmu_idx
|= ARM_MMU_IDX_M_PRIV
;
2424 if (armv7m_nvic_neg_prio_requested(env
->nvic
, secstate
)) {
2425 mmu_idx
|= ARM_MMU_IDX_M_NEGPRI
;
2429 mmu_idx
|= ARM_MMU_IDX_M_S
;
2435 /* Return the MMU index for a v7M CPU in the specified security state */
2436 static inline ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
,
2439 bool priv
= arm_current_el(env
) != 0;
2441 return arm_v7m_mmu_idx_for_secstate_and_priv(env
, secstate
, priv
);
2444 /* Determine the current mmu_idx to use for normal loads/stores */
2445 static inline int cpu_mmu_index(CPUARMState
*env
, bool ifetch
)
2447 int el
= arm_current_el(env
);
2449 if (arm_feature(env
, ARM_FEATURE_M
)) {
2450 ARMMMUIdx mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, env
->v7m
.secure
);
2452 return arm_to_core_mmu_idx(mmu_idx
);
2455 if (el
< 2 && arm_is_secure_below_el3(env
)) {
2456 return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0
+ el
);
2461 /* Indexes used when registering address spaces with cpu_address_space_init */
2462 typedef enum ARMASIdx
{
2467 /* Return the Exception Level targeted by debug exceptions. */
2468 static inline int arm_debug_target_el(CPUARMState
*env
)
2470 bool secure
= arm_is_secure(env
);
2471 bool route_to_el2
= false;
2473 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
) {
2474 route_to_el2
= env
->cp15
.hcr_el2
& HCR_TGE
||
2475 env
->cp15
.mdcr_el2
& (1 << 8);
2480 } else if (arm_feature(env
, ARM_FEATURE_EL3
) &&
2481 !arm_el_is_aa64(env
, 3) && secure
) {
2488 static inline bool aa64_generate_debug_exceptions(CPUARMState
*env
)
2490 if (arm_is_secure(env
)) {
2491 /* MDCR_EL3.SDD disables debug events from Secure state */
2492 if (extract32(env
->cp15
.mdcr_el3
, 16, 1) != 0
2493 || arm_current_el(env
) == 3) {
2498 if (arm_current_el(env
) == arm_debug_target_el(env
)) {
2499 if ((extract32(env
->cp15
.mdscr_el1
, 13, 1) == 0)
2500 || (env
->daif
& PSTATE_D
)) {
2507 static inline bool aa32_generate_debug_exceptions(CPUARMState
*env
)
2509 int el
= arm_current_el(env
);
2511 if (el
== 0 && arm_el_is_aa64(env
, 1)) {
2512 return aa64_generate_debug_exceptions(env
);
2515 if (arm_is_secure(env
)) {
2518 if (el
== 0 && (env
->cp15
.sder
& 1)) {
2519 /* SDER.SUIDEN means debug exceptions from Secure EL0
2520 * are always enabled. Otherwise they are controlled by
2521 * SDCR.SPD like those from other Secure ELs.
2526 spd
= extract32(env
->cp15
.mdcr_el3
, 14, 2);
2529 /* SPD == 0b01 is reserved, but behaves as 0b00. */
2531 /* For 0b00 we return true if external secure invasive debug
2532 * is enabled. On real hardware this is controlled by external
2533 * signals to the core. QEMU always permits debug, and behaves
2534 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
2547 /* Return true if debugging exceptions are currently enabled.
2548 * This corresponds to what in ARM ARM pseudocode would be
2549 * if UsingAArch32() then
2550 * return AArch32.GenerateDebugExceptions()
2552 * return AArch64.GenerateDebugExceptions()
2553 * We choose to push the if() down into this function for clarity,
2554 * since the pseudocode has it at all callsites except for the one in
2555 * CheckSoftwareStep(), where it is elided because both branches would
2556 * always return the same value.
2558 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
2559 * don't yet implement those exception levels or their associated trap bits.
2561 static inline bool arm_generate_debug_exceptions(CPUARMState
*env
)
2564 return aa64_generate_debug_exceptions(env
);
2566 return aa32_generate_debug_exceptions(env
);
2570 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
2571 * implicitly means this always returns false in pre-v8 CPUs.)
2573 static inline bool arm_singlestep_active(CPUARMState
*env
)
2575 return extract32(env
->cp15
.mdscr_el1
, 0, 1)
2576 && arm_el_is_aa64(env
, arm_debug_target_el(env
))
2577 && arm_generate_debug_exceptions(env
);
2580 static inline bool arm_sctlr_b(CPUARMState
*env
)
2583 /* We need not implement SCTLR.ITD in user-mode emulation, so
2584 * let linux-user ignore the fact that it conflicts with SCTLR_B.
2585 * This lets people run BE32 binaries with "-cpu any".
2587 #ifndef CONFIG_USER_ONLY
2588 !arm_feature(env
, ARM_FEATURE_V7
) &&
2590 (env
->cp15
.sctlr_el
[1] & SCTLR_B
) != 0;
2593 /* Return true if the processor is in big-endian mode. */
2594 static inline bool arm_cpu_data_is_big_endian(CPUARMState
*env
)
2598 /* In 32bit endianness is determined by looking at CPSR's E bit */
2601 #ifdef CONFIG_USER_ONLY
2602 /* In system mode, BE32 is modelled in line with the
2603 * architecture (as word-invariant big-endianness), where loads
2604 * and stores are done little endian but from addresses which
2605 * are adjusted by XORing with the appropriate constant. So the
2606 * endianness to use for the raw data access is not affected by
2608 * In user mode, however, we model BE32 as byte-invariant
2609 * big-endianness (because user-only code cannot tell the
2610 * difference), and so we need to use a data access endianness
2611 * that depends on SCTLR.B.
2615 ((env
->uncached_cpsr
& CPSR_E
) ? 1 : 0);
2618 cur_el
= arm_current_el(env
);
2621 return (env
->cp15
.sctlr_el
[1] & SCTLR_E0E
) != 0;
2624 return (env
->cp15
.sctlr_el
[cur_el
] & SCTLR_EE
) != 0;
2627 #include "exec/cpu-all.h"
2629 /* Bit usage in the TB flags field: bit 31 indicates whether we are
2630 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
2631 * We put flags which are shared between 32 and 64 bit mode at the top
2632 * of the word, and flags which apply to only one mode at the bottom.
2634 #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
2635 #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
2636 #define ARM_TBFLAG_MMUIDX_SHIFT 28
2637 #define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
2638 #define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
2639 #define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
2640 #define ARM_TBFLAG_PSTATE_SS_SHIFT 26
2641 #define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
2642 /* Target EL if we take a floating-point-disabled exception */
2643 #define ARM_TBFLAG_FPEXC_EL_SHIFT 24
2644 #define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
2646 /* Bit usage when in AArch32 state: */
2647 #define ARM_TBFLAG_THUMB_SHIFT 0
2648 #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
2649 #define ARM_TBFLAG_VECLEN_SHIFT 1
2650 #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
2651 #define ARM_TBFLAG_VECSTRIDE_SHIFT 4
2652 #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
2653 #define ARM_TBFLAG_VFPEN_SHIFT 7
2654 #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
2655 #define ARM_TBFLAG_CONDEXEC_SHIFT 8
2656 #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
2657 #define ARM_TBFLAG_SCTLR_B_SHIFT 16
2658 #define ARM_TBFLAG_SCTLR_B_MASK (1 << ARM_TBFLAG_SCTLR_B_SHIFT)
2659 /* We store the bottom two bits of the CPAR as TB flags and handle
2660 * checks on the other bits at runtime
2662 #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
2663 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2664 /* Indicates whether cp register reads and writes by guest code should access
2665 * the secure or nonsecure bank of banked registers; note that this is not
2666 * the same thing as the current security state of the processor!
2668 #define ARM_TBFLAG_NS_SHIFT 19
2669 #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
2670 #define ARM_TBFLAG_BE_DATA_SHIFT 20
2671 #define ARM_TBFLAG_BE_DATA_MASK (1 << ARM_TBFLAG_BE_DATA_SHIFT)
2672 /* For M profile only, Handler (ie not Thread) mode */
2673 #define ARM_TBFLAG_HANDLER_SHIFT 21
2674 #define ARM_TBFLAG_HANDLER_MASK (1 << ARM_TBFLAG_HANDLER_SHIFT)
2676 /* Bit usage when in AArch64 state */
2677 #define ARM_TBFLAG_TBI0_SHIFT 0 /* TBI0 for EL0/1 or TBI for EL2/3 */
2678 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
2679 #define ARM_TBFLAG_TBI1_SHIFT 1 /* TBI1 for EL0/1 */
2680 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
2682 /* some convenience accessor macros */
2683 #define ARM_TBFLAG_AARCH64_STATE(F) \
2684 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
2685 #define ARM_TBFLAG_MMUIDX(F) \
2686 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
2687 #define ARM_TBFLAG_SS_ACTIVE(F) \
2688 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
2689 #define ARM_TBFLAG_PSTATE_SS(F) \
2690 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
2691 #define ARM_TBFLAG_FPEXC_EL(F) \
2692 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
2693 #define ARM_TBFLAG_THUMB(F) \
2694 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
2695 #define ARM_TBFLAG_VECLEN(F) \
2696 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
2697 #define ARM_TBFLAG_VECSTRIDE(F) \
2698 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
2699 #define ARM_TBFLAG_VFPEN(F) \
2700 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
2701 #define ARM_TBFLAG_CONDEXEC(F) \
2702 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
2703 #define ARM_TBFLAG_SCTLR_B(F) \
2704 (((F) & ARM_TBFLAG_SCTLR_B_MASK) >> ARM_TBFLAG_SCTLR_B_SHIFT)
2705 #define ARM_TBFLAG_XSCALE_CPAR(F) \
2706 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
2707 #define ARM_TBFLAG_NS(F) \
2708 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
2709 #define ARM_TBFLAG_BE_DATA(F) \
2710 (((F) & ARM_TBFLAG_BE_DATA_MASK) >> ARM_TBFLAG_BE_DATA_SHIFT)
2711 #define ARM_TBFLAG_HANDLER(F) \
2712 (((F) & ARM_TBFLAG_HANDLER_MASK) >> ARM_TBFLAG_HANDLER_SHIFT)
2713 #define ARM_TBFLAG_TBI0(F) \
2714 (((F) & ARM_TBFLAG_TBI0_MASK) >> ARM_TBFLAG_TBI0_SHIFT)
2715 #define ARM_TBFLAG_TBI1(F) \
2716 (((F) & ARM_TBFLAG_TBI1_MASK) >> ARM_TBFLAG_TBI1_SHIFT)
2718 static inline bool bswap_code(bool sctlr_b
)
2720 #ifdef CONFIG_USER_ONLY
2721 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
2722 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
2723 * would also end up as a mixed-endian mode with BE code, LE data.
2726 #ifdef TARGET_WORDS_BIGENDIAN
2731 /* All code access in ARM is little endian, and there are no loaders
2732 * doing swaps that need to be reversed
2738 #ifdef CONFIG_USER_ONLY
2739 static inline bool arm_cpu_bswap_data(CPUARMState
*env
)
2742 #ifdef TARGET_WORDS_BIGENDIAN
2745 arm_cpu_data_is_big_endian(env
);
2749 #ifndef CONFIG_USER_ONLY
2753 * @mmu_idx: MMU index indicating required translation regime
2755 * Extracts the TBI0 value from the appropriate TCR for the current EL
2757 * Returns: the TBI0 value.
2759 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2764 * @mmu_idx: MMU index indicating required translation regime
2766 * Extracts the TBI1 value from the appropriate TCR for the current EL
2768 * Returns: the TBI1 value.
2770 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
2772 /* We can't handle tagged addresses properly in user-only mode */
2773 static inline uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2778 static inline uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
2784 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
2785 target_ulong
*cs_base
, uint32_t *flags
);
2788 QEMU_PSCI_CONDUIT_DISABLED
= 0,
2789 QEMU_PSCI_CONDUIT_SMC
= 1,
2790 QEMU_PSCI_CONDUIT_HVC
= 2,
2793 #ifndef CONFIG_USER_ONLY
2794 /* Return the address space index to use for a memory access */
2795 static inline int arm_asidx_from_attrs(CPUState
*cs
, MemTxAttrs attrs
)
2797 return attrs
.secure
? ARMASIdx_S
: ARMASIdx_NS
;
2800 /* Return the AddressSpace to use for a memory access
2801 * (which depends on whether the access is S or NS, and whether
2802 * the board gave us a separate AddressSpace for S accesses).
2804 static inline AddressSpace
*arm_addressspace(CPUState
*cs
, MemTxAttrs attrs
)
2806 return cpu_get_address_space(cs
, arm_asidx_from_attrs(cs
, attrs
));
2811 * arm_register_el_change_hook:
2812 * Register a hook function which will be called back whenever this
2813 * CPU changes exception level or mode. The hook function will be
2814 * passed a pointer to the ARMCPU and the opaque data pointer passed
2815 * to this function when the hook was registered.
2817 * Note that we currently only support registering a single hook function,
2818 * and will assert if this function is called twice.
2819 * This facility is intended for the use of the GICv3 emulation.
2821 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
2825 * arm_get_el_change_hook_opaque:
2826 * Return the opaque data that will be used by the el_change_hook
2829 static inline void *arm_get_el_change_hook_opaque(ARMCPU
*cpu
)
2831 return cpu
->el_change_hook_opaque
;
2836 * Return a pointer to the Dn register within env in 32-bit mode.
2838 static inline uint64_t *aa32_vfp_dreg(CPUARMState
*env
, unsigned regno
)
2840 return &env
->vfp
.zregs
[regno
>> 1].d
[regno
& 1];
2845 * Return a pointer to the Qn register within env in 32-bit mode.
2847 static inline uint64_t *aa32_vfp_qreg(CPUARMState
*env
, unsigned regno
)
2849 return &env
->vfp
.zregs
[regno
].d
[0];
2854 * Return a pointer to the Qn register within env in 64-bit mode.
2856 static inline uint64_t *aa64_vfp_qreg(CPUARMState
*env
, unsigned regno
)
2858 return &env
->vfp
.zregs
[regno
].d
[0];