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Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-sev' into staging
[qemu.git] / target / i386 / kvm.c
blobd23fff12f5fd5e1df2db7e1a1cc19e2e4d134b15
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94 static bool has_msr_spec_ctrl;
95 static bool has_msr_smi_count;
96
97 static uint32_t has_architectural_pmu_version;
98 static uint32_t num_architectural_pmu_gp_counters;
99 static uint32_t num_architectural_pmu_fixed_counters;
100
101 static int has_xsave;
102 static int has_xcrs;
103 static int has_pit_state2;
104
105 static bool has_msr_mcg_ext_ctl;
106
107 static struct kvm_cpuid2 *cpuid_cache;
108
109 int kvm_has_pit_state2(void)
110 {
111 return has_pit_state2;
112 }
113
114 bool kvm_has_smm(void)
115 {
116 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
117 }
118
119 bool kvm_has_adjust_clock_stable(void)
120 {
121 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
122
123 return (ret == KVM_CLOCK_TSC_STABLE);
124 }
125
126 bool kvm_allows_irq0_override(void)
127 {
128 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
129 }
130
131 static bool kvm_x2apic_api_set_flags(uint64_t flags)
132 {
133 KVMState *s = KVM_STATE(current_machine->accelerator);
134
135 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
136 }
137
138 #define MEMORIZE(fn, _result) \
139 ({ \
140 static bool _memorized; \
141 \
142 if (_memorized) { \
143 return _result; \
144 } \
145 _memorized = true; \
146 _result = fn; \
147 })
148
149 static bool has_x2apic_api;
150
151 bool kvm_has_x2apic_api(void)
152 {
153 return has_x2apic_api;
154 }
155
156 bool kvm_enable_x2apic(void)
157 {
158 return MEMORIZE(
159 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
160 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
161 has_x2apic_api);
162 }
163
164 static int kvm_get_tsc(CPUState *cs)
165 {
166 X86CPU *cpu = X86_CPU(cs);
167 CPUX86State *env = &cpu->env;
168 struct {
169 struct kvm_msrs info;
170 struct kvm_msr_entry entries[1];
171 } msr_data;
172 int ret;
173
174 if (env->tsc_valid) {
175 return 0;
176 }
177
178 msr_data.info.nmsrs = 1;
179 msr_data.entries[0].index = MSR_IA32_TSC;
180 env->tsc_valid = !runstate_is_running();
181
182 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
183 if (ret < 0) {
184 return ret;
185 }
186
187 assert(ret == 1);
188 env->tsc = msr_data.entries[0].data;
189 return 0;
190 }
191
192 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
193 {
194 kvm_get_tsc(cpu);
195 }
196
197 void kvm_synchronize_all_tsc(void)
198 {
199 CPUState *cpu;
200
201 if (kvm_enabled()) {
202 CPU_FOREACH(cpu) {
203 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
204 }
205 }
206 }
207
208 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
209 {
210 struct kvm_cpuid2 *cpuid;
211 int r, size;
212
213 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
214 cpuid = g_malloc0(size);
215 cpuid->nent = max;
216 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
217 if (r == 0 && cpuid->nent >= max) {
218 r = -E2BIG;
219 }
220 if (r < 0) {
221 if (r == -E2BIG) {
222 g_free(cpuid);
223 return NULL;
224 } else {
225 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
226 strerror(-r));
227 exit(1);
228 }
229 }
230 return cpuid;
231 }
232
233 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
234 * for all entries.
235 */
236 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
237 {
238 struct kvm_cpuid2 *cpuid;
239 int max = 1;
240
241 if (cpuid_cache != NULL) {
242 return cpuid_cache;
243 }
244 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
245 max *= 2;
246 }
247 cpuid_cache = cpuid;
248 return cpuid;
249 }
250
251 static const struct kvm_para_features {
252 int cap;
253 int feature;
254 } para_features[] = {
255 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
256 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
257 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
258 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
259 };
260
261 static int get_para_features(KVMState *s)
262 {
263 int i, features = 0;
264
265 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
266 if (kvm_check_extension(s, para_features[i].cap)) {
267 features |= (1 << para_features[i].feature);
268 }
269 }
270
271 return features;
272 }
273
274 static bool host_tsx_blacklisted(void)
275 {
276 int family, model, stepping;\
277 char vendor[CPUID_VENDOR_SZ + 1];
278
279 host_vendor_fms(vendor, &family, &model, &stepping);
280
281 /* Check if we are running on a Haswell host known to have broken TSX */
282 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
283 (family == 6) &&
284 ((model == 63 && stepping < 4) ||
285 model == 60 || model == 69 || model == 70);
286 }
287
288 /* Returns the value for a specific register on the cpuid entry
289 */
290 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
291 {
292 uint32_t ret = 0;
293 switch (reg) {
294 case R_EAX:
295 ret = entry->eax;
296 break;
297 case R_EBX:
298 ret = entry->ebx;
299 break;
300 case R_ECX:
301 ret = entry->ecx;
302 break;
303 case R_EDX:
304 ret = entry->edx;
305 break;
306 }
307 return ret;
308 }
309
310 /* Find matching entry for function/index on kvm_cpuid2 struct
311 */
312 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
313 uint32_t function,
314 uint32_t index)
315 {
316 int i;
317 for (i = 0; i < cpuid->nent; ++i) {
318 if (cpuid->entries[i].function == function &&
319 cpuid->entries[i].index == index) {
320 return &cpuid->entries[i];
321 }
322 }
323 /* not found: */
324 return NULL;
325 }
326
327 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
328 uint32_t index, int reg)
329 {
330 struct kvm_cpuid2 *cpuid;
331 uint32_t ret = 0;
332 uint32_t cpuid_1_edx;
333 bool found = false;
334
335 cpuid = get_supported_cpuid(s);
336
337 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
338 if (entry) {
339 found = true;
340 ret = cpuid_entry_get_reg(entry, reg);
341 }
342
343 /* Fixups for the data returned by KVM, below */
344
345 if (function == 1 && reg == R_EDX) {
346 /* KVM before 2.6.30 misreports the following features */
347 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
348 } else if (function == 1 && reg == R_ECX) {
349 /* We can set the hypervisor flag, even if KVM does not return it on
350 * GET_SUPPORTED_CPUID
351 */
352 ret |= CPUID_EXT_HYPERVISOR;
353 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
354 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
355 * and the irqchip is in the kernel.
356 */
357 if (kvm_irqchip_in_kernel() &&
358 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
359 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
360 }
361
362 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
363 * without the in-kernel irqchip
364 */
365 if (!kvm_irqchip_in_kernel()) {
366 ret &= ~CPUID_EXT_X2APIC;
367 }
368 } else if (function == 6 && reg == R_EAX) {
369 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
370 } else if (function == 7 && index == 0 && reg == R_EBX) {
371 if (host_tsx_blacklisted()) {
372 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
373 }
374 } else if (function == 0x80000001 && reg == R_EDX) {
375 /* On Intel, kvm returns cpuid according to the Intel spec,
376 * so add missing bits according to the AMD spec:
377 */
378 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
379 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
380 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
381 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
382 * be enabled without the in-kernel irqchip
383 */
384 if (!kvm_irqchip_in_kernel()) {
385 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
386 }
387 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
388 ret |= KVM_HINTS_DEDICATED;
389 found = 1;
390 }
391
392 /* fallback for older kernels */
393 if ((function == KVM_CPUID_FEATURES) && !found) {
394 ret = get_para_features(s);
395 }
396
397 return ret;
398 }
399
400 typedef struct HWPoisonPage {
401 ram_addr_t ram_addr;
402 QLIST_ENTRY(HWPoisonPage) list;
403 } HWPoisonPage;
404
405 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
406 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
407
408 static void kvm_unpoison_all(void *param)
409 {
410 HWPoisonPage *page, *next_page;
411
412 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
413 QLIST_REMOVE(page, list);
414 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
415 g_free(page);
416 }
417 }
418
419 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
420 {
421 HWPoisonPage *page;
422
423 QLIST_FOREACH(page, &hwpoison_page_list, list) {
424 if (page->ram_addr == ram_addr) {
425 return;
426 }
427 }
428 page = g_new(HWPoisonPage, 1);
429 page->ram_addr = ram_addr;
430 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
431 }
432
433 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
434 int *max_banks)
435 {
436 int r;
437
438 r = kvm_check_extension(s, KVM_CAP_MCE);
439 if (r > 0) {
440 *max_banks = r;
441 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
442 }
443 return -ENOSYS;
444 }
445
446 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
447 {
448 CPUState *cs = CPU(cpu);
449 CPUX86State *env = &cpu->env;
450 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
451 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
452 uint64_t mcg_status = MCG_STATUS_MCIP;
453 int flags = 0;
454
455 if (code == BUS_MCEERR_AR) {
456 status |= MCI_STATUS_AR | 0x134;
457 mcg_status |= MCG_STATUS_EIPV;
458 } else {
459 status |= 0xc0;
460 mcg_status |= MCG_STATUS_RIPV;
461 }
462
463 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
464 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
465 * guest kernel back into env->mcg_ext_ctl.
466 */
467 cpu_synchronize_state(cs);
468 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
469 mcg_status |= MCG_STATUS_LMCE;
470 flags = 0;
471 }
472
473 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
474 (MCM_ADDR_PHYS << 6) | 0xc, flags);
475 }
476
477 static void hardware_memory_error(void)
478 {
479 fprintf(stderr, "Hardware memory error!\n");
480 exit(1);
481 }
482
483 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
484 {
485 X86CPU *cpu = X86_CPU(c);
486 CPUX86State *env = &cpu->env;
487 ram_addr_t ram_addr;
488 hwaddr paddr;
489
490 /* If we get an action required MCE, it has been injected by KVM
491 * while the VM was running. An action optional MCE instead should
492 * be coming from the main thread, which qemu_init_sigbus identifies
493 * as the "early kill" thread.
494 */
495 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
496
497 if ((env->mcg_cap & MCG_SER_P) && addr) {
498 ram_addr = qemu_ram_addr_from_host(addr);
499 if (ram_addr != RAM_ADDR_INVALID &&
500 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
501 kvm_hwpoison_page_add(ram_addr);
502 kvm_mce_inject(cpu, paddr, code);
503 return;
504 }
505
506 fprintf(stderr, "Hardware memory error for memory used by "
507 "QEMU itself instead of guest system!\n");
508 }
509
510 if (code == BUS_MCEERR_AR) {
511 hardware_memory_error();
512 }
513
514 /* Hope we are lucky for AO MCE */
515 }
516
517 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
518 {
519 CPUX86State *env = &cpu->env;
520
521 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
522 unsigned int bank, bank_num = env->mcg_cap & 0xff;
523 struct kvm_x86_mce mce;
524
525 env->exception_injected = -1;
526
527 /*
528 * There must be at least one bank in use if an MCE is pending.
529 * Find it and use its values for the event injection.
530 */
531 for (bank = 0; bank < bank_num; bank++) {
532 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
533 break;
534 }
535 }
536 assert(bank < bank_num);
537
538 mce.bank = bank;
539 mce.status = env->mce_banks[bank * 4 + 1];
540 mce.mcg_status = env->mcg_status;
541 mce.addr = env->mce_banks[bank * 4 + 2];
542 mce.misc = env->mce_banks[bank * 4 + 3];
543
544 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
545 }
546 return 0;
547 }
548
549 static void cpu_update_state(void *opaque, int running, RunState state)
550 {
551 CPUX86State *env = opaque;
552
553 if (running) {
554 env->tsc_valid = false;
555 }
556 }
557
558 unsigned long kvm_arch_vcpu_id(CPUState *cs)
559 {
560 X86CPU *cpu = X86_CPU(cs);
561 return cpu->apic_id;
562 }
563
564 #ifndef KVM_CPUID_SIGNATURE_NEXT
565 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
566 #endif
567
568 static bool hyperv_hypercall_available(X86CPU *cpu)
569 {
570 return cpu->hyperv_vapic ||
571 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
572 }
573
574 static bool hyperv_enabled(X86CPU *cpu)
575 {
576 CPUState *cs = CPU(cpu);
577 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
578 (hyperv_hypercall_available(cpu) ||
579 cpu->hyperv_time ||
580 cpu->hyperv_relaxed_timing ||
581 cpu->hyperv_crash ||
582 cpu->hyperv_reset ||
583 cpu->hyperv_vpindex ||
584 cpu->hyperv_runtime ||
585 cpu->hyperv_synic ||
586 cpu->hyperv_stimer);
587 }
588
589 static int kvm_arch_set_tsc_khz(CPUState *cs)
590 {
591 X86CPU *cpu = X86_CPU(cs);
592 CPUX86State *env = &cpu->env;
593 int r;
594
595 if (!env->tsc_khz) {
596 return 0;
597 }
598
599 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
600 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
601 -ENOTSUP;
602 if (r < 0) {
603 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
604 * TSC frequency doesn't match the one we want.
605 */
606 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
607 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
608 -ENOTSUP;
609 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
610 warn_report("TSC frequency mismatch between "
611 "VM (%" PRId64 " kHz) and host (%d kHz), "
612 "and TSC scaling unavailable",
613 env->tsc_khz, cur_freq);
614 return r;
615 }
616 }
617
618 return 0;
619 }
620
621 static bool tsc_is_stable_and_known(CPUX86State *env)
622 {
623 if (!env->tsc_khz) {
624 return false;
625 }
626 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
627 || env->user_tsc_khz;
628 }
629
630 static int hyperv_handle_properties(CPUState *cs)
631 {
632 X86CPU *cpu = X86_CPU(cs);
633 CPUX86State *env = &cpu->env;
634
635 if (cpu->hyperv_time &&
636 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
637 cpu->hyperv_time = false;
638 }
639
640 if (cpu->hyperv_relaxed_timing) {
641 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
642 }
643 if (cpu->hyperv_vapic) {
644 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
646 }
647 if (cpu->hyperv_time) {
648 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
649 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
651
652 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
653 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
654 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
655 }
656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
658 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
659 }
660 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
661 if (cpu->hyperv_reset && has_msr_hv_reset) {
662 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
665 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
668 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
669 }
670 if (cpu->hyperv_synic) {
671 if (!has_msr_hv_synic ||
672 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
673 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
674 return -ENOSYS;
675 }
676
677 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
684 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
685 }
686 return 0;
687 }
688
689 static Error *invtsc_mig_blocker;
690
691 #define KVM_MAX_CPUID_ENTRIES 100
692
693 int kvm_arch_init_vcpu(CPUState *cs)
694 {
695 struct {
696 struct kvm_cpuid2 cpuid;
697 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
698 } QEMU_PACKED cpuid_data;
699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
701 uint32_t limit, i, j, cpuid_i;
702 uint32_t unused;
703 struct kvm_cpuid_entry2 *c;
704 uint32_t signature[3];
705 int kvm_base = KVM_CPUID_SIGNATURE;
706 int r;
707 Error *local_err = NULL;
708
709 memset(&cpuid_data, 0, sizeof(cpuid_data));
710
711 cpuid_i = 0;
712
713 r = kvm_arch_set_tsc_khz(cs);
714 if (r < 0) {
715 goto fail;
716 }
717
718 /* vcpu's TSC frequency is either specified by user, or following
719 * the value used by KVM if the former is not present. In the
720 * latter case, we query it from KVM and record in env->tsc_khz,
721 * so that vcpu's TSC frequency can be migrated later via this field.
722 */
723 if (!env->tsc_khz) {
724 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
725 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
726 -ENOTSUP;
727 if (r > 0) {
728 env->tsc_khz = r;
729 }
730 }
731
732 /* Paravirtualization CPUIDs */
733 if (hyperv_enabled(cpu)) {
734 c = &cpuid_data.entries[cpuid_i++];
735 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
736 if (!cpu->hyperv_vendor_id) {
737 memcpy(signature, "Microsoft Hv", 12);
738 } else {
739 size_t len = strlen(cpu->hyperv_vendor_id);
740
741 if (len > 12) {
742 error_report("hv-vendor-id truncated to 12 characters");
743 len = 12;
744 }
745 memset(signature, 0, 12);
746 memcpy(signature, cpu->hyperv_vendor_id, len);
747 }
748 c->eax = HV_CPUID_MIN;
749 c->ebx = signature[0];
750 c->ecx = signature[1];
751 c->edx = signature[2];
752
753 c = &cpuid_data.entries[cpuid_i++];
754 c->function = HV_CPUID_INTERFACE;
755 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
756 c->eax = signature[0];
757 c->ebx = 0;
758 c->ecx = 0;
759 c->edx = 0;
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HV_CPUID_VERSION;
763 c->eax = 0x00001bbc;
764 c->ebx = 0x00060001;
765
766 c = &cpuid_data.entries[cpuid_i++];
767 c->function = HV_CPUID_FEATURES;
768 r = hyperv_handle_properties(cs);
769 if (r) {
770 return r;
771 }
772 c->eax = env->features[FEAT_HYPERV_EAX];
773 c->ebx = env->features[FEAT_HYPERV_EBX];
774 c->edx = env->features[FEAT_HYPERV_EDX];
775
776 c = &cpuid_data.entries[cpuid_i++];
777 c->function = HV_CPUID_ENLIGHTMENT_INFO;
778 if (cpu->hyperv_relaxed_timing) {
779 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
780 }
781 if (cpu->hyperv_vapic) {
782 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
783 }
784 c->ebx = cpu->hyperv_spinlock_attempts;
785
786 c = &cpuid_data.entries[cpuid_i++];
787 c->function = HV_CPUID_IMPLEMENT_LIMITS;
788
789 c->eax = cpu->hv_max_vps;
790 c->ebx = 0x40;
791
792 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
793 has_msr_hv_hypercall = true;
794 }
795
796 if (cpu->expose_kvm) {
797 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
798 c = &cpuid_data.entries[cpuid_i++];
799 c->function = KVM_CPUID_SIGNATURE | kvm_base;
800 c->eax = KVM_CPUID_FEATURES | kvm_base;
801 c->ebx = signature[0];
802 c->ecx = signature[1];
803 c->edx = signature[2];
804
805 c = &cpuid_data.entries[cpuid_i++];
806 c->function = KVM_CPUID_FEATURES | kvm_base;
807 c->eax = env->features[FEAT_KVM];
808 c->edx = env->features[FEAT_KVM_HINTS];
809 }
810
811 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
812
813 for (i = 0; i <= limit; i++) {
814 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
815 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
816 abort();
817 }
818 c = &cpuid_data.entries[cpuid_i++];
819
820 switch (i) {
821 case 2: {
822 /* Keep reading function 2 till all the input is received */
823 int times;
824
825 c->function = i;
826 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
827 KVM_CPUID_FLAG_STATE_READ_NEXT;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
829 times = c->eax & 0xff;
830
831 for (j = 1; j < times; ++j) {
832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "cpuid_data is full, no space for "
834 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
835 abort();
836 }
837 c = &cpuid_data.entries[cpuid_i++];
838 c->function = i;
839 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
841 }
842 break;
843 }
844 case 4:
845 case 0xb:
846 case 0xd:
847 for (j = 0; ; j++) {
848 if (i == 0xd && j == 64) {
849 break;
850 }
851 c->function = i;
852 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
853 c->index = j;
854 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
855
856 if (i == 4 && c->eax == 0) {
857 break;
858 }
859 if (i == 0xb && !(c->ecx & 0xff00)) {
860 break;
861 }
862 if (i == 0xd && c->eax == 0) {
863 continue;
864 }
865 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
866 fprintf(stderr, "cpuid_data is full, no space for "
867 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
868 abort();
869 }
870 c = &cpuid_data.entries[cpuid_i++];
871 }
872 break;
873 case 0x14: {
874 uint32_t times;
875
876 c->function = i;
877 c->index = 0;
878 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
879 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
880 times = c->eax;
881
882 for (j = 1; j <= times; ++j) {
883 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
884 fprintf(stderr, "cpuid_data is full, no space for "
885 "cpuid(eax:0x14,ecx:0x%x)\n", j);
886 abort();
887 }
888 c = &cpuid_data.entries[cpuid_i++];
889 c->function = i;
890 c->index = j;
891 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
892 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
893 }
894 break;
895 }
896 default:
897 c->function = i;
898 c->flags = 0;
899 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
900 break;
901 }
902 }
903
904 if (limit >= 0x0a) {
905 uint32_t eax, edx;
906
907 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
908
909 has_architectural_pmu_version = eax & 0xff;
910 if (has_architectural_pmu_version > 0) {
911 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
912
913 /* Shouldn't be more than 32, since that's the number of bits
914 * available in EBX to tell us _which_ counters are available.
915 * Play it safe.
916 */
917 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
918 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
919 }
920
921 if (has_architectural_pmu_version > 1) {
922 num_architectural_pmu_fixed_counters = edx & 0x1f;
923
924 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
925 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
926 }
927 }
928 }
929 }
930
931 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
932
933 for (i = 0x80000000; i <= limit; i++) {
934 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
935 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
936 abort();
937 }
938 c = &cpuid_data.entries[cpuid_i++];
939
940 c->function = i;
941 c->flags = 0;
942 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
943 }
944
945 /* Call Centaur's CPUID instructions they are supported. */
946 if (env->cpuid_xlevel2 > 0) {
947 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
948
949 for (i = 0xC0000000; i <= limit; i++) {
950 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
951 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
952 abort();
953 }
954 c = &cpuid_data.entries[cpuid_i++];
955
956 c->function = i;
957 c->flags = 0;
958 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
959 }
960 }
961
962 cpuid_data.cpuid.nent = cpuid_i;
963
964 if (((env->cpuid_version >> 8)&0xF) >= 6
965 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
966 (CPUID_MCE | CPUID_MCA)
967 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
968 uint64_t mcg_cap, unsupported_caps;
969 int banks;
970 int ret;
971
972 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
973 if (ret < 0) {
974 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
975 return ret;
976 }
977
978 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
979 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
980 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
981 return -ENOTSUP;
982 }
983
984 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
985 if (unsupported_caps) {
986 if (unsupported_caps & MCG_LMCE_P) {
987 error_report("kvm: LMCE not supported");
988 return -ENOTSUP;
989 }
990 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
991 unsupported_caps);
992 }
993
994 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
995 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
996 if (ret < 0) {
997 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
998 return ret;
999 }
1000 }
1001
1002 qemu_add_vm_change_state_handler(cpu_update_state, env);
1003
1004 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1005 if (c) {
1006 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1007 !!(c->ecx & CPUID_EXT_SMX);
1008 }
1009
1010 if (env->mcg_cap & MCG_LMCE_P) {
1011 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1012 }
1013
1014 if (!env->user_tsc_khz) {
1015 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1016 invtsc_mig_blocker == NULL) {
1017 /* for migration */
1018 error_setg(&invtsc_mig_blocker,
1019 "State blocked by non-migratable CPU device"
1020 " (invtsc flag)");
1021 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1022 if (local_err) {
1023 error_report_err(local_err);
1024 error_free(invtsc_mig_blocker);
1025 goto fail;
1026 }
1027 /* for savevm */
1028 vmstate_x86_cpu.unmigratable = 1;
1029 }
1030 }
1031
1032 if (cpu->vmware_cpuid_freq
1033 /* Guests depend on 0x40000000 to detect this feature, so only expose
1034 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1035 && cpu->expose_kvm
1036 && kvm_base == KVM_CPUID_SIGNATURE
1037 /* TSC clock must be stable and known for this feature. */
1038 && tsc_is_stable_and_known(env)) {
1039
1040 c = &cpuid_data.entries[cpuid_i++];
1041 c->function = KVM_CPUID_SIGNATURE | 0x10;
1042 c->eax = env->tsc_khz;
1043 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1044 * APIC_BUS_CYCLE_NS */
1045 c->ebx = 1000000;
1046 c->ecx = c->edx = 0;
1047
1048 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1049 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1050 }
1051
1052 cpuid_data.cpuid.nent = cpuid_i;
1053
1054 cpuid_data.cpuid.padding = 0;
1055 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1056 if (r) {
1057 goto fail;
1058 }
1059
1060 if (has_xsave) {
1061 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1062 }
1063 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1064
1065 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1066 has_msr_tsc_aux = false;
1067 }
1068
1069 return 0;
1070
1071 fail:
1072 migrate_del_blocker(invtsc_mig_blocker);
1073 return r;
1074 }
1075
1076 void kvm_arch_reset_vcpu(X86CPU *cpu)
1077 {
1078 CPUX86State *env = &cpu->env;
1079
1080 env->xcr0 = 1;
1081 if (kvm_irqchip_in_kernel()) {
1082 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1083 KVM_MP_STATE_UNINITIALIZED;
1084 } else {
1085 env->mp_state = KVM_MP_STATE_RUNNABLE;
1086 }
1087
1088 if (cpu->hyperv_synic) {
1089 int i;
1090 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1091 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1092 }
1093 }
1094 }
1095
1096 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1097 {
1098 CPUX86State *env = &cpu->env;
1099
1100 /* APs get directly into wait-for-SIPI state. */
1101 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1102 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1103 }
1104 }
1105
1106 static int kvm_get_supported_msrs(KVMState *s)
1107 {
1108 static int kvm_supported_msrs;
1109 int ret = 0;
1110
1111 /* first time */
1112 if (kvm_supported_msrs == 0) {
1113 struct kvm_msr_list msr_list, *kvm_msr_list;
1114
1115 kvm_supported_msrs = -1;
1116
1117 /* Obtain MSR list from KVM. These are the MSRs that we must
1118 * save/restore */
1119 msr_list.nmsrs = 0;
1120 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1121 if (ret < 0 && ret != -E2BIG) {
1122 return ret;
1123 }
1124 /* Old kernel modules had a bug and could write beyond the provided
1125 memory. Allocate at least a safe amount of 1K. */
1126 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1127 msr_list.nmsrs *
1128 sizeof(msr_list.indices[0])));
1129
1130 kvm_msr_list->nmsrs = msr_list.nmsrs;
1131 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1132 if (ret >= 0) {
1133 int i;
1134
1135 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1136 switch (kvm_msr_list->indices[i]) {
1137 case MSR_STAR:
1138 has_msr_star = true;
1139 break;
1140 case MSR_VM_HSAVE_PA:
1141 has_msr_hsave_pa = true;
1142 break;
1143 case MSR_TSC_AUX:
1144 has_msr_tsc_aux = true;
1145 break;
1146 case MSR_TSC_ADJUST:
1147 has_msr_tsc_adjust = true;
1148 break;
1149 case MSR_IA32_TSCDEADLINE:
1150 has_msr_tsc_deadline = true;
1151 break;
1152 case MSR_IA32_SMBASE:
1153 has_msr_smbase = true;
1154 break;
1155 case MSR_SMI_COUNT:
1156 has_msr_smi_count = true;
1157 break;
1158 case MSR_IA32_MISC_ENABLE:
1159 has_msr_misc_enable = true;
1160 break;
1161 case MSR_IA32_BNDCFGS:
1162 has_msr_bndcfgs = true;
1163 break;
1164 case MSR_IA32_XSS:
1165 has_msr_xss = true;
1166 break;
1167 case HV_X64_MSR_CRASH_CTL:
1168 has_msr_hv_crash = true;
1169 break;
1170 case HV_X64_MSR_RESET:
1171 has_msr_hv_reset = true;
1172 break;
1173 case HV_X64_MSR_VP_INDEX:
1174 has_msr_hv_vpindex = true;
1175 break;
1176 case HV_X64_MSR_VP_RUNTIME:
1177 has_msr_hv_runtime = true;
1178 break;
1179 case HV_X64_MSR_SCONTROL:
1180 has_msr_hv_synic = true;
1181 break;
1182 case HV_X64_MSR_STIMER0_CONFIG:
1183 has_msr_hv_stimer = true;
1184 break;
1185 case HV_X64_MSR_TSC_FREQUENCY:
1186 has_msr_hv_frequencies = true;
1187 break;
1188 case MSR_IA32_SPEC_CTRL:
1189 has_msr_spec_ctrl = true;
1190 break;
1191 }
1192 }
1193 }
1194
1195 g_free(kvm_msr_list);
1196 }
1197
1198 return ret;
1199 }
1200
1201 static Notifier smram_machine_done;
1202 static KVMMemoryListener smram_listener;
1203 static AddressSpace smram_address_space;
1204 static MemoryRegion smram_as_root;
1205 static MemoryRegion smram_as_mem;
1206
1207 static void register_smram_listener(Notifier *n, void *unused)
1208 {
1209 MemoryRegion *smram =
1210 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1211
1212 /* Outer container... */
1213 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1214 memory_region_set_enabled(&smram_as_root, true);
1215
1216 /* ... with two regions inside: normal system memory with low
1217 * priority, and...
1218 */
1219 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1220 get_system_memory(), 0, ~0ull);
1221 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1222 memory_region_set_enabled(&smram_as_mem, true);
1223
1224 if (smram) {
1225 /* ... SMRAM with higher priority */
1226 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1227 memory_region_set_enabled(smram, true);
1228 }
1229
1230 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1231 kvm_memory_listener_register(kvm_state, &smram_listener,
1232 &smram_address_space, 1);
1233 }
1234
1235 int kvm_arch_init(MachineState *ms, KVMState *s)
1236 {
1237 uint64_t identity_base = 0xfffbc000;
1238 uint64_t shadow_mem;
1239 int ret;
1240 struct utsname utsname;
1241
1242 #ifdef KVM_CAP_XSAVE
1243 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1244 #endif
1245
1246 #ifdef KVM_CAP_XCRS
1247 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1248 #endif
1249
1250 #ifdef KVM_CAP_PIT_STATE2
1251 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1252 #endif
1253
1254 ret = kvm_get_supported_msrs(s);
1255 if (ret < 0) {
1256 return ret;
1257 }
1258
1259 uname(&utsname);
1260 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1261
1262 /*
1263 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1264 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1265 * Since these must be part of guest physical memory, we need to allocate
1266 * them, both by setting their start addresses in the kernel and by
1267 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1268 *
1269 * Older KVM versions may not support setting the identity map base. In
1270 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1271 * size.
1272 */
1273 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1274 /* Allows up to 16M BIOSes. */
1275 identity_base = 0xfeffc000;
1276
1277 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1278 if (ret < 0) {
1279 return ret;
1280 }
1281 }
1282
1283 /* Set TSS base one page after EPT identity map. */
1284 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1285 if (ret < 0) {
1286 return ret;
1287 }
1288
1289 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1290 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1291 if (ret < 0) {
1292 fprintf(stderr, "e820_add_entry() table is full\n");
1293 return ret;
1294 }
1295 qemu_register_reset(kvm_unpoison_all, NULL);
1296
1297 shadow_mem = machine_kvm_shadow_mem(ms);
1298 if (shadow_mem != -1) {
1299 shadow_mem /= 4096;
1300 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1301 if (ret < 0) {
1302 return ret;
1303 }
1304 }
1305
1306 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1307 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1308 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1309 smram_machine_done.notify = register_smram_listener;
1310 qemu_add_machine_init_done_notifier(&smram_machine_done);
1311 }
1312 return 0;
1313 }
1314
1315 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1316 {
1317 lhs->selector = rhs->selector;
1318 lhs->base = rhs->base;
1319 lhs->limit = rhs->limit;
1320 lhs->type = 3;
1321 lhs->present = 1;
1322 lhs->dpl = 3;
1323 lhs->db = 0;
1324 lhs->s = 1;
1325 lhs->l = 0;
1326 lhs->g = 0;
1327 lhs->avl = 0;
1328 lhs->unusable = 0;
1329 }
1330
1331 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1332 {
1333 unsigned flags = rhs->flags;
1334 lhs->selector = rhs->selector;
1335 lhs->base = rhs->base;
1336 lhs->limit = rhs->limit;
1337 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1338 lhs->present = (flags & DESC_P_MASK) != 0;
1339 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1340 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1341 lhs->s = (flags & DESC_S_MASK) != 0;
1342 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1343 lhs->g = (flags & DESC_G_MASK) != 0;
1344 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1345 lhs->unusable = !lhs->present;
1346 lhs->padding = 0;
1347 }
1348
1349 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1350 {
1351 lhs->selector = rhs->selector;
1352 lhs->base = rhs->base;
1353 lhs->limit = rhs->limit;
1354 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1355 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1356 (rhs->dpl << DESC_DPL_SHIFT) |
1357 (rhs->db << DESC_B_SHIFT) |
1358 (rhs->s * DESC_S_MASK) |
1359 (rhs->l << DESC_L_SHIFT) |
1360 (rhs->g * DESC_G_MASK) |
1361 (rhs->avl * DESC_AVL_MASK);
1362 }
1363
1364 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1365 {
1366 if (set) {
1367 *kvm_reg = *qemu_reg;
1368 } else {
1369 *qemu_reg = *kvm_reg;
1370 }
1371 }
1372
1373 static int kvm_getput_regs(X86CPU *cpu, int set)
1374 {
1375 CPUX86State *env = &cpu->env;
1376 struct kvm_regs regs;
1377 int ret = 0;
1378
1379 if (!set) {
1380 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1381 if (ret < 0) {
1382 return ret;
1383 }
1384 }
1385
1386 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1387 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1388 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1389 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1390 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1391 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1392 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1393 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1394 #ifdef TARGET_X86_64
1395 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1396 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1397 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1398 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1399 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1400 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1401 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1402 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1403 #endif
1404
1405 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1406 kvm_getput_reg(&regs.rip, &env->eip, set);
1407
1408 if (set) {
1409 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1410 }
1411
1412 return ret;
1413 }
1414
1415 static int kvm_put_fpu(X86CPU *cpu)
1416 {
1417 CPUX86State *env = &cpu->env;
1418 struct kvm_fpu fpu;
1419 int i;
1420
1421 memset(&fpu, 0, sizeof fpu);
1422 fpu.fsw = env->fpus & ~(7 << 11);
1423 fpu.fsw |= (env->fpstt & 7) << 11;
1424 fpu.fcw = env->fpuc;
1425 fpu.last_opcode = env->fpop;
1426 fpu.last_ip = env->fpip;
1427 fpu.last_dp = env->fpdp;
1428 for (i = 0; i < 8; ++i) {
1429 fpu.ftwx |= (!env->fptags[i]) << i;
1430 }
1431 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1432 for (i = 0; i < CPU_NB_REGS; i++) {
1433 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1434 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1435 }
1436 fpu.mxcsr = env->mxcsr;
1437
1438 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1439 }
1440
1441 #define XSAVE_FCW_FSW 0
1442 #define XSAVE_FTW_FOP 1
1443 #define XSAVE_CWD_RIP 2
1444 #define XSAVE_CWD_RDP 4
1445 #define XSAVE_MXCSR 6
1446 #define XSAVE_ST_SPACE 8
1447 #define XSAVE_XMM_SPACE 40
1448 #define XSAVE_XSTATE_BV 128
1449 #define XSAVE_YMMH_SPACE 144
1450 #define XSAVE_BNDREGS 240
1451 #define XSAVE_BNDCSR 256
1452 #define XSAVE_OPMASK 272
1453 #define XSAVE_ZMM_Hi256 288
1454 #define XSAVE_Hi16_ZMM 416
1455 #define XSAVE_PKRU 672
1456
1457 #define XSAVE_BYTE_OFFSET(word_offset) \
1458 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1459
1460 #define ASSERT_OFFSET(word_offset, field) \
1461 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1462 offsetof(X86XSaveArea, field))
1463
1464 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1465 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1466 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1467 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1468 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1469 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1470 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1471 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1472 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1473 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1474 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1475 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1476 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1477 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1478 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1479
1480 static int kvm_put_xsave(X86CPU *cpu)
1481 {
1482 CPUX86State *env = &cpu->env;
1483 X86XSaveArea *xsave = env->kvm_xsave_buf;
1484
1485 if (!has_xsave) {
1486 return kvm_put_fpu(cpu);
1487 }
1488 x86_cpu_xsave_all_areas(cpu, xsave);
1489
1490 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1491 }
1492
1493 static int kvm_put_xcrs(X86CPU *cpu)
1494 {
1495 CPUX86State *env = &cpu->env;
1496 struct kvm_xcrs xcrs = {};
1497
1498 if (!has_xcrs) {
1499 return 0;
1500 }
1501
1502 xcrs.nr_xcrs = 1;
1503 xcrs.flags = 0;
1504 xcrs.xcrs[0].xcr = 0;
1505 xcrs.xcrs[0].value = env->xcr0;
1506 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1507 }
1508
1509 static int kvm_put_sregs(X86CPU *cpu)
1510 {
1511 CPUX86State *env = &cpu->env;
1512 struct kvm_sregs sregs;
1513
1514 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1515 if (env->interrupt_injected >= 0) {
1516 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1517 (uint64_t)1 << (env->interrupt_injected % 64);
1518 }
1519
1520 if ((env->eflags & VM_MASK)) {
1521 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1522 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1523 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1524 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1525 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1526 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1527 } else {
1528 set_seg(&sregs.cs, &env->segs[R_CS]);
1529 set_seg(&sregs.ds, &env->segs[R_DS]);
1530 set_seg(&sregs.es, &env->segs[R_ES]);
1531 set_seg(&sregs.fs, &env->segs[R_FS]);
1532 set_seg(&sregs.gs, &env->segs[R_GS]);
1533 set_seg(&sregs.ss, &env->segs[R_SS]);
1534 }
1535
1536 set_seg(&sregs.tr, &env->tr);
1537 set_seg(&sregs.ldt, &env->ldt);
1538
1539 sregs.idt.limit = env->idt.limit;
1540 sregs.idt.base = env->idt.base;
1541 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1542 sregs.gdt.limit = env->gdt.limit;
1543 sregs.gdt.base = env->gdt.base;
1544 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1545
1546 sregs.cr0 = env->cr[0];
1547 sregs.cr2 = env->cr[2];
1548 sregs.cr3 = env->cr[3];
1549 sregs.cr4 = env->cr[4];
1550
1551 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1552 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1553
1554 sregs.efer = env->efer;
1555
1556 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1557 }
1558
1559 static void kvm_msr_buf_reset(X86CPU *cpu)
1560 {
1561 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1562 }
1563
1564 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1565 {
1566 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1567 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1568 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1569
1570 assert((void *)(entry + 1) <= limit);
1571
1572 entry->index = index;
1573 entry->reserved = 0;
1574 entry->data = value;
1575 msrs->nmsrs++;
1576 }
1577
1578 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1579 {
1580 kvm_msr_buf_reset(cpu);
1581 kvm_msr_entry_add(cpu, index, value);
1582
1583 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1584 }
1585
1586 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1587 {
1588 int ret;
1589
1590 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1591 assert(ret == 1);
1592 }
1593
1594 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1595 {
1596 CPUX86State *env = &cpu->env;
1597 int ret;
1598
1599 if (!has_msr_tsc_deadline) {
1600 return 0;
1601 }
1602
1603 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1604 if (ret < 0) {
1605 return ret;
1606 }
1607
1608 assert(ret == 1);
1609 return 0;
1610 }
1611
1612 /*
1613 * Provide a separate write service for the feature control MSR in order to
1614 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1615 * before writing any other state because forcibly leaving nested mode
1616 * invalidates the VCPU state.
1617 */
1618 static int kvm_put_msr_feature_control(X86CPU *cpu)
1619 {
1620 int ret;
1621
1622 if (!has_msr_feature_control) {
1623 return 0;
1624 }
1625
1626 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1627 cpu->env.msr_ia32_feature_control);
1628 if (ret < 0) {
1629 return ret;
1630 }
1631
1632 assert(ret == 1);
1633 return 0;
1634 }
1635
1636 static int kvm_put_msrs(X86CPU *cpu, int level)
1637 {
1638 CPUX86State *env = &cpu->env;
1639 int i;
1640 int ret;
1641
1642 kvm_msr_buf_reset(cpu);
1643
1644 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1645 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1646 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1647 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1648 if (has_msr_star) {
1649 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1650 }
1651 if (has_msr_hsave_pa) {
1652 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1653 }
1654 if (has_msr_tsc_aux) {
1655 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1656 }
1657 if (has_msr_tsc_adjust) {
1658 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1659 }
1660 if (has_msr_misc_enable) {
1661 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1662 env->msr_ia32_misc_enable);
1663 }
1664 if (has_msr_smbase) {
1665 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1666 }
1667 if (has_msr_smi_count) {
1668 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1669 }
1670 if (has_msr_bndcfgs) {
1671 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1672 }
1673 if (has_msr_xss) {
1674 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1675 }
1676 if (has_msr_spec_ctrl) {
1677 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1678 }
1679 #ifdef TARGET_X86_64
1680 if (lm_capable_kernel) {
1681 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1682 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1683 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1684 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1685 }
1686 #endif
1687
1688 /*
1689 * The following MSRs have side effects on the guest or are too heavy
1690 * for normal writeback. Limit them to reset or full state updates.
1691 */
1692 if (level >= KVM_PUT_RESET_STATE) {
1693 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1694 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1695 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1696 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1697 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1698 }
1699 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1700 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1701 }
1702 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1703 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1704 }
1705 if (has_architectural_pmu_version > 0) {
1706 if (has_architectural_pmu_version > 1) {
1707 /* Stop the counter. */
1708 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1709 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1710 }
1711
1712 /* Set the counter values. */
1713 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1714 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1715 env->msr_fixed_counters[i]);
1716 }
1717 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1718 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1719 env->msr_gp_counters[i]);
1720 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1721 env->msr_gp_evtsel[i]);
1722 }
1723 if (has_architectural_pmu_version > 1) {
1724 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1725 env->msr_global_status);
1726 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1727 env->msr_global_ovf_ctrl);
1728
1729 /* Now start the PMU. */
1730 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1731 env->msr_fixed_ctr_ctrl);
1732 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1733 env->msr_global_ctrl);
1734 }
1735 }
1736 /*
1737 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1738 * only sync them to KVM on the first cpu
1739 */
1740 if (current_cpu == first_cpu) {
1741 if (has_msr_hv_hypercall) {
1742 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1743 env->msr_hv_guest_os_id);
1744 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1745 env->msr_hv_hypercall);
1746 }
1747 if (cpu->hyperv_time) {
1748 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1749 env->msr_hv_tsc);
1750 }
1751 }
1752 if (cpu->hyperv_vapic) {
1753 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1754 env->msr_hv_vapic);
1755 }
1756 if (has_msr_hv_crash) {
1757 int j;
1758
1759 for (j = 0; j < HV_CRASH_PARAMS; j++)
1760 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1761 env->msr_hv_crash_params[j]);
1762
1763 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1764 }
1765 if (has_msr_hv_runtime) {
1766 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1767 }
1768 if (cpu->hyperv_synic) {
1769 int j;
1770
1771 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1772
1773 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1774 env->msr_hv_synic_control);
1775 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1776 env->msr_hv_synic_evt_page);
1777 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1778 env->msr_hv_synic_msg_page);
1779
1780 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1781 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1782 env->msr_hv_synic_sint[j]);
1783 }
1784 }
1785 if (has_msr_hv_stimer) {
1786 int j;
1787
1788 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1789 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1790 env->msr_hv_stimer_config[j]);
1791 }
1792
1793 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1794 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1795 env->msr_hv_stimer_count[j]);
1796 }
1797 }
1798 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1799 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1800
1801 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1802 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1803 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1804 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1805 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1806 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1807 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1808 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1809 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1810 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1811 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1812 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1813 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1814 /* The CPU GPs if we write to a bit above the physical limit of
1815 * the host CPU (and KVM emulates that)
1816 */
1817 uint64_t mask = env->mtrr_var[i].mask;
1818 mask &= phys_mask;
1819
1820 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1821 env->mtrr_var[i].base);
1822 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1823 }
1824 }
1825 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1826 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1827 0x14, 1, R_EAX) & 0x7;
1828
1829 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1830 env->msr_rtit_ctrl);
1831 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1832 env->msr_rtit_status);
1833 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1834 env->msr_rtit_output_base);
1835 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1836 env->msr_rtit_output_mask);
1837 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1838 env->msr_rtit_cr3_match);
1839 for (i = 0; i < addr_num; i++) {
1840 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1841 env->msr_rtit_addrs[i]);
1842 }
1843 }
1844
1845 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1846 * kvm_put_msr_feature_control. */
1847 }
1848 if (env->mcg_cap) {
1849 int i;
1850
1851 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1852 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1853 if (has_msr_mcg_ext_ctl) {
1854 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1855 }
1856 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1857 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1858 }
1859 }
1860
1861 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1862 if (ret < 0) {
1863 return ret;
1864 }
1865
1866 if (ret < cpu->kvm_msr_buf->nmsrs) {
1867 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1868 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1869 (uint32_t)e->index, (uint64_t)e->data);
1870 }
1871
1872 assert(ret == cpu->kvm_msr_buf->nmsrs);
1873 return 0;
1874 }
1875
1876
1877 static int kvm_get_fpu(X86CPU *cpu)
1878 {
1879 CPUX86State *env = &cpu->env;
1880 struct kvm_fpu fpu;
1881 int i, ret;
1882
1883 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1884 if (ret < 0) {
1885 return ret;
1886 }
1887
1888 env->fpstt = (fpu.fsw >> 11) & 7;
1889 env->fpus = fpu.fsw;
1890 env->fpuc = fpu.fcw;
1891 env->fpop = fpu.last_opcode;
1892 env->fpip = fpu.last_ip;
1893 env->fpdp = fpu.last_dp;
1894 for (i = 0; i < 8; ++i) {
1895 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1896 }
1897 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1898 for (i = 0; i < CPU_NB_REGS; i++) {
1899 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1900 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1901 }
1902 env->mxcsr = fpu.mxcsr;
1903
1904 return 0;
1905 }
1906
1907 static int kvm_get_xsave(X86CPU *cpu)
1908 {
1909 CPUX86State *env = &cpu->env;
1910 X86XSaveArea *xsave = env->kvm_xsave_buf;
1911 int ret;
1912
1913 if (!has_xsave) {
1914 return kvm_get_fpu(cpu);
1915 }
1916
1917 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1918 if (ret < 0) {
1919 return ret;
1920 }
1921 x86_cpu_xrstor_all_areas(cpu, xsave);
1922
1923 return 0;
1924 }
1925
1926 static int kvm_get_xcrs(X86CPU *cpu)
1927 {
1928 CPUX86State *env = &cpu->env;
1929 int i, ret;
1930 struct kvm_xcrs xcrs;
1931
1932 if (!has_xcrs) {
1933 return 0;
1934 }
1935
1936 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1937 if (ret < 0) {
1938 return ret;
1939 }
1940
1941 for (i = 0; i < xcrs.nr_xcrs; i++) {
1942 /* Only support xcr0 now */
1943 if (xcrs.xcrs[i].xcr == 0) {
1944 env->xcr0 = xcrs.xcrs[i].value;
1945 break;
1946 }
1947 }
1948 return 0;
1949 }
1950
1951 static int kvm_get_sregs(X86CPU *cpu)
1952 {
1953 CPUX86State *env = &cpu->env;
1954 struct kvm_sregs sregs;
1955 int bit, i, ret;
1956
1957 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1958 if (ret < 0) {
1959 return ret;
1960 }
1961
1962 /* There can only be one pending IRQ set in the bitmap at a time, so try
1963 to find it and save its number instead (-1 for none). */
1964 env->interrupt_injected = -1;
1965 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1966 if (sregs.interrupt_bitmap[i]) {
1967 bit = ctz64(sregs.interrupt_bitmap[i]);
1968 env->interrupt_injected = i * 64 + bit;
1969 break;
1970 }
1971 }
1972
1973 get_seg(&env->segs[R_CS], &sregs.cs);
1974 get_seg(&env->segs[R_DS], &sregs.ds);
1975 get_seg(&env->segs[R_ES], &sregs.es);
1976 get_seg(&env->segs[R_FS], &sregs.fs);
1977 get_seg(&env->segs[R_GS], &sregs.gs);
1978 get_seg(&env->segs[R_SS], &sregs.ss);
1979
1980 get_seg(&env->tr, &sregs.tr);
1981 get_seg(&env->ldt, &sregs.ldt);
1982
1983 env->idt.limit = sregs.idt.limit;
1984 env->idt.base = sregs.idt.base;
1985 env->gdt.limit = sregs.gdt.limit;
1986 env->gdt.base = sregs.gdt.base;
1987
1988 env->cr[0] = sregs.cr0;
1989 env->cr[2] = sregs.cr2;
1990 env->cr[3] = sregs.cr3;
1991 env->cr[4] = sregs.cr4;
1992
1993 env->efer = sregs.efer;
1994
1995 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1996 x86_update_hflags(env);
1997
1998 return 0;
1999 }
2000
2001 static int kvm_get_msrs(X86CPU *cpu)
2002 {
2003 CPUX86State *env = &cpu->env;
2004 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2005 int ret, i;
2006 uint64_t mtrr_top_bits;
2007
2008 kvm_msr_buf_reset(cpu);
2009
2010 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2011 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2012 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2013 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2014 if (has_msr_star) {
2015 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2016 }
2017 if (has_msr_hsave_pa) {
2018 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2019 }
2020 if (has_msr_tsc_aux) {
2021 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2022 }
2023 if (has_msr_tsc_adjust) {
2024 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2025 }
2026 if (has_msr_tsc_deadline) {
2027 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2028 }
2029 if (has_msr_misc_enable) {
2030 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2031 }
2032 if (has_msr_smbase) {
2033 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2034 }
2035 if (has_msr_smi_count) {
2036 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2037 }
2038 if (has_msr_feature_control) {
2039 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2040 }
2041 if (has_msr_bndcfgs) {
2042 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2043 }
2044 if (has_msr_xss) {
2045 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2046 }
2047 if (has_msr_spec_ctrl) {
2048 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2049 }
2050
2051
2052 if (!env->tsc_valid) {
2053 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2054 env->tsc_valid = !runstate_is_running();
2055 }
2056
2057 #ifdef TARGET_X86_64
2058 if (lm_capable_kernel) {
2059 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2060 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2061 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2062 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2063 }
2064 #endif
2065 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2066 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2067 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2068 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2069 }
2070 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2071 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2072 }
2073 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2074 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2075 }
2076 if (has_architectural_pmu_version > 0) {
2077 if (has_architectural_pmu_version > 1) {
2078 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2079 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2080 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2081 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2082 }
2083 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2084 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2085 }
2086 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2087 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2088 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2089 }
2090 }
2091
2092 if (env->mcg_cap) {
2093 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2094 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2095 if (has_msr_mcg_ext_ctl) {
2096 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2097 }
2098 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2099 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2100 }
2101 }
2102
2103 if (has_msr_hv_hypercall) {
2104 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2105 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2106 }
2107 if (cpu->hyperv_vapic) {
2108 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2109 }
2110 if (cpu->hyperv_time) {
2111 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2112 }
2113 if (has_msr_hv_crash) {
2114 int j;
2115
2116 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2117 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2118 }
2119 }
2120 if (has_msr_hv_runtime) {
2121 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2122 }
2123 if (cpu->hyperv_synic) {
2124 uint32_t msr;
2125
2126 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2127 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2128 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2129 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2130 kvm_msr_entry_add(cpu, msr, 0);
2131 }
2132 }
2133 if (has_msr_hv_stimer) {
2134 uint32_t msr;
2135
2136 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2137 msr++) {
2138 kvm_msr_entry_add(cpu, msr, 0);
2139 }
2140 }
2141 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2142 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2143 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2144 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2145 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2146 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2147 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2148 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2149 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2150 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2151 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2152 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2153 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2154 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2155 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2156 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2157 }
2158 }
2159
2160 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2161 int addr_num =
2162 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2163
2164 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2165 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2166 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2167 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2168 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2169 for (i = 0; i < addr_num; i++) {
2170 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2171 }
2172 }
2173
2174 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2175 if (ret < 0) {
2176 return ret;
2177 }
2178
2179 if (ret < cpu->kvm_msr_buf->nmsrs) {
2180 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2181 error_report("error: failed to get MSR 0x%" PRIx32,
2182 (uint32_t)e->index);
2183 }
2184
2185 assert(ret == cpu->kvm_msr_buf->nmsrs);
2186 /*
2187 * MTRR masks: Each mask consists of 5 parts
2188 * a 10..0: must be zero
2189 * b 11 : valid bit
2190 * c n-1.12: actual mask bits
2191 * d 51..n: reserved must be zero
2192 * e 63.52: reserved must be zero
2193 *
2194 * 'n' is the number of physical bits supported by the CPU and is
2195 * apparently always <= 52. We know our 'n' but don't know what
2196 * the destinations 'n' is; it might be smaller, in which case
2197 * it masks (c) on loading. It might be larger, in which case
2198 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2199 * we're migrating to.
2200 */
2201
2202 if (cpu->fill_mtrr_mask) {
2203 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2204 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2205 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2206 } else {
2207 mtrr_top_bits = 0;
2208 }
2209
2210 for (i = 0; i < ret; i++) {
2211 uint32_t index = msrs[i].index;
2212 switch (index) {
2213 case MSR_IA32_SYSENTER_CS:
2214 env->sysenter_cs = msrs[i].data;
2215 break;
2216 case MSR_IA32_SYSENTER_ESP:
2217 env->sysenter_esp = msrs[i].data;
2218 break;
2219 case MSR_IA32_SYSENTER_EIP:
2220 env->sysenter_eip = msrs[i].data;
2221 break;
2222 case MSR_PAT:
2223 env->pat = msrs[i].data;
2224 break;
2225 case MSR_STAR:
2226 env->star = msrs[i].data;
2227 break;
2228 #ifdef TARGET_X86_64
2229 case MSR_CSTAR:
2230 env->cstar = msrs[i].data;
2231 break;
2232 case MSR_KERNELGSBASE:
2233 env->kernelgsbase = msrs[i].data;
2234 break;
2235 case MSR_FMASK:
2236 env->fmask = msrs[i].data;
2237 break;
2238 case MSR_LSTAR:
2239 env->lstar = msrs[i].data;
2240 break;
2241 #endif
2242 case MSR_IA32_TSC:
2243 env->tsc = msrs[i].data;
2244 break;
2245 case MSR_TSC_AUX:
2246 env->tsc_aux = msrs[i].data;
2247 break;
2248 case MSR_TSC_ADJUST:
2249 env->tsc_adjust = msrs[i].data;
2250 break;
2251 case MSR_IA32_TSCDEADLINE:
2252 env->tsc_deadline = msrs[i].data;
2253 break;
2254 case MSR_VM_HSAVE_PA:
2255 env->vm_hsave = msrs[i].data;
2256 break;
2257 case MSR_KVM_SYSTEM_TIME:
2258 env->system_time_msr = msrs[i].data;
2259 break;
2260 case MSR_KVM_WALL_CLOCK:
2261 env->wall_clock_msr = msrs[i].data;
2262 break;
2263 case MSR_MCG_STATUS:
2264 env->mcg_status = msrs[i].data;
2265 break;
2266 case MSR_MCG_CTL:
2267 env->mcg_ctl = msrs[i].data;
2268 break;
2269 case MSR_MCG_EXT_CTL:
2270 env->mcg_ext_ctl = msrs[i].data;
2271 break;
2272 case MSR_IA32_MISC_ENABLE:
2273 env->msr_ia32_misc_enable = msrs[i].data;
2274 break;
2275 case MSR_IA32_SMBASE:
2276 env->smbase = msrs[i].data;
2277 break;
2278 case MSR_SMI_COUNT:
2279 env->msr_smi_count = msrs[i].data;
2280 break;
2281 case MSR_IA32_FEATURE_CONTROL:
2282 env->msr_ia32_feature_control = msrs[i].data;
2283 break;
2284 case MSR_IA32_BNDCFGS:
2285 env->msr_bndcfgs = msrs[i].data;
2286 break;
2287 case MSR_IA32_XSS:
2288 env->xss = msrs[i].data;
2289 break;
2290 default:
2291 if (msrs[i].index >= MSR_MC0_CTL &&
2292 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2293 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2294 }
2295 break;
2296 case MSR_KVM_ASYNC_PF_EN:
2297 env->async_pf_en_msr = msrs[i].data;
2298 break;
2299 case MSR_KVM_PV_EOI_EN:
2300 env->pv_eoi_en_msr = msrs[i].data;
2301 break;
2302 case MSR_KVM_STEAL_TIME:
2303 env->steal_time_msr = msrs[i].data;
2304 break;
2305 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2306 env->msr_fixed_ctr_ctrl = msrs[i].data;
2307 break;
2308 case MSR_CORE_PERF_GLOBAL_CTRL:
2309 env->msr_global_ctrl = msrs[i].data;
2310 break;
2311 case MSR_CORE_PERF_GLOBAL_STATUS:
2312 env->msr_global_status = msrs[i].data;
2313 break;
2314 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2315 env->msr_global_ovf_ctrl = msrs[i].data;
2316 break;
2317 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2318 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2319 break;
2320 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2321 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2322 break;
2323 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2324 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2325 break;
2326 case HV_X64_MSR_HYPERCALL:
2327 env->msr_hv_hypercall = msrs[i].data;
2328 break;
2329 case HV_X64_MSR_GUEST_OS_ID:
2330 env->msr_hv_guest_os_id = msrs[i].data;
2331 break;
2332 case HV_X64_MSR_APIC_ASSIST_PAGE:
2333 env->msr_hv_vapic = msrs[i].data;
2334 break;
2335 case HV_X64_MSR_REFERENCE_TSC:
2336 env->msr_hv_tsc = msrs[i].data;
2337 break;
2338 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2339 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2340 break;
2341 case HV_X64_MSR_VP_RUNTIME:
2342 env->msr_hv_runtime = msrs[i].data;
2343 break;
2344 case HV_X64_MSR_SCONTROL:
2345 env->msr_hv_synic_control = msrs[i].data;
2346 break;
2347 case HV_X64_MSR_SIEFP:
2348 env->msr_hv_synic_evt_page = msrs[i].data;
2349 break;
2350 case HV_X64_MSR_SIMP:
2351 env->msr_hv_synic_msg_page = msrs[i].data;
2352 break;
2353 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2354 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2355 break;
2356 case HV_X64_MSR_STIMER0_CONFIG:
2357 case HV_X64_MSR_STIMER1_CONFIG:
2358 case HV_X64_MSR_STIMER2_CONFIG:
2359 case HV_X64_MSR_STIMER3_CONFIG:
2360 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2361 msrs[i].data;
2362 break;
2363 case HV_X64_MSR_STIMER0_COUNT:
2364 case HV_X64_MSR_STIMER1_COUNT:
2365 case HV_X64_MSR_STIMER2_COUNT:
2366 case HV_X64_MSR_STIMER3_COUNT:
2367 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2368 msrs[i].data;
2369 break;
2370 case MSR_MTRRdefType:
2371 env->mtrr_deftype = msrs[i].data;
2372 break;
2373 case MSR_MTRRfix64K_00000:
2374 env->mtrr_fixed[0] = msrs[i].data;
2375 break;
2376 case MSR_MTRRfix16K_80000:
2377 env->mtrr_fixed[1] = msrs[i].data;
2378 break;
2379 case MSR_MTRRfix16K_A0000:
2380 env->mtrr_fixed[2] = msrs[i].data;
2381 break;
2382 case MSR_MTRRfix4K_C0000:
2383 env->mtrr_fixed[3] = msrs[i].data;
2384 break;
2385 case MSR_MTRRfix4K_C8000:
2386 env->mtrr_fixed[4] = msrs[i].data;
2387 break;
2388 case MSR_MTRRfix4K_D0000:
2389 env->mtrr_fixed[5] = msrs[i].data;
2390 break;
2391 case MSR_MTRRfix4K_D8000:
2392 env->mtrr_fixed[6] = msrs[i].data;
2393 break;
2394 case MSR_MTRRfix4K_E0000:
2395 env->mtrr_fixed[7] = msrs[i].data;
2396 break;
2397 case MSR_MTRRfix4K_E8000:
2398 env->mtrr_fixed[8] = msrs[i].data;
2399 break;
2400 case MSR_MTRRfix4K_F0000:
2401 env->mtrr_fixed[9] = msrs[i].data;
2402 break;
2403 case MSR_MTRRfix4K_F8000:
2404 env->mtrr_fixed[10] = msrs[i].data;
2405 break;
2406 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2407 if (index & 1) {
2408 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2409 mtrr_top_bits;
2410 } else {
2411 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2412 }
2413 break;
2414 case MSR_IA32_SPEC_CTRL:
2415 env->spec_ctrl = msrs[i].data;
2416 break;
2417 case MSR_IA32_RTIT_CTL:
2418 env->msr_rtit_ctrl = msrs[i].data;
2419 break;
2420 case MSR_IA32_RTIT_STATUS:
2421 env->msr_rtit_status = msrs[i].data;
2422 break;
2423 case MSR_IA32_RTIT_OUTPUT_BASE:
2424 env->msr_rtit_output_base = msrs[i].data;
2425 break;
2426 case MSR_IA32_RTIT_OUTPUT_MASK:
2427 env->msr_rtit_output_mask = msrs[i].data;
2428 break;
2429 case MSR_IA32_RTIT_CR3_MATCH:
2430 env->msr_rtit_cr3_match = msrs[i].data;
2431 break;
2432 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2433 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2434 break;
2435 }
2436 }
2437
2438 return 0;
2439 }
2440
2441 static int kvm_put_mp_state(X86CPU *cpu)
2442 {
2443 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2444
2445 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2446 }
2447
2448 static int kvm_get_mp_state(X86CPU *cpu)
2449 {
2450 CPUState *cs = CPU(cpu);
2451 CPUX86State *env = &cpu->env;
2452 struct kvm_mp_state mp_state;
2453 int ret;
2454
2455 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2456 if (ret < 0) {
2457 return ret;
2458 }
2459 env->mp_state = mp_state.mp_state;
2460 if (kvm_irqchip_in_kernel()) {
2461 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2462 }
2463 return 0;
2464 }
2465
2466 static int kvm_get_apic(X86CPU *cpu)
2467 {
2468 DeviceState *apic = cpu->apic_state;
2469 struct kvm_lapic_state kapic;
2470 int ret;
2471
2472 if (apic && kvm_irqchip_in_kernel()) {
2473 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2474 if (ret < 0) {
2475 return ret;
2476 }
2477
2478 kvm_get_apic_state(apic, &kapic);
2479 }
2480 return 0;
2481 }
2482
2483 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2484 {
2485 CPUState *cs = CPU(cpu);
2486 CPUX86State *env = &cpu->env;
2487 struct kvm_vcpu_events events = {};
2488
2489 if (!kvm_has_vcpu_events()) {
2490 return 0;
2491 }
2492
2493 events.exception.injected = (env->exception_injected >= 0);
2494 events.exception.nr = env->exception_injected;
2495 events.exception.has_error_code = env->has_error_code;
2496 events.exception.error_code = env->error_code;
2497 events.exception.pad = 0;
2498
2499 events.interrupt.injected = (env->interrupt_injected >= 0);
2500 events.interrupt.nr = env->interrupt_injected;
2501 events.interrupt.soft = env->soft_interrupt;
2502
2503 events.nmi.injected = env->nmi_injected;
2504 events.nmi.pending = env->nmi_pending;
2505 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2506 events.nmi.pad = 0;
2507
2508 events.sipi_vector = env->sipi_vector;
2509 events.flags = 0;
2510
2511 if (has_msr_smbase) {
2512 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2513 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2514 if (kvm_irqchip_in_kernel()) {
2515 /* As soon as these are moved to the kernel, remove them
2516 * from cs->interrupt_request.
2517 */
2518 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2519 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2520 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2521 } else {
2522 /* Keep these in cs->interrupt_request. */
2523 events.smi.pending = 0;
2524 events.smi.latched_init = 0;
2525 }
2526 /* Stop SMI delivery on old machine types to avoid a reboot
2527 * on an inward migration of an old VM.
2528 */
2529 if (!cpu->kvm_no_smi_migration) {
2530 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2531 }
2532 }
2533
2534 if (level >= KVM_PUT_RESET_STATE) {
2535 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2536 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2537 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2538 }
2539 }
2540
2541 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2542 }
2543
2544 static int kvm_get_vcpu_events(X86CPU *cpu)
2545 {
2546 CPUX86State *env = &cpu->env;
2547 struct kvm_vcpu_events events;
2548 int ret;
2549
2550 if (!kvm_has_vcpu_events()) {
2551 return 0;
2552 }
2553
2554 memset(&events, 0, sizeof(events));
2555 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2556 if (ret < 0) {
2557 return ret;
2558 }
2559 env->exception_injected =
2560 events.exception.injected ? events.exception.nr : -1;
2561 env->has_error_code = events.exception.has_error_code;
2562 env->error_code = events.exception.error_code;
2563
2564 env->interrupt_injected =
2565 events.interrupt.injected ? events.interrupt.nr : -1;
2566 env->soft_interrupt = events.interrupt.soft;
2567
2568 env->nmi_injected = events.nmi.injected;
2569 env->nmi_pending = events.nmi.pending;
2570 if (events.nmi.masked) {
2571 env->hflags2 |= HF2_NMI_MASK;
2572 } else {
2573 env->hflags2 &= ~HF2_NMI_MASK;
2574 }
2575
2576 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2577 if (events.smi.smm) {
2578 env->hflags |= HF_SMM_MASK;
2579 } else {
2580 env->hflags &= ~HF_SMM_MASK;
2581 }
2582 if (events.smi.pending) {
2583 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2584 } else {
2585 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2586 }
2587 if (events.smi.smm_inside_nmi) {
2588 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2589 } else {
2590 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2591 }
2592 if (events.smi.latched_init) {
2593 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2594 } else {
2595 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2596 }
2597 }
2598
2599 env->sipi_vector = events.sipi_vector;
2600
2601 return 0;
2602 }
2603
2604 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2605 {
2606 CPUState *cs = CPU(cpu);
2607 CPUX86State *env = &cpu->env;
2608 int ret = 0;
2609 unsigned long reinject_trap = 0;
2610
2611 if (!kvm_has_vcpu_events()) {
2612 if (env->exception_injected == 1) {
2613 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2614 } else if (env->exception_injected == 3) {
2615 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2616 }
2617 env->exception_injected = -1;
2618 }
2619
2620 /*
2621 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2622 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2623 * by updating the debug state once again if single-stepping is on.
2624 * Another reason to call kvm_update_guest_debug here is a pending debug
2625 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2626 * reinject them via SET_GUEST_DEBUG.
2627 */
2628 if (reinject_trap ||
2629 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2630 ret = kvm_update_guest_debug(cs, reinject_trap);
2631 }
2632 return ret;
2633 }
2634
2635 static int kvm_put_debugregs(X86CPU *cpu)
2636 {
2637 CPUX86State *env = &cpu->env;
2638 struct kvm_debugregs dbgregs;
2639 int i;
2640
2641 if (!kvm_has_debugregs()) {
2642 return 0;
2643 }
2644
2645 for (i = 0; i < 4; i++) {
2646 dbgregs.db[i] = env->dr[i];
2647 }
2648 dbgregs.dr6 = env->dr[6];
2649 dbgregs.dr7 = env->dr[7];
2650 dbgregs.flags = 0;
2651
2652 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2653 }
2654
2655 static int kvm_get_debugregs(X86CPU *cpu)
2656 {
2657 CPUX86State *env = &cpu->env;
2658 struct kvm_debugregs dbgregs;
2659 int i, ret;
2660
2661 if (!kvm_has_debugregs()) {
2662 return 0;
2663 }
2664
2665 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2666 if (ret < 0) {
2667 return ret;
2668 }
2669 for (i = 0; i < 4; i++) {
2670 env->dr[i] = dbgregs.db[i];
2671 }
2672 env->dr[4] = env->dr[6] = dbgregs.dr6;
2673 env->dr[5] = env->dr[7] = dbgregs.dr7;
2674
2675 return 0;
2676 }
2677
2678 int kvm_arch_put_registers(CPUState *cpu, int level)
2679 {
2680 X86CPU *x86_cpu = X86_CPU(cpu);
2681 int ret;
2682
2683 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2684
2685 if (level >= KVM_PUT_RESET_STATE) {
2686 ret = kvm_put_msr_feature_control(x86_cpu);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 }
2691
2692 if (level == KVM_PUT_FULL_STATE) {
2693 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2694 * because TSC frequency mismatch shouldn't abort migration,
2695 * unless the user explicitly asked for a more strict TSC
2696 * setting (e.g. using an explicit "tsc-freq" option).
2697 */
2698 kvm_arch_set_tsc_khz(cpu);
2699 }
2700
2701 ret = kvm_getput_regs(x86_cpu, 1);
2702 if (ret < 0) {
2703 return ret;
2704 }
2705 ret = kvm_put_xsave(x86_cpu);
2706 if (ret < 0) {
2707 return ret;
2708 }
2709 ret = kvm_put_xcrs(x86_cpu);
2710 if (ret < 0) {
2711 return ret;
2712 }
2713 ret = kvm_put_sregs(x86_cpu);
2714 if (ret < 0) {
2715 return ret;
2716 }
2717 /* must be before kvm_put_msrs */
2718 ret = kvm_inject_mce_oldstyle(x86_cpu);
2719 if (ret < 0) {
2720 return ret;
2721 }
2722 ret = kvm_put_msrs(x86_cpu, level);
2723 if (ret < 0) {
2724 return ret;
2725 }
2726 ret = kvm_put_vcpu_events(x86_cpu, level);
2727 if (ret < 0) {
2728 return ret;
2729 }
2730 if (level >= KVM_PUT_RESET_STATE) {
2731 ret = kvm_put_mp_state(x86_cpu);
2732 if (ret < 0) {
2733 return ret;
2734 }
2735 }
2736
2737 ret = kvm_put_tscdeadline_msr(x86_cpu);
2738 if (ret < 0) {
2739 return ret;
2740 }
2741 ret = kvm_put_debugregs(x86_cpu);
2742 if (ret < 0) {
2743 return ret;
2744 }
2745 /* must be last */
2746 ret = kvm_guest_debug_workarounds(x86_cpu);
2747 if (ret < 0) {
2748 return ret;
2749 }
2750 return 0;
2751 }
2752
2753 int kvm_arch_get_registers(CPUState *cs)
2754 {
2755 X86CPU *cpu = X86_CPU(cs);
2756 int ret;
2757
2758 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2759
2760 ret = kvm_get_vcpu_events(cpu);
2761 if (ret < 0) {
2762 goto out;
2763 }
2764 /*
2765 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2766 * KVM_GET_REGS and KVM_GET_SREGS.
2767 */
2768 ret = kvm_get_mp_state(cpu);
2769 if (ret < 0) {
2770 goto out;
2771 }
2772 ret = kvm_getput_regs(cpu, 0);
2773 if (ret < 0) {
2774 goto out;
2775 }
2776 ret = kvm_get_xsave(cpu);
2777 if (ret < 0) {
2778 goto out;
2779 }
2780 ret = kvm_get_xcrs(cpu);
2781 if (ret < 0) {
2782 goto out;
2783 }
2784 ret = kvm_get_sregs(cpu);
2785 if (ret < 0) {
2786 goto out;
2787 }
2788 ret = kvm_get_msrs(cpu);
2789 if (ret < 0) {
2790 goto out;
2791 }
2792 ret = kvm_get_apic(cpu);
2793 if (ret < 0) {
2794 goto out;
2795 }
2796 ret = kvm_get_debugregs(cpu);
2797 if (ret < 0) {
2798 goto out;
2799 }
2800 ret = 0;
2801 out:
2802 cpu_sync_bndcs_hflags(&cpu->env);
2803 return ret;
2804 }
2805
2806 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2807 {
2808 X86CPU *x86_cpu = X86_CPU(cpu);
2809 CPUX86State *env = &x86_cpu->env;
2810 int ret;
2811
2812 /* Inject NMI */
2813 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2814 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2815 qemu_mutex_lock_iothread();
2816 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2817 qemu_mutex_unlock_iothread();
2818 DPRINTF("injected NMI\n");
2819 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2820 if (ret < 0) {
2821 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2822 strerror(-ret));
2823 }
2824 }
2825 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2826 qemu_mutex_lock_iothread();
2827 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2828 qemu_mutex_unlock_iothread();
2829 DPRINTF("injected SMI\n");
2830 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2831 if (ret < 0) {
2832 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2833 strerror(-ret));
2834 }
2835 }
2836 }
2837
2838 if (!kvm_pic_in_kernel()) {
2839 qemu_mutex_lock_iothread();
2840 }
2841
2842 /* Force the VCPU out of its inner loop to process any INIT requests
2843 * or (for userspace APIC, but it is cheap to combine the checks here)
2844 * pending TPR access reports.
2845 */
2846 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2847 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2848 !(env->hflags & HF_SMM_MASK)) {
2849 cpu->exit_request = 1;
2850 }
2851 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2852 cpu->exit_request = 1;
2853 }
2854 }
2855
2856 if (!kvm_pic_in_kernel()) {
2857 /* Try to inject an interrupt if the guest can accept it */
2858 if (run->ready_for_interrupt_injection &&
2859 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2860 (env->eflags & IF_MASK)) {
2861 int irq;
2862
2863 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2864 irq = cpu_get_pic_interrupt(env);
2865 if (irq >= 0) {
2866 struct kvm_interrupt intr;
2867
2868 intr.irq = irq;
2869 DPRINTF("injected interrupt %d\n", irq);
2870 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2871 if (ret < 0) {
2872 fprintf(stderr,
2873 "KVM: injection failed, interrupt lost (%s)\n",
2874 strerror(-ret));
2875 }
2876 }
2877 }
2878
2879 /* If we have an interrupt but the guest is not ready to receive an
2880 * interrupt, request an interrupt window exit. This will
2881 * cause a return to userspace as soon as the guest is ready to
2882 * receive interrupts. */
2883 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2884 run->request_interrupt_window = 1;
2885 } else {
2886 run->request_interrupt_window = 0;
2887 }
2888
2889 DPRINTF("setting tpr\n");
2890 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2891
2892 qemu_mutex_unlock_iothread();
2893 }
2894 }
2895
2896 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2897 {
2898 X86CPU *x86_cpu = X86_CPU(cpu);
2899 CPUX86State *env = &x86_cpu->env;
2900
2901 if (run->flags & KVM_RUN_X86_SMM) {
2902 env->hflags |= HF_SMM_MASK;
2903 } else {
2904 env->hflags &= ~HF_SMM_MASK;
2905 }
2906 if (run->if_flag) {
2907 env->eflags |= IF_MASK;
2908 } else {
2909 env->eflags &= ~IF_MASK;
2910 }
2911
2912 /* We need to protect the apic state against concurrent accesses from
2913 * different threads in case the userspace irqchip is used. */
2914 if (!kvm_irqchip_in_kernel()) {
2915 qemu_mutex_lock_iothread();
2916 }
2917 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2918 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2919 if (!kvm_irqchip_in_kernel()) {
2920 qemu_mutex_unlock_iothread();
2921 }
2922 return cpu_get_mem_attrs(env);
2923 }
2924
2925 int kvm_arch_process_async_events(CPUState *cs)
2926 {
2927 X86CPU *cpu = X86_CPU(cs);
2928 CPUX86State *env = &cpu->env;
2929
2930 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2931 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2932 assert(env->mcg_cap);
2933
2934 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2935
2936 kvm_cpu_synchronize_state(cs);
2937
2938 if (env->exception_injected == EXCP08_DBLE) {
2939 /* this means triple fault */
2940 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2941 cs->exit_request = 1;
2942 return 0;
2943 }
2944 env->exception_injected = EXCP12_MCHK;
2945 env->has_error_code = 0;
2946
2947 cs->halted = 0;
2948 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2949 env->mp_state = KVM_MP_STATE_RUNNABLE;
2950 }
2951 }
2952
2953 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2954 !(env->hflags & HF_SMM_MASK)) {
2955 kvm_cpu_synchronize_state(cs);
2956 do_cpu_init(cpu);
2957 }
2958
2959 if (kvm_irqchip_in_kernel()) {
2960 return 0;
2961 }
2962
2963 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2964 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2965 apic_poll_irq(cpu->apic_state);
2966 }
2967 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2968 (env->eflags & IF_MASK)) ||
2969 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2970 cs->halted = 0;
2971 }
2972 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2973 kvm_cpu_synchronize_state(cs);
2974 do_cpu_sipi(cpu);
2975 }
2976 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2977 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2978 kvm_cpu_synchronize_state(cs);
2979 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2980 env->tpr_access_type);
2981 }
2982
2983 return cs->halted;
2984 }
2985
2986 static int kvm_handle_halt(X86CPU *cpu)
2987 {
2988 CPUState *cs = CPU(cpu);
2989 CPUX86State *env = &cpu->env;
2990
2991 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2992 (env->eflags & IF_MASK)) &&
2993 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2994 cs->halted = 1;
2995 return EXCP_HLT;
2996 }
2997
2998 return 0;
2999 }
3000
3001 static int kvm_handle_tpr_access(X86CPU *cpu)
3002 {
3003 CPUState *cs = CPU(cpu);
3004 struct kvm_run *run = cs->kvm_run;
3005
3006 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3007 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3008 : TPR_ACCESS_READ);
3009 return 1;
3010 }
3011
3012 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3013 {
3014 static const uint8_t int3 = 0xcc;
3015
3016 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3017 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3018 return -EINVAL;
3019 }
3020 return 0;
3021 }
3022
3023 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3024 {
3025 uint8_t int3;
3026
3027 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3028 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3029 return -EINVAL;
3030 }
3031 return 0;
3032 }
3033
3034 static struct {
3035 target_ulong addr;
3036 int len;
3037 int type;
3038 } hw_breakpoint[4];
3039
3040 static int nb_hw_breakpoint;
3041
3042 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3043 {
3044 int n;
3045
3046 for (n = 0; n < nb_hw_breakpoint; n++) {
3047 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3048 (hw_breakpoint[n].len == len || len == -1)) {
3049 return n;
3050 }
3051 }
3052 return -1;
3053 }
3054
3055 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3056 target_ulong len, int type)
3057 {
3058 switch (type) {
3059 case GDB_BREAKPOINT_HW:
3060 len = 1;
3061 break;
3062 case GDB_WATCHPOINT_WRITE:
3063 case GDB_WATCHPOINT_ACCESS:
3064 switch (len) {
3065 case 1:
3066 break;
3067 case 2:
3068 case 4:
3069 case 8:
3070 if (addr & (len - 1)) {
3071 return -EINVAL;
3072 }
3073 break;
3074 default:
3075 return -EINVAL;
3076 }
3077 break;
3078 default:
3079 return -ENOSYS;
3080 }
3081
3082 if (nb_hw_breakpoint == 4) {
3083 return -ENOBUFS;
3084 }
3085 if (find_hw_breakpoint(addr, len, type) >= 0) {
3086 return -EEXIST;
3087 }
3088 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3089 hw_breakpoint[nb_hw_breakpoint].len = len;
3090 hw_breakpoint[nb_hw_breakpoint].type = type;
3091 nb_hw_breakpoint++;
3092
3093 return 0;
3094 }
3095
3096 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3097 target_ulong len, int type)
3098 {
3099 int n;
3100
3101 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3102 if (n < 0) {
3103 return -ENOENT;
3104 }
3105 nb_hw_breakpoint--;
3106 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3107
3108 return 0;
3109 }
3110
3111 void kvm_arch_remove_all_hw_breakpoints(void)
3112 {
3113 nb_hw_breakpoint = 0;
3114 }
3115
3116 static CPUWatchpoint hw_watchpoint;
3117
3118 static int kvm_handle_debug(X86CPU *cpu,
3119 struct kvm_debug_exit_arch *arch_info)
3120 {
3121 CPUState *cs = CPU(cpu);
3122 CPUX86State *env = &cpu->env;
3123 int ret = 0;
3124 int n;
3125
3126 if (arch_info->exception == 1) {
3127 if (arch_info->dr6 & (1 << 14)) {
3128 if (cs->singlestep_enabled) {
3129 ret = EXCP_DEBUG;
3130 }
3131 } else {
3132 for (n = 0; n < 4; n++) {
3133 if (arch_info->dr6 & (1 << n)) {
3134 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3135 case 0x0:
3136 ret = EXCP_DEBUG;
3137 break;
3138 case 0x1:
3139 ret = EXCP_DEBUG;
3140 cs->watchpoint_hit = &hw_watchpoint;
3141 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3142 hw_watchpoint.flags = BP_MEM_WRITE;
3143 break;
3144 case 0x3:
3145 ret = EXCP_DEBUG;
3146 cs->watchpoint_hit = &hw_watchpoint;
3147 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3148 hw_watchpoint.flags = BP_MEM_ACCESS;
3149 break;
3150 }
3151 }
3152 }
3153 }
3154 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3155 ret = EXCP_DEBUG;
3156 }
3157 if (ret == 0) {
3158 cpu_synchronize_state(cs);
3159 assert(env->exception_injected == -1);
3160
3161 /* pass to guest */
3162 env->exception_injected = arch_info->exception;
3163 env->has_error_code = 0;
3164 }
3165
3166 return ret;
3167 }
3168
3169 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3170 {
3171 const uint8_t type_code[] = {
3172 [GDB_BREAKPOINT_HW] = 0x0,
3173 [GDB_WATCHPOINT_WRITE] = 0x1,
3174 [GDB_WATCHPOINT_ACCESS] = 0x3
3175 };
3176 const uint8_t len_code[] = {
3177 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3178 };
3179 int n;
3180
3181 if (kvm_sw_breakpoints_active(cpu)) {
3182 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3183 }
3184 if (nb_hw_breakpoint > 0) {
3185 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3186 dbg->arch.debugreg[7] = 0x0600;
3187 for (n = 0; n < nb_hw_breakpoint; n++) {
3188 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3189 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3190 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3191 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3192 }
3193 }
3194 }
3195
3196 static bool host_supports_vmx(void)
3197 {
3198 uint32_t ecx, unused;
3199
3200 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3201 return ecx & CPUID_EXT_VMX;
3202 }
3203
3204 #define VMX_INVALID_GUEST_STATE 0x80000021
3205
3206 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3207 {
3208 X86CPU *cpu = X86_CPU(cs);
3209 uint64_t code;
3210 int ret;
3211
3212 switch (run->exit_reason) {
3213 case KVM_EXIT_HLT:
3214 DPRINTF("handle_hlt\n");
3215 qemu_mutex_lock_iothread();
3216 ret = kvm_handle_halt(cpu);
3217 qemu_mutex_unlock_iothread();
3218 break;
3219 case KVM_EXIT_SET_TPR:
3220 ret = 0;
3221 break;
3222 case KVM_EXIT_TPR_ACCESS:
3223 qemu_mutex_lock_iothread();
3224 ret = kvm_handle_tpr_access(cpu);
3225 qemu_mutex_unlock_iothread();
3226 break;
3227 case KVM_EXIT_FAIL_ENTRY:
3228 code = run->fail_entry.hardware_entry_failure_reason;
3229 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3230 code);
3231 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3232 fprintf(stderr,
3233 "\nIf you're running a guest on an Intel machine without "
3234 "unrestricted mode\n"
3235 "support, the failure can be most likely due to the guest "
3236 "entering an invalid\n"
3237 "state for Intel VT. For example, the guest maybe running "
3238 "in big real mode\n"
3239 "which is not supported on less recent Intel processors."
3240 "\n\n");
3241 }
3242 ret = -1;
3243 break;
3244 case KVM_EXIT_EXCEPTION:
3245 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3246 run->ex.exception, run->ex.error_code);
3247 ret = -1;
3248 break;
3249 case KVM_EXIT_DEBUG:
3250 DPRINTF("kvm_exit_debug\n");
3251 qemu_mutex_lock_iothread();
3252 ret = kvm_handle_debug(cpu, &run->debug.arch);
3253 qemu_mutex_unlock_iothread();
3254 break;
3255 case KVM_EXIT_HYPERV:
3256 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3257 break;
3258 case KVM_EXIT_IOAPIC_EOI:
3259 ioapic_eoi_broadcast(run->eoi.vector);
3260 ret = 0;
3261 break;
3262 default:
3263 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3264 ret = -1;
3265 break;
3266 }
3267
3268 return ret;
3269 }
3270
3271 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3272 {
3273 X86CPU *cpu = X86_CPU(cs);
3274 CPUX86State *env = &cpu->env;
3275
3276 kvm_cpu_synchronize_state(cs);
3277 return !(env->cr[0] & CR0_PE_MASK) ||
3278 ((env->segs[R_CS].selector & 3) != 3);
3279 }
3280
3281 void kvm_arch_init_irq_routing(KVMState *s)
3282 {
3283 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3284 /* If kernel can't do irq routing, interrupt source
3285 * override 0->2 cannot be set up as required by HPET.
3286 * So we have to disable it.
3287 */
3288 no_hpet = 1;
3289 }
3290 /* We know at this point that we're using the in-kernel
3291 * irqchip, so we can use irqfds, and on x86 we know
3292 * we can use msi via irqfd and GSI routing.
3293 */
3294 kvm_msi_via_irqfd_allowed = true;
3295 kvm_gsi_routing_allowed = true;
3296
3297 if (kvm_irqchip_is_split()) {
3298 int i;
3299
3300 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3301 MSI routes for signaling interrupts to the local apics. */
3302 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3303 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3304 error_report("Could not enable split IRQ mode.");
3305 exit(1);
3306 }
3307 }
3308 }
3309 }
3310
3311 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3312 {
3313 int ret;
3314 if (machine_kernel_irqchip_split(ms)) {
3315 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3316 if (ret) {
3317 error_report("Could not enable split irqchip mode: %s",
3318 strerror(-ret));
3319 exit(1);
3320 } else {
3321 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3322 kvm_split_irqchip = true;
3323 return 1;
3324 }
3325 } else {
3326 return 0;
3327 }
3328 }
3329
3330 /* Classic KVM device assignment interface. Will remain x86 only. */
3331 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3332 uint32_t flags, uint32_t *dev_id)
3333 {
3334 struct kvm_assigned_pci_dev dev_data = {
3335 .segnr = dev_addr->domain,
3336 .busnr = dev_addr->bus,
3337 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3338 .flags = flags,
3339 };
3340 int ret;
3341
3342 dev_data.assigned_dev_id =
3343 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3344
3345 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3346 if (ret < 0) {
3347 return ret;
3348 }
3349
3350 *dev_id = dev_data.assigned_dev_id;
3351
3352 return 0;
3353 }
3354
3355 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3356 {
3357 struct kvm_assigned_pci_dev dev_data = {
3358 .assigned_dev_id = dev_id,
3359 };
3360
3361 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3362 }
3363
3364 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3365 uint32_t irq_type, uint32_t guest_irq)
3366 {
3367 struct kvm_assigned_irq assigned_irq = {
3368 .assigned_dev_id = dev_id,
3369 .guest_irq = guest_irq,
3370 .flags = irq_type,
3371 };
3372
3373 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3374 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3375 } else {
3376 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3377 }
3378 }
3379
3380 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3381 uint32_t guest_irq)
3382 {
3383 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3384 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3385
3386 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3387 }
3388
3389 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3390 {
3391 struct kvm_assigned_pci_dev dev_data = {
3392 .assigned_dev_id = dev_id,
3393 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3394 };
3395
3396 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3397 }
3398
3399 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3400 uint32_t type)
3401 {
3402 struct kvm_assigned_irq assigned_irq = {
3403 .assigned_dev_id = dev_id,
3404 .flags = type,
3405 };
3406
3407 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3408 }
3409
3410 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3411 {
3412 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3413 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3414 }
3415
3416 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3417 {
3418 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3419 KVM_DEV_IRQ_GUEST_MSI, virq);
3420 }
3421
3422 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3423 {
3424 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3425 KVM_DEV_IRQ_HOST_MSI);
3426 }
3427
3428 bool kvm_device_msix_supported(KVMState *s)
3429 {
3430 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3431 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3432 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3433 }
3434
3435 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3436 uint32_t nr_vectors)
3437 {
3438 struct kvm_assigned_msix_nr msix_nr = {
3439 .assigned_dev_id = dev_id,
3440 .entry_nr = nr_vectors,
3441 };
3442
3443 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3444 }
3445
3446 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3447 int virq)
3448 {
3449 struct kvm_assigned_msix_entry msix_entry = {
3450 .assigned_dev_id = dev_id,
3451 .gsi = virq,
3452 .entry = vector,
3453 };
3454
3455 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3456 }
3457
3458 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3459 {
3460 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3461 KVM_DEV_IRQ_GUEST_MSIX, 0);
3462 }
3463
3464 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3465 {
3466 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3467 KVM_DEV_IRQ_HOST_MSIX);
3468 }
3469
3470 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3471 uint64_t address, uint32_t data, PCIDevice *dev)
3472 {
3473 X86IOMMUState *iommu = x86_iommu_get_default();
3474
3475 if (iommu) {
3476 int ret;
3477 MSIMessage src, dst;
3478 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3479
3480 src.address = route->u.msi.address_hi;
3481 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3482 src.address |= route->u.msi.address_lo;
3483 src.data = route->u.msi.data;
3484
3485 ret = class->int_remap(iommu, &src, &dst, dev ? \
3486 pci_requester_id(dev) : \
3487 X86_IOMMU_SID_INVALID);
3488 if (ret) {
3489 trace_kvm_x86_fixup_msi_error(route->gsi);
3490 return 1;
3491 }
3492
3493 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3494 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3495 route->u.msi.data = dst.data;
3496 }
3497
3498 return 0;
3499 }
3500
3501 typedef struct MSIRouteEntry MSIRouteEntry;
3502
3503 struct MSIRouteEntry {
3504 PCIDevice *dev; /* Device pointer */
3505 int vector; /* MSI/MSIX vector index */
3506 int virq; /* Virtual IRQ index */
3507 QLIST_ENTRY(MSIRouteEntry) list;
3508 };
3509
3510 /* List of used GSI routes */
3511 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3512 QLIST_HEAD_INITIALIZER(msi_route_list);
3513
3514 static void kvm_update_msi_routes_all(void *private, bool global,
3515 uint32_t index, uint32_t mask)
3516 {
3517 int cnt = 0;
3518 MSIRouteEntry *entry;
3519 MSIMessage msg;
3520 PCIDevice *dev;
3521
3522 /* TODO: explicit route update */
3523 QLIST_FOREACH(entry, &msi_route_list, list) {
3524 cnt++;
3525 dev = entry->dev;
3526 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3527 continue;
3528 }
3529 msg = pci_get_msi_message(dev, entry->vector);
3530 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3531 }
3532 kvm_irqchip_commit_routes(kvm_state);
3533 trace_kvm_x86_update_msi_routes(cnt);
3534 }
3535
3536 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3537 int vector, PCIDevice *dev)
3538 {
3539 static bool notify_list_inited = false;
3540 MSIRouteEntry *entry;
3541
3542 if (!dev) {
3543 /* These are (possibly) IOAPIC routes only used for split
3544 * kernel irqchip mode, while what we are housekeeping are
3545 * PCI devices only. */
3546 return 0;
3547 }
3548
3549 entry = g_new0(MSIRouteEntry, 1);
3550 entry->dev = dev;
3551 entry->vector = vector;
3552 entry->virq = route->gsi;
3553 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3554
3555 trace_kvm_x86_add_msi_route(route->gsi);
3556
3557 if (!notify_list_inited) {
3558 /* For the first time we do add route, add ourselves into
3559 * IOMMU's IEC notify list if needed. */
3560 X86IOMMUState *iommu = x86_iommu_get_default();
3561 if (iommu) {
3562 x86_iommu_iec_register_notifier(iommu,
3563 kvm_update_msi_routes_all,
3564 NULL);
3565 }
3566 notify_list_inited = true;
3567 }
3568 return 0;
3569 }
3570
3571 int kvm_arch_release_virq_post(int virq)
3572 {
3573 MSIRouteEntry *entry, *next;
3574 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3575 if (entry->virq == virq) {
3576 trace_kvm_x86_remove_msi_route(virq);
3577 QLIST_REMOVE(entry, list);
3578 g_free(entry);
3579 break;
3580 }
3581 }
3582 return 0;
3583 }
3584
3585 int kvm_arch_msi_data_to_gsi(uint32_t data)
3586 {
3587 abort();
3588 }
QEmu