2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/i2c/ppc4xx_i2c.h"
33 #include "hw/qdev-properties.h"
35 #include "hw/char/serial.h"
36 #include "qemu/timer.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/address-spaces.h"
40 #include "hw/intc/ppc-uic.h"
41 #include "hw/qdev-properties.h"
42 #include "qapi/error.h"
45 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t
*bd
,
48 memset(bd
, 0, sizeof(*bd
));
50 bd
->bi_memstart
= PPC405EP_SDRAM_BASE
;
51 bd
->bi_memsize
= ram_size
;
52 bd
->bi_sramstart
= PPC405EP_SRAM_BASE
;
53 bd
->bi_sramsize
= PPC405EP_SRAM_SIZE
;
55 bd
->bi_intfreq
= 133333333;
56 bd
->bi_busfreq
= 33333333;
57 bd
->bi_baudrate
= 115200;
58 bd
->bi_s_version
[0] = 'Q';
59 bd
->bi_s_version
[1] = 'M';
60 bd
->bi_s_version
[2] = 'U';
61 bd
->bi_s_version
[3] = '\0';
62 bd
->bi_r_version
[0] = 'Q';
63 bd
->bi_r_version
[1] = 'E';
64 bd
->bi_r_version
[2] = 'M';
65 bd
->bi_r_version
[3] = 'U';
66 bd
->bi_r_version
[4] = '\0';
67 bd
->bi_procfreq
= 133333333;
68 bd
->bi_plb_busfreq
= 33333333;
69 bd
->bi_pci_busfreq
= 33333333;
70 bd
->bi_opbfreq
= 33333333;
73 static ram_addr_t
__ppc405_set_bootinfo(CPUPPCState
*env
, ppc4xx_bd_info_t
*bd
)
75 CPUState
*cs
= env_cpu(env
);
79 /* We put the bd structure at the top of memory */
80 if (bd
->bi_memsize
>= 0x01000000UL
)
81 bdloc
= 0x01000000UL
- sizeof(struct ppc4xx_bd_info_t
);
83 bdloc
= bd
->bi_memsize
- sizeof(struct ppc4xx_bd_info_t
);
84 stl_be_phys(cs
->as
, bdloc
+ 0x00, bd
->bi_memstart
);
85 stl_be_phys(cs
->as
, bdloc
+ 0x04, bd
->bi_memsize
);
86 stl_be_phys(cs
->as
, bdloc
+ 0x08, bd
->bi_flashstart
);
87 stl_be_phys(cs
->as
, bdloc
+ 0x0C, bd
->bi_flashsize
);
88 stl_be_phys(cs
->as
, bdloc
+ 0x10, bd
->bi_flashoffset
);
89 stl_be_phys(cs
->as
, bdloc
+ 0x14, bd
->bi_sramstart
);
90 stl_be_phys(cs
->as
, bdloc
+ 0x18, bd
->bi_sramsize
);
91 stl_be_phys(cs
->as
, bdloc
+ 0x1C, bd
->bi_bootflags
);
92 stl_be_phys(cs
->as
, bdloc
+ 0x20, bd
->bi_ipaddr
);
93 for (i
= 0; i
< 6; i
++) {
94 stb_phys(cs
->as
, bdloc
+ 0x24 + i
, bd
->bi_enetaddr
[i
]);
96 stw_be_phys(cs
->as
, bdloc
+ 0x2A, bd
->bi_ethspeed
);
97 stl_be_phys(cs
->as
, bdloc
+ 0x2C, bd
->bi_intfreq
);
98 stl_be_phys(cs
->as
, bdloc
+ 0x30, bd
->bi_busfreq
);
99 stl_be_phys(cs
->as
, bdloc
+ 0x34, bd
->bi_baudrate
);
100 for (i
= 0; i
< 4; i
++) {
101 stb_phys(cs
->as
, bdloc
+ 0x38 + i
, bd
->bi_s_version
[i
]);
103 for (i
= 0; i
< 32; i
++) {
104 stb_phys(cs
->as
, bdloc
+ 0x3C + i
, bd
->bi_r_version
[i
]);
106 stl_be_phys(cs
->as
, bdloc
+ 0x5C, bd
->bi_procfreq
);
107 stl_be_phys(cs
->as
, bdloc
+ 0x60, bd
->bi_plb_busfreq
);
108 stl_be_phys(cs
->as
, bdloc
+ 0x64, bd
->bi_pci_busfreq
);
109 for (i
= 0; i
< 6; i
++) {
110 stb_phys(cs
->as
, bdloc
+ 0x68 + i
, bd
->bi_pci_enetaddr
[i
]);
112 n
= 0x70; /* includes 2 bytes hole */
113 for (i
= 0; i
< 6; i
++) {
114 stb_phys(cs
->as
, bdloc
+ n
++, bd
->bi_pci_enetaddr2
[i
]);
116 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_opbfreq
);
118 for (i
= 0; i
< 2; i
++) {
119 stl_be_phys(cs
->as
, bdloc
+ n
, bd
->bi_iic_fast
[i
]);
126 ram_addr_t
ppc405_set_bootinfo(CPUPPCState
*env
, ram_addr_t ram_size
)
130 memset(&bd
, 0, sizeof(bd
));
132 ppc405_set_default_bootinfo(&bd
, ram_size
);
134 return __ppc405_set_bootinfo(env
, &bd
);
137 /*****************************************************************************/
138 /* Shared peripherals */
140 /*****************************************************************************/
141 /* Peripheral local bus arbitrer */
151 typedef struct ppc4xx_plb_t ppc4xx_plb_t
;
152 struct ppc4xx_plb_t
{
158 static uint32_t dcr_read_plb (void *opaque
, int dcrn
)
175 /* Avoid gcc warning */
183 static void dcr_write_plb (void *opaque
, int dcrn
, uint32_t val
)
190 /* We don't care about the actual parameters written as
191 * we don't manage any priorities on the bus
193 plb
->acr
= val
& 0xF8000000;
205 static void ppc4xx_plb_reset (void *opaque
)
210 plb
->acr
= 0x00000000;
211 plb
->bear
= 0x00000000;
212 plb
->besr
= 0x00000000;
215 void ppc4xx_plb_init(CPUPPCState
*env
)
219 plb
= g_new0(ppc4xx_plb_t
, 1);
220 ppc_dcr_register(env
, PLB3A0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
221 ppc_dcr_register(env
, PLB4A0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
222 ppc_dcr_register(env
, PLB0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
223 ppc_dcr_register(env
, PLB0_BEAR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
224 ppc_dcr_register(env
, PLB0_BESR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
225 ppc_dcr_register(env
, PLB4A1_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
226 qemu_register_reset(ppc4xx_plb_reset
, plb
);
229 /*****************************************************************************/
230 /* PLB to OPB bridge */
237 typedef struct ppc4xx_pob_t ppc4xx_pob_t
;
238 struct ppc4xx_pob_t
{
244 static uint32_t dcr_read_pob (void *opaque
, int dcrn
)
261 /* Avoid gcc warning */
269 static void dcr_write_pob (void *opaque
, int dcrn
, uint32_t val
)
289 static void ppc4xx_pob_reset (void *opaque
)
295 pob
->bear
= 0x00000000;
296 pob
->besr0
= 0x0000000;
297 pob
->besr1
= 0x0000000;
300 static void ppc4xx_pob_init(CPUPPCState
*env
)
304 pob
= g_new0(ppc4xx_pob_t
, 1);
305 ppc_dcr_register(env
, POB0_BEAR
, pob
, &dcr_read_pob
, &dcr_write_pob
);
306 ppc_dcr_register(env
, POB0_BESR0
, pob
, &dcr_read_pob
, &dcr_write_pob
);
307 ppc_dcr_register(env
, POB0_BESR1
, pob
, &dcr_read_pob
, &dcr_write_pob
);
308 qemu_register_reset(ppc4xx_pob_reset
, pob
);
311 /*****************************************************************************/
313 typedef struct ppc4xx_opba_t ppc4xx_opba_t
;
314 struct ppc4xx_opba_t
{
320 static uint64_t opba_readb(void *opaque
, hwaddr addr
, unsigned size
)
322 ppc4xx_opba_t
*opba
= opaque
;
337 trace_opba_readb(addr
, ret
);
341 static void opba_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
344 ppc4xx_opba_t
*opba
= opaque
;
346 trace_opba_writeb(addr
, value
);
350 opba
->cr
= value
& 0xF8;
353 opba
->pr
= value
& 0xFF;
359 static const MemoryRegionOps opba_ops
= {
361 .write
= opba_writeb
,
362 .impl
.min_access_size
= 1,
363 .impl
.max_access_size
= 1,
364 .valid
.min_access_size
= 1,
365 .valid
.max_access_size
= 4,
366 .endianness
= DEVICE_BIG_ENDIAN
,
369 static void ppc4xx_opba_reset (void *opaque
)
374 opba
->cr
= 0x00; /* No dynamic priorities - park disabled */
378 static void ppc4xx_opba_init(hwaddr base
)
382 trace_opba_init(base
);
384 opba
= g_new0(ppc4xx_opba_t
, 1);
385 memory_region_init_io(&opba
->io
, NULL
, &opba_ops
, opba
, "opba", 0x002);
386 memory_region_add_subregion(get_system_memory(), base
, &opba
->io
);
387 qemu_register_reset(ppc4xx_opba_reset
, opba
);
390 /*****************************************************************************/
391 /* Code decompression controller */
394 /*****************************************************************************/
395 /* Peripheral controller */
396 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t
;
397 struct ppc4xx_ebc_t
{
408 EBC0_CFGADDR
= 0x012,
409 EBC0_CFGDATA
= 0x013,
412 static uint32_t dcr_read_ebc (void *opaque
, int dcrn
)
424 case 0x00: /* B0CR */
427 case 0x01: /* B1CR */
430 case 0x02: /* B2CR */
433 case 0x03: /* B3CR */
436 case 0x04: /* B4CR */
439 case 0x05: /* B5CR */
442 case 0x06: /* B6CR */
445 case 0x07: /* B7CR */
448 case 0x10: /* B0AP */
451 case 0x11: /* B1AP */
454 case 0x12: /* B2AP */
457 case 0x13: /* B3AP */
460 case 0x14: /* B4AP */
463 case 0x15: /* B5AP */
466 case 0x16: /* B6AP */
469 case 0x17: /* B7AP */
472 case 0x20: /* BEAR */
475 case 0x21: /* BESR0 */
478 case 0x22: /* BESR1 */
497 static void dcr_write_ebc (void *opaque
, int dcrn
, uint32_t val
)
508 case 0x00: /* B0CR */
510 case 0x01: /* B1CR */
512 case 0x02: /* B2CR */
514 case 0x03: /* B3CR */
516 case 0x04: /* B4CR */
518 case 0x05: /* B5CR */
520 case 0x06: /* B6CR */
522 case 0x07: /* B7CR */
524 case 0x10: /* B0AP */
526 case 0x11: /* B1AP */
528 case 0x12: /* B2AP */
530 case 0x13: /* B3AP */
532 case 0x14: /* B4AP */
534 case 0x15: /* B5AP */
536 case 0x16: /* B6AP */
538 case 0x17: /* B7AP */
540 case 0x20: /* BEAR */
542 case 0x21: /* BESR0 */
544 case 0x22: /* BESR1 */
557 static void ebc_reset (void *opaque
)
563 ebc
->addr
= 0x00000000;
564 ebc
->bap
[0] = 0x7F8FFE80;
565 ebc
->bcr
[0] = 0xFFE28000;
566 for (i
= 0; i
< 8; i
++) {
567 ebc
->bap
[i
] = 0x00000000;
568 ebc
->bcr
[i
] = 0x00000000;
570 ebc
->besr0
= 0x00000000;
571 ebc
->besr1
= 0x00000000;
572 ebc
->cfg
= 0x80400000;
575 void ppc405_ebc_init(CPUPPCState
*env
)
579 ebc
= g_new0(ppc4xx_ebc_t
, 1);
580 qemu_register_reset(&ebc_reset
, ebc
);
581 ppc_dcr_register(env
, EBC0_CFGADDR
,
582 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
583 ppc_dcr_register(env
, EBC0_CFGDATA
,
584 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
587 /*****************************************************************************/
616 typedef struct ppc405_dma_t ppc405_dma_t
;
617 struct ppc405_dma_t
{
630 static uint32_t dcr_read_dma (void *opaque
, int dcrn
)
635 static void dcr_write_dma (void *opaque
, int dcrn
, uint32_t val
)
639 static void ppc405_dma_reset (void *opaque
)
645 for (i
= 0; i
< 4; i
++) {
646 dma
->cr
[i
] = 0x00000000;
647 dma
->ct
[i
] = 0x00000000;
648 dma
->da
[i
] = 0x00000000;
649 dma
->sa
[i
] = 0x00000000;
650 dma
->sg
[i
] = 0x00000000;
652 dma
->sr
= 0x00000000;
653 dma
->sgc
= 0x00000000;
654 dma
->slp
= 0x7C000000;
655 dma
->pol
= 0x00000000;
658 static void ppc405_dma_init(CPUPPCState
*env
, qemu_irq irqs
[4])
662 dma
= g_new0(ppc405_dma_t
, 1);
663 memcpy(dma
->irqs
, irqs
, 4 * sizeof(qemu_irq
));
664 qemu_register_reset(&ppc405_dma_reset
, dma
);
665 ppc_dcr_register(env
, DMA0_CR0
,
666 dma
, &dcr_read_dma
, &dcr_write_dma
);
667 ppc_dcr_register(env
, DMA0_CT0
,
668 dma
, &dcr_read_dma
, &dcr_write_dma
);
669 ppc_dcr_register(env
, DMA0_DA0
,
670 dma
, &dcr_read_dma
, &dcr_write_dma
);
671 ppc_dcr_register(env
, DMA0_SA0
,
672 dma
, &dcr_read_dma
, &dcr_write_dma
);
673 ppc_dcr_register(env
, DMA0_SG0
,
674 dma
, &dcr_read_dma
, &dcr_write_dma
);
675 ppc_dcr_register(env
, DMA0_CR1
,
676 dma
, &dcr_read_dma
, &dcr_write_dma
);
677 ppc_dcr_register(env
, DMA0_CT1
,
678 dma
, &dcr_read_dma
, &dcr_write_dma
);
679 ppc_dcr_register(env
, DMA0_DA1
,
680 dma
, &dcr_read_dma
, &dcr_write_dma
);
681 ppc_dcr_register(env
, DMA0_SA1
,
682 dma
, &dcr_read_dma
, &dcr_write_dma
);
683 ppc_dcr_register(env
, DMA0_SG1
,
684 dma
, &dcr_read_dma
, &dcr_write_dma
);
685 ppc_dcr_register(env
, DMA0_CR2
,
686 dma
, &dcr_read_dma
, &dcr_write_dma
);
687 ppc_dcr_register(env
, DMA0_CT2
,
688 dma
, &dcr_read_dma
, &dcr_write_dma
);
689 ppc_dcr_register(env
, DMA0_DA2
,
690 dma
, &dcr_read_dma
, &dcr_write_dma
);
691 ppc_dcr_register(env
, DMA0_SA2
,
692 dma
, &dcr_read_dma
, &dcr_write_dma
);
693 ppc_dcr_register(env
, DMA0_SG2
,
694 dma
, &dcr_read_dma
, &dcr_write_dma
);
695 ppc_dcr_register(env
, DMA0_CR3
,
696 dma
, &dcr_read_dma
, &dcr_write_dma
);
697 ppc_dcr_register(env
, DMA0_CT3
,
698 dma
, &dcr_read_dma
, &dcr_write_dma
);
699 ppc_dcr_register(env
, DMA0_DA3
,
700 dma
, &dcr_read_dma
, &dcr_write_dma
);
701 ppc_dcr_register(env
, DMA0_SA3
,
702 dma
, &dcr_read_dma
, &dcr_write_dma
);
703 ppc_dcr_register(env
, DMA0_SG3
,
704 dma
, &dcr_read_dma
, &dcr_write_dma
);
705 ppc_dcr_register(env
, DMA0_SR
,
706 dma
, &dcr_read_dma
, &dcr_write_dma
);
707 ppc_dcr_register(env
, DMA0_SGC
,
708 dma
, &dcr_read_dma
, &dcr_write_dma
);
709 ppc_dcr_register(env
, DMA0_SLP
,
710 dma
, &dcr_read_dma
, &dcr_write_dma
);
711 ppc_dcr_register(env
, DMA0_POL
,
712 dma
, &dcr_read_dma
, &dcr_write_dma
);
715 /*****************************************************************************/
717 typedef struct ppc405_gpio_t ppc405_gpio_t
;
718 struct ppc405_gpio_t
{
733 static uint64_t ppc405_gpio_read(void *opaque
, hwaddr addr
, unsigned size
)
735 trace_ppc405_gpio_read(addr
, size
);
739 static void ppc405_gpio_write(void *opaque
, hwaddr addr
, uint64_t value
,
742 trace_ppc405_gpio_write(addr
, size
, value
);
745 static const MemoryRegionOps ppc405_gpio_ops
= {
746 .read
= ppc405_gpio_read
,
747 .write
= ppc405_gpio_write
,
748 .endianness
= DEVICE_NATIVE_ENDIAN
,
751 static void ppc405_gpio_reset (void *opaque
)
755 static void ppc405_gpio_init(hwaddr base
)
759 trace_ppc405_gpio_init(base
);
761 gpio
= g_new0(ppc405_gpio_t
, 1);
762 memory_region_init_io(&gpio
->io
, NULL
, &ppc405_gpio_ops
, gpio
, "pgio", 0x038);
763 memory_region_add_subregion(get_system_memory(), base
, &gpio
->io
);
764 qemu_register_reset(&ppc405_gpio_reset
, gpio
);
767 /*****************************************************************************/
771 OCM0_ISACNTL
= 0x019,
773 OCM0_DSACNTL
= 0x01B,
776 typedef struct ppc405_ocm_t ppc405_ocm_t
;
777 struct ppc405_ocm_t
{
779 MemoryRegion isarc_ram
;
780 MemoryRegion dsarc_ram
;
787 static void ocm_update_mappings (ppc405_ocm_t
*ocm
,
788 uint32_t isarc
, uint32_t isacntl
,
789 uint32_t dsarc
, uint32_t dsacntl
)
791 trace_ocm_update_mappings(isarc
, isacntl
, dsarc
, dsacntl
, ocm
->isarc
,
792 ocm
->isacntl
, ocm
->dsarc
, ocm
->dsacntl
);
794 if (ocm
->isarc
!= isarc
||
795 (ocm
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
796 if (ocm
->isacntl
& 0x80000000) {
797 /* Unmap previously assigned memory region */
798 trace_ocm_unmap("ISA", ocm
->isarc
);
799 memory_region_del_subregion(get_system_memory(), &ocm
->isarc_ram
);
801 if (isacntl
& 0x80000000) {
802 /* Map new instruction memory region */
803 trace_ocm_map("ISA", isarc
);
804 memory_region_add_subregion(get_system_memory(), isarc
,
808 if (ocm
->dsarc
!= dsarc
||
809 (ocm
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
810 if (ocm
->dsacntl
& 0x80000000) {
811 /* Beware not to unmap the region we just mapped */
812 if (!(isacntl
& 0x80000000) || ocm
->dsarc
!= isarc
) {
813 /* Unmap previously assigned memory region */
814 trace_ocm_unmap("DSA", ocm
->dsarc
);
815 memory_region_del_subregion(get_system_memory(),
819 if (dsacntl
& 0x80000000) {
820 /* Beware not to remap the region we just mapped */
821 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
822 /* Map new data memory region */
823 trace_ocm_map("DSA", dsarc
);
824 memory_region_add_subregion(get_system_memory(), dsarc
,
831 static uint32_t dcr_read_ocm (void *opaque
, int dcrn
)
858 static void dcr_write_ocm (void *opaque
, int dcrn
, uint32_t val
)
861 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
866 isacntl
= ocm
->isacntl
;
867 dsacntl
= ocm
->dsacntl
;
870 isarc
= val
& 0xFC000000;
873 isacntl
= val
& 0xC0000000;
876 isarc
= val
& 0xFC000000;
879 isacntl
= val
& 0xC0000000;
882 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
885 ocm
->isacntl
= isacntl
;
886 ocm
->dsacntl
= dsacntl
;
889 static void ocm_reset (void *opaque
)
892 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
896 isacntl
= 0x00000000;
898 dsacntl
= 0x00000000;
899 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
902 ocm
->isacntl
= isacntl
;
903 ocm
->dsacntl
= dsacntl
;
906 static void ppc405_ocm_init(CPUPPCState
*env
)
910 ocm
= g_new0(ppc405_ocm_t
, 1);
911 /* XXX: Size is 4096 or 0x04000000 */
912 memory_region_init_ram(&ocm
->isarc_ram
, NULL
, "ppc405.ocm", 4 * KiB
,
914 memory_region_init_alias(&ocm
->dsarc_ram
, NULL
, "ppc405.dsarc",
915 &ocm
->isarc_ram
, 0, 4 * KiB
);
916 qemu_register_reset(&ocm_reset
, ocm
);
917 ppc_dcr_register(env
, OCM0_ISARC
,
918 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
919 ppc_dcr_register(env
, OCM0_ISACNTL
,
920 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
921 ppc_dcr_register(env
, OCM0_DSARC
,
922 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
923 ppc_dcr_register(env
, OCM0_DSACNTL
,
924 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
927 /*****************************************************************************/
928 /* General purpose timers */
929 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t
;
930 struct ppc4xx_gpt_t
{
945 static int ppc4xx_gpt_compare (ppc4xx_gpt_t
*gpt
, int n
)
951 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t
*gpt
, int n
, int level
)
956 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t
*gpt
)
962 for (i
= 0; i
< 5; i
++) {
963 if (gpt
->oe
& mask
) {
964 /* Output is enabled */
965 if (ppc4xx_gpt_compare(gpt
, i
)) {
966 /* Comparison is OK */
967 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
);
969 /* Comparison is KO */
970 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
? 0 : 1);
977 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t
*gpt
)
983 for (i
= 0; i
< 5; i
++) {
984 if (gpt
->is
& gpt
->im
& mask
)
985 qemu_irq_raise(gpt
->irqs
[i
]);
987 qemu_irq_lower(gpt
->irqs
[i
]);
992 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t
*gpt
)
997 static uint64_t ppc4xx_gpt_read(void *opaque
, hwaddr addr
, unsigned size
)
999 ppc4xx_gpt_t
*gpt
= opaque
;
1003 trace_ppc4xx_gpt_read(addr
, size
);
1007 /* Time base counter */
1008 ret
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + gpt
->tb_offset
,
1009 gpt
->tb_freq
, NANOSECONDS_PER_SECOND
);
1020 /* Interrupt mask */
1025 /* Interrupt status */
1029 /* Interrupt enable */
1034 idx
= (addr
- 0x80) >> 2;
1035 ret
= gpt
->comp
[idx
];
1039 idx
= (addr
- 0xC0) >> 2;
1040 ret
= gpt
->mask
[idx
];
1050 static void ppc4xx_gpt_write(void *opaque
, hwaddr addr
, uint64_t value
,
1053 ppc4xx_gpt_t
*gpt
= opaque
;
1056 trace_ppc4xx_gpt_write(addr
, size
, value
);
1060 /* Time base counter */
1061 gpt
->tb_offset
= muldiv64(value
, NANOSECONDS_PER_SECOND
, gpt
->tb_freq
)
1062 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1063 ppc4xx_gpt_compute_timer(gpt
);
1067 gpt
->oe
= value
& 0xF8000000;
1068 ppc4xx_gpt_set_outputs(gpt
);
1072 gpt
->ol
= value
& 0xF8000000;
1073 ppc4xx_gpt_set_outputs(gpt
);
1076 /* Interrupt mask */
1077 gpt
->im
= value
& 0x0000F800;
1080 /* Interrupt status set */
1081 gpt
->is
|= value
& 0x0000F800;
1082 ppc4xx_gpt_set_irqs(gpt
);
1085 /* Interrupt status clear */
1086 gpt
->is
&= ~(value
& 0x0000F800);
1087 ppc4xx_gpt_set_irqs(gpt
);
1090 /* Interrupt enable */
1091 gpt
->ie
= value
& 0x0000F800;
1092 ppc4xx_gpt_set_irqs(gpt
);
1096 idx
= (addr
- 0x80) >> 2;
1097 gpt
->comp
[idx
] = value
& 0xF8000000;
1098 ppc4xx_gpt_compute_timer(gpt
);
1102 idx
= (addr
- 0xC0) >> 2;
1103 gpt
->mask
[idx
] = value
& 0xF8000000;
1104 ppc4xx_gpt_compute_timer(gpt
);
1109 static const MemoryRegionOps gpt_ops
= {
1110 .read
= ppc4xx_gpt_read
,
1111 .write
= ppc4xx_gpt_write
,
1112 .valid
.min_access_size
= 4,
1113 .valid
.max_access_size
= 4,
1114 .endianness
= DEVICE_NATIVE_ENDIAN
,
1117 static void ppc4xx_gpt_cb (void *opaque
)
1122 ppc4xx_gpt_set_irqs(gpt
);
1123 ppc4xx_gpt_set_outputs(gpt
);
1124 ppc4xx_gpt_compute_timer(gpt
);
1127 static void ppc4xx_gpt_reset (void *opaque
)
1133 timer_del(gpt
->timer
);
1134 gpt
->oe
= 0x00000000;
1135 gpt
->ol
= 0x00000000;
1136 gpt
->im
= 0x00000000;
1137 gpt
->is
= 0x00000000;
1138 gpt
->ie
= 0x00000000;
1139 for (i
= 0; i
< 5; i
++) {
1140 gpt
->comp
[i
] = 0x00000000;
1141 gpt
->mask
[i
] = 0x00000000;
1145 static void ppc4xx_gpt_init(hwaddr base
, qemu_irq irqs
[5])
1150 trace_ppc4xx_gpt_init(base
);
1152 gpt
= g_new0(ppc4xx_gpt_t
, 1);
1153 for (i
= 0; i
< 5; i
++) {
1154 gpt
->irqs
[i
] = irqs
[i
];
1156 gpt
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &ppc4xx_gpt_cb
, gpt
);
1157 memory_region_init_io(&gpt
->iomem
, NULL
, &gpt_ops
, gpt
, "gpt", 0x0d4);
1158 memory_region_add_subregion(get_system_memory(), base
, &gpt
->iomem
);
1159 qemu_register_reset(ppc4xx_gpt_reset
, gpt
);
1162 /*****************************************************************************/
1166 PPC405EP_CPC0_PLLMR0
= 0x0F0,
1167 PPC405EP_CPC0_BOOT
= 0x0F1,
1168 PPC405EP_CPC0_EPCTL
= 0x0F3,
1169 PPC405EP_CPC0_PLLMR1
= 0x0F4,
1170 PPC405EP_CPC0_UCR
= 0x0F5,
1171 PPC405EP_CPC0_SRR
= 0x0F6,
1172 PPC405EP_CPC0_JTAGID
= 0x0F7,
1173 PPC405EP_CPC0_PCI
= 0x0F9,
1175 PPC405EP_CPC0_ER
= xxx
,
1176 PPC405EP_CPC0_FR
= xxx
,
1177 PPC405EP_CPC0_SR
= xxx
,
1182 PPC405EP_CPU_CLK
= 0,
1183 PPC405EP_PLB_CLK
= 1,
1184 PPC405EP_OPB_CLK
= 2,
1185 PPC405EP_EBC_CLK
= 3,
1186 PPC405EP_MAL_CLK
= 4,
1187 PPC405EP_PCI_CLK
= 5,
1188 PPC405EP_UART0_CLK
= 6,
1189 PPC405EP_UART1_CLK
= 7,
1190 PPC405EP_CLK_NB
= 8,
1193 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t
;
1194 struct ppc405ep_cpc_t
{
1196 clk_setup_t clk_setup
[PPC405EP_CLK_NB
];
1204 /* Clock and power management */
1210 static void ppc405ep_compute_clocks (ppc405ep_cpc_t
*cpc
)
1212 uint32_t CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
;
1213 uint32_t UART0_clk
, UART1_clk
;
1214 uint64_t VCO_out
, PLL_out
;
1218 if ((cpc
->pllmr
[1] & 0x80000000) && !(cpc
->pllmr
[1] & 0x40000000)) {
1219 M
= (((cpc
->pllmr
[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
1220 trace_ppc405ep_clocks_compute("FBMUL", (cpc
->pllmr
[1] >> 20) & 0xF, M
);
1221 D
= 8 - ((cpc
->pllmr
[1] >> 16) & 0x7); /* FWDA */
1222 trace_ppc405ep_clocks_compute("FWDA", (cpc
->pllmr
[1] >> 16) & 0x7, D
);
1223 VCO_out
= (uint64_t)cpc
->sysclk
* M
* D
;
1224 if (VCO_out
< 500000000UL || VCO_out
> 1000000000UL) {
1225 /* Error - unlock the PLL */
1226 qemu_log_mask(LOG_GUEST_ERROR
, "VCO out of range %" PRIu64
"\n",
1229 cpc
->pllmr
[1] &= ~0x80000000;
1233 PLL_out
= VCO_out
/ D
;
1234 /* Pretend the PLL is locked */
1235 cpc
->boot
|= 0x00000001;
1240 PLL_out
= cpc
->sysclk
;
1241 if (cpc
->pllmr
[1] & 0x40000000) {
1242 /* Pretend the PLL is not locked */
1243 cpc
->boot
&= ~0x00000001;
1246 /* Now, compute all other clocks */
1247 D
= ((cpc
->pllmr
[0] >> 20) & 0x3) + 1; /* CCDV */
1248 trace_ppc405ep_clocks_compute("CCDV", (cpc
->pllmr
[0] >> 20) & 0x3, D
);
1249 CPU_clk
= PLL_out
/ D
;
1250 D
= ((cpc
->pllmr
[0] >> 16) & 0x3) + 1; /* CBDV */
1251 trace_ppc405ep_clocks_compute("CBDV", (cpc
->pllmr
[0] >> 16) & 0x3, D
);
1252 PLB_clk
= CPU_clk
/ D
;
1253 D
= ((cpc
->pllmr
[0] >> 12) & 0x3) + 1; /* OPDV */
1254 trace_ppc405ep_clocks_compute("OPDV", (cpc
->pllmr
[0] >> 12) & 0x3, D
);
1255 OPB_clk
= PLB_clk
/ D
;
1256 D
= ((cpc
->pllmr
[0] >> 8) & 0x3) + 2; /* EPDV */
1257 trace_ppc405ep_clocks_compute("EPDV", (cpc
->pllmr
[0] >> 8) & 0x3, D
);
1258 EBC_clk
= PLB_clk
/ D
;
1259 D
= ((cpc
->pllmr
[0] >> 4) & 0x3) + 1; /* MPDV */
1260 trace_ppc405ep_clocks_compute("MPDV", (cpc
->pllmr
[0] >> 4) & 0x3, D
);
1261 MAL_clk
= PLB_clk
/ D
;
1262 D
= (cpc
->pllmr
[0] & 0x3) + 1; /* PPDV */
1263 trace_ppc405ep_clocks_compute("PPDV", cpc
->pllmr
[0] & 0x3, D
);
1264 PCI_clk
= PLB_clk
/ D
;
1265 D
= ((cpc
->ucr
- 1) & 0x7F) + 1; /* U0DIV */
1266 trace_ppc405ep_clocks_compute("U0DIV", cpc
->ucr
& 0x7F, D
);
1267 UART0_clk
= PLL_out
/ D
;
1268 D
= (((cpc
->ucr
>> 8) - 1) & 0x7F) + 1; /* U1DIV */
1269 trace_ppc405ep_clocks_compute("U1DIV", (cpc
->ucr
>> 8) & 0x7F, D
);
1270 UART1_clk
= PLL_out
/ D
;
1272 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP
)) {
1273 g_autofree
char *trace
= g_strdup_printf(
1274 "Setup PPC405EP clocks - sysclk %" PRIu32
" VCO %" PRIu64
1275 " PLL out %" PRIu64
" Hz\n"
1276 "CPU %" PRIu32
" PLB %" PRIu32
" OPB %" PRIu32
" EBC %" PRIu32
1277 " MAL %" PRIu32
" PCI %" PRIu32
" UART0 %" PRIu32
1278 " UART1 %" PRIu32
"\n",
1279 cpc
->sysclk
, VCO_out
, PLL_out
,
1280 CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
,
1281 UART0_clk
, UART1_clk
);
1282 trace_ppc405ep_clocks_setup(trace
);
1285 /* Setup CPU clocks */
1286 clk_setup(&cpc
->clk_setup
[PPC405EP_CPU_CLK
], CPU_clk
);
1287 /* Setup PLB clock */
1288 clk_setup(&cpc
->clk_setup
[PPC405EP_PLB_CLK
], PLB_clk
);
1289 /* Setup OPB clock */
1290 clk_setup(&cpc
->clk_setup
[PPC405EP_OPB_CLK
], OPB_clk
);
1291 /* Setup external clock */
1292 clk_setup(&cpc
->clk_setup
[PPC405EP_EBC_CLK
], EBC_clk
);
1293 /* Setup MAL clock */
1294 clk_setup(&cpc
->clk_setup
[PPC405EP_MAL_CLK
], MAL_clk
);
1295 /* Setup PCI clock */
1296 clk_setup(&cpc
->clk_setup
[PPC405EP_PCI_CLK
], PCI_clk
);
1297 /* Setup UART0 clock */
1298 clk_setup(&cpc
->clk_setup
[PPC405EP_UART0_CLK
], UART0_clk
);
1299 /* Setup UART1 clock */
1300 clk_setup(&cpc
->clk_setup
[PPC405EP_UART1_CLK
], UART1_clk
);
1303 static uint32_t dcr_read_epcpc (void *opaque
, int dcrn
)
1305 ppc405ep_cpc_t
*cpc
;
1310 case PPC405EP_CPC0_BOOT
:
1313 case PPC405EP_CPC0_EPCTL
:
1316 case PPC405EP_CPC0_PLLMR0
:
1317 ret
= cpc
->pllmr
[0];
1319 case PPC405EP_CPC0_PLLMR1
:
1320 ret
= cpc
->pllmr
[1];
1322 case PPC405EP_CPC0_UCR
:
1325 case PPC405EP_CPC0_SRR
:
1328 case PPC405EP_CPC0_JTAGID
:
1331 case PPC405EP_CPC0_PCI
:
1335 /* Avoid gcc warning */
1343 static void dcr_write_epcpc (void *opaque
, int dcrn
, uint32_t val
)
1345 ppc405ep_cpc_t
*cpc
;
1349 case PPC405EP_CPC0_BOOT
:
1350 /* Read-only register */
1352 case PPC405EP_CPC0_EPCTL
:
1353 /* Don't care for now */
1354 cpc
->epctl
= val
& 0xC00000F3;
1356 case PPC405EP_CPC0_PLLMR0
:
1357 cpc
->pllmr
[0] = val
& 0x00633333;
1358 ppc405ep_compute_clocks(cpc
);
1360 case PPC405EP_CPC0_PLLMR1
:
1361 cpc
->pllmr
[1] = val
& 0xC0F73FFF;
1362 ppc405ep_compute_clocks(cpc
);
1364 case PPC405EP_CPC0_UCR
:
1365 /* UART control - don't care for now */
1366 cpc
->ucr
= val
& 0x003F7F7F;
1368 case PPC405EP_CPC0_SRR
:
1371 case PPC405EP_CPC0_JTAGID
:
1374 case PPC405EP_CPC0_PCI
:
1380 static void ppc405ep_cpc_reset (void *opaque
)
1382 ppc405ep_cpc_t
*cpc
= opaque
;
1384 cpc
->boot
= 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
1385 cpc
->epctl
= 0x00000000;
1386 cpc
->pllmr
[0] = 0x00021002;
1387 cpc
->pllmr
[1] = 0x80a552be;
1388 cpc
->ucr
= 0x00004646;
1389 cpc
->srr
= 0x00040000;
1390 cpc
->pci
= 0x00000000;
1391 cpc
->er
= 0x00000000;
1392 cpc
->fr
= 0x00000000;
1393 cpc
->sr
= 0x00000000;
1394 ppc405ep_compute_clocks(cpc
);
1397 /* XXX: sysclk should be between 25 and 100 MHz */
1398 static void ppc405ep_cpc_init (CPUPPCState
*env
, clk_setup_t clk_setup
[8],
1401 ppc405ep_cpc_t
*cpc
;
1403 cpc
= g_new0(ppc405ep_cpc_t
, 1);
1404 memcpy(cpc
->clk_setup
, clk_setup
,
1405 PPC405EP_CLK_NB
* sizeof(clk_setup_t
));
1406 cpc
->jtagid
= 0x20267049;
1407 cpc
->sysclk
= sysclk
;
1408 qemu_register_reset(&ppc405ep_cpc_reset
, cpc
);
1409 ppc_dcr_register(env
, PPC405EP_CPC0_BOOT
, cpc
,
1410 &dcr_read_epcpc
, &dcr_write_epcpc
);
1411 ppc_dcr_register(env
, PPC405EP_CPC0_EPCTL
, cpc
,
1412 &dcr_read_epcpc
, &dcr_write_epcpc
);
1413 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR0
, cpc
,
1414 &dcr_read_epcpc
, &dcr_write_epcpc
);
1415 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR1
, cpc
,
1416 &dcr_read_epcpc
, &dcr_write_epcpc
);
1417 ppc_dcr_register(env
, PPC405EP_CPC0_UCR
, cpc
,
1418 &dcr_read_epcpc
, &dcr_write_epcpc
);
1419 ppc_dcr_register(env
, PPC405EP_CPC0_SRR
, cpc
,
1420 &dcr_read_epcpc
, &dcr_write_epcpc
);
1421 ppc_dcr_register(env
, PPC405EP_CPC0_JTAGID
, cpc
,
1422 &dcr_read_epcpc
, &dcr_write_epcpc
);
1423 ppc_dcr_register(env
, PPC405EP_CPC0_PCI
, cpc
,
1424 &dcr_read_epcpc
, &dcr_write_epcpc
);
1426 ppc_dcr_register(env
, PPC405EP_CPC0_ER
, cpc
,
1427 &dcr_read_epcpc
, &dcr_write_epcpc
);
1428 ppc_dcr_register(env
, PPC405EP_CPC0_FR
, cpc
,
1429 &dcr_read_epcpc
, &dcr_write_epcpc
);
1430 ppc_dcr_register(env
, PPC405EP_CPC0_SR
, cpc
,
1431 &dcr_read_epcpc
, &dcr_write_epcpc
);
1435 static void ppc405_soc_realize(DeviceState
*dev
, Error
**errp
)
1437 Ppc405SoCState
*s
= PPC405_SOC(dev
);
1438 clk_setup_t clk_setup
[PPC405EP_CLK_NB
], tlb_clk_setup
;
1439 qemu_irq dma_irqs
[4], gpt_irqs
[5], mal_irqs
[4];
1442 memset(clk_setup
, 0, sizeof(clk_setup
));
1445 s
->cpu
= ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"),
1446 &clk_setup
[PPC405EP_CPU_CLK
],
1447 &tlb_clk_setup
, s
->sysclk
);
1449 clk_setup
[PPC405EP_CPU_CLK
].cb
= tlb_clk_setup
.cb
;
1450 clk_setup
[PPC405EP_CPU_CLK
].opaque
= tlb_clk_setup
.opaque
;
1453 ppc405ep_cpc_init(env
, clk_setup
, s
->sysclk
);
1456 ppc4xx_plb_init(env
);
1458 /* PLB to OPB bridge */
1459 ppc4xx_pob_init(env
);
1462 ppc4xx_opba_init(0xef600600);
1464 /* Universal interrupt controller */
1465 s
->uic
= qdev_new(TYPE_PPC_UIC
);
1467 object_property_set_link(OBJECT(s
->uic
), "cpu", OBJECT(s
->cpu
),
1469 if (!sysbus_realize(SYS_BUS_DEVICE(s
->uic
), errp
)) {
1473 sysbus_connect_irq(SYS_BUS_DEVICE(s
->uic
), PPCUIC_OUTPUT_INT
,
1474 qdev_get_gpio_in(DEVICE(s
->cpu
), PPC40x_INPUT_INT
));
1475 sysbus_connect_irq(SYS_BUS_DEVICE(s
->uic
), PPCUIC_OUTPUT_CINT
,
1476 qdev_get_gpio_in(DEVICE(s
->cpu
), PPC40x_INPUT_CINT
));
1478 /* SDRAM controller */
1479 /* XXX 405EP has no ECC interrupt */
1480 s
->ram_bases
[0] = 0;
1481 s
->ram_sizes
[0] = s
->ram_size
;
1482 memory_region_init_alias(&s
->ram_banks
[0], OBJECT(s
),
1483 "ppc405.sdram0", s
->dram_mr
,
1484 s
->ram_bases
[0], s
->ram_sizes
[0]);
1486 ppc4xx_sdram_init(env
, qdev_get_gpio_in(s
->uic
, 17), 1,
1487 s
->ram_banks
, s
->ram_bases
, s
->ram_sizes
,
1490 /* External bus controller */
1491 ppc405_ebc_init(env
);
1493 /* DMA controller */
1494 dma_irqs
[0] = qdev_get_gpio_in(s
->uic
, 5);
1495 dma_irqs
[1] = qdev_get_gpio_in(s
->uic
, 6);
1496 dma_irqs
[2] = qdev_get_gpio_in(s
->uic
, 7);
1497 dma_irqs
[3] = qdev_get_gpio_in(s
->uic
, 8);
1498 ppc405_dma_init(env
, dma_irqs
);
1500 /* I2C controller */
1501 sysbus_create_simple(TYPE_PPC4xx_I2C
, 0xef600500,
1502 qdev_get_gpio_in(s
->uic
, 2));
1504 ppc405_gpio_init(0xef600700);
1507 if (serial_hd(0) != NULL
) {
1508 serial_mm_init(get_system_memory(), 0xef600300, 0,
1509 qdev_get_gpio_in(s
->uic
, 0),
1510 PPC_SERIAL_MM_BAUDBASE
, serial_hd(0),
1513 if (serial_hd(1) != NULL
) {
1514 serial_mm_init(get_system_memory(), 0xef600400, 0,
1515 qdev_get_gpio_in(s
->uic
, 1),
1516 PPC_SERIAL_MM_BAUDBASE
, serial_hd(1),
1521 ppc405_ocm_init(env
);
1524 gpt_irqs
[0] = qdev_get_gpio_in(s
->uic
, 19);
1525 gpt_irqs
[1] = qdev_get_gpio_in(s
->uic
, 20);
1526 gpt_irqs
[2] = qdev_get_gpio_in(s
->uic
, 21);
1527 gpt_irqs
[3] = qdev_get_gpio_in(s
->uic
, 22);
1528 gpt_irqs
[4] = qdev_get_gpio_in(s
->uic
, 23);
1529 ppc4xx_gpt_init(0xef600000, gpt_irqs
);
1532 mal_irqs
[0] = qdev_get_gpio_in(s
->uic
, 11);
1533 mal_irqs
[1] = qdev_get_gpio_in(s
->uic
, 12);
1534 mal_irqs
[2] = qdev_get_gpio_in(s
->uic
, 13);
1535 mal_irqs
[3] = qdev_get_gpio_in(s
->uic
, 14);
1536 ppc4xx_mal_init(env
, 4, 2, mal_irqs
);
1539 /* Uses UIC IRQs 9, 15, 17 */
1542 static Property ppc405_soc_properties
[] = {
1543 DEFINE_PROP_LINK("dram", Ppc405SoCState
, dram_mr
, TYPE_MEMORY_REGION
,
1545 DEFINE_PROP_UINT32("sys-clk", Ppc405SoCState
, sysclk
, 0),
1546 DEFINE_PROP_BOOL("dram-init", Ppc405SoCState
, do_dram_init
, 0),
1547 DEFINE_PROP_UINT64("ram-size", Ppc405SoCState
, ram_size
, 0),
1548 DEFINE_PROP_END_OF_LIST(),
1551 static void ppc405_soc_class_init(ObjectClass
*oc
, void *data
)
1553 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1555 dc
->realize
= ppc405_soc_realize
;
1556 /* Reason: only works as part of a ppc405 board/machine */
1557 dc
->user_creatable
= false;
1558 device_class_set_props(dc
, ppc405_soc_properties
);
1561 static const TypeInfo ppc405_types
[] = {
1563 .name
= TYPE_PPC405_SOC
,
1564 .parent
= TYPE_DEVICE
,
1565 .instance_size
= sizeof(Ppc405SoCState
),
1566 .class_init
= ppc405_soc_class_init
,
1570 DEFINE_TYPES(ppc405_types
)