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raw-posix: Use qemu_dup
[qemu.git] / hw / block / m25p80.c
blobca8c12c0f89180a43cf6a2f327de6d91df85b28e
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31 #include "qapi/error.h"
32
33 #ifndef M25P80_ERR_DEBUG
34 #define M25P80_ERR_DEBUG 0
35 #endif
36
37 #define DB_PRINT_L(level, ...) do { \
38 if (M25P80_ERR_DEBUG > (level)) { \
39 fprintf(stderr, ": %s: ", __func__); \
40 fprintf(stderr, ## __VA_ARGS__); \
41 } \
42 } while (0);
43
44 /* Fields for FlashPartInfo->flags */
45
46 /* erase capabilities */
47 #define ER_4K 1
48 #define ER_32K 2
49 /* set to allow the page program command to write 0s back to 1. Useful for
50 * modelling EEPROM with SPI flash command set
51 */
52 #define EEPROM 0x100
53
54 /* 16 MiB max in 3 byte address mode */
55 #define MAX_3BYTES_SIZE 0x1000000
56
57 #define SPI_NOR_MAX_ID_LEN 6
58
59 typedef struct FlashPartInfo {
60 const char *part_name;
61 /*
62 * This array stores the ID bytes.
63 * The first three bytes are the JEDIC ID.
64 * JEDEC ID zero means "no ID" (mostly older chips).
65 */
66 uint8_t id[SPI_NOR_MAX_ID_LEN];
67 uint8_t id_len;
68 /* there is confusion between manufacturers as to what a sector is. In this
69 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
70 * command (opcode 0xd8).
71 */
72 uint32_t sector_size;
73 uint32_t n_sectors;
74 uint32_t page_size;
75 uint16_t flags;
76 } FlashPartInfo;
77
78 /* adapted from linux */
79 /* Used when the "_ext_id" is two bytes at most */
80 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
81 .part_name = _part_name,\
82 .id = {\
83 ((_jedec_id) >> 16) & 0xff,\
84 ((_jedec_id) >> 8) & 0xff,\
85 (_jedec_id) & 0xff,\
86 ((_ext_id) >> 8) & 0xff,\
87 (_ext_id) & 0xff,\
88 },\
89 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
90 .sector_size = (_sector_size),\
91 .n_sectors = (_n_sectors),\
92 .page_size = 256,\
93 .flags = (_flags),
94
95 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
96 .part_name = _part_name,\
97 .id = {\
98 ((_jedec_id) >> 16) & 0xff,\
99 ((_jedec_id) >> 8) & 0xff,\
100 (_jedec_id) & 0xff,\
101 ((_ext_id) >> 16) & 0xff,\
102 ((_ext_id) >> 8) & 0xff,\
103 (_ext_id) & 0xff,\
104 },\
105 .id_len = 6,\
106 .sector_size = (_sector_size),\
107 .n_sectors = (_n_sectors),\
108 .page_size = 256,\
109 .flags = (_flags),\
110
111 #define JEDEC_NUMONYX 0x20
112 #define JEDEC_WINBOND 0xEF
113 #define JEDEC_SPANSION 0x01
114
115 /* Numonyx (Micron) Configuration register macros */
116 #define VCFG_DUMMY 0x1
117 #define VCFG_WRAP_SEQUENTIAL 0x2
118 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
119 #define NVCFG_XIP_MODE_MASK (7 << 9)
120 #define VCFG_XIP_MODE_ENABLED (1 << 3)
121 #define CFG_DUMMY_CLK_LEN 4
122 #define NVCFG_DUMMY_CLK_POS 12
123 #define VCFG_DUMMY_CLK_POS 4
124 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
125 #define EVCFG_VPP_ACCELERATOR (1 << 3)
126 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
127 #define NVCFG_DUAL_IO_MASK (1 << 2)
128 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
129 #define NVCFG_QUAD_IO_MASK (1 << 3)
130 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
131 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
132 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
133
134 /* Numonyx (Micron) Flag Status Register macros */
135 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
136 #define FSR_FLASH_READY (1 << 7)
137
138 /* Spansion configuration registers macros. */
139 #define SPANSION_QUAD_CFG_POS 0
140 #define SPANSION_QUAD_CFG_LEN 1
141 #define SPANSION_DUMMY_CLK_POS 0
142 #define SPANSION_DUMMY_CLK_LEN 4
143 #define SPANSION_ADDR_LEN_POS 7
144 #define SPANSION_ADDR_LEN_LEN 1
145
146 /*
147 * Spansion read mode command length in bytes,
148 * the mode is currently not supported.
149 */
150
151 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
152
153 static const FlashPartInfo known_devices[] = {
154 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
155 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
156 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
157
158 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
159 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
160 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
161
162 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
163 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
164 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
165 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
166
167 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
168
169 /* Atmel EEPROMS - it is assumed, that don't care bit in command
170 * is set to 0. Block protection is not supported.
171 */
172 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
173 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
174
175 /* EON -- en25xxx */
176 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
177 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
178 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
179 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
180 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
181
182 /* GigaDevice */
183 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
184 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
185
186 /* Intel/Numonyx -- xxxs33b */
187 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
188 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
189 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
190 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
191
192 /* Macronix */
193 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
194 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
195 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
196 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
197 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
198 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
199 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
200 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
201 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
202 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
203 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
204 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
205
206 /* Micron */
207 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
208 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
209 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
210 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
211 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
212 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
213 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
214 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
215 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
216 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
217 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
218 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) },
219 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) },
220
221 /* Spansion -- single (large) sector size only, at least
222 * for the chips listed here (without boot sectors).
223 */
224 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
225 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
226 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
227 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
228 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
229 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
230 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
231 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
232 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
233 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
234 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
235 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
236 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
237 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
238 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
239 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
240 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
241
242 /* Spansion -- boot sectors support */
243 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
244 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
245
246 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
247 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
248 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
249 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
250 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
251 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
252 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
253 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
254 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
255 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
256
257 /* ST Microelectronics -- newer production may have feature updates */
258 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
259 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
260 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
261 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
262 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
263 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
264 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
265 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
266 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
267 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
268
269 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
270 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
271 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
272
273 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
274 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
275 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
276
277 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
278 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
279 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
280 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
281
282 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
283 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
284 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
285 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
286 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
287 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
288 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
289 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
290 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
291 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
292 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
293 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
294 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
295 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
296 };
297
298 typedef enum {
299 NOP = 0,
300 WRSR = 0x1,
301 WRDI = 0x4,
302 RDSR = 0x5,
303 WREN = 0x6,
304 JEDEC_READ = 0x9f,
305 BULK_ERASE = 0xc7,
306 READ_FSR = 0x70,
307 RDCR = 0x15,
308
309 READ = 0x03,
310 READ4 = 0x13,
311 FAST_READ = 0x0b,
312 FAST_READ4 = 0x0c,
313 DOR = 0x3b,
314 DOR4 = 0x3c,
315 QOR = 0x6b,
316 QOR4 = 0x6c,
317 DIOR = 0xbb,
318 DIOR4 = 0xbc,
319 QIOR = 0xeb,
320 QIOR4 = 0xec,
321
322 PP = 0x02,
323 PP4 = 0x12,
324 PP4_4 = 0x3e,
325 DPP = 0xa2,
326 QPP = 0x32,
327
328 ERASE_4K = 0x20,
329 ERASE4_4K = 0x21,
330 ERASE_32K = 0x52,
331 ERASE4_32K = 0x5c,
332 ERASE_SECTOR = 0xd8,
333 ERASE4_SECTOR = 0xdc,
334
335 EN_4BYTE_ADDR = 0xB7,
336 EX_4BYTE_ADDR = 0xE9,
337
338 EXTEND_ADDR_READ = 0xC8,
339 EXTEND_ADDR_WRITE = 0xC5,
340
341 RESET_ENABLE = 0x66,
342 RESET_MEMORY = 0x99,
343
344 /*
345 * Micron: 0x35 - enable QPI
346 * Spansion: 0x35 - read control register
347 */
348 RDCR_EQIO = 0x35,
349 RSTQIO = 0xf5,
350
351 RNVCR = 0xB5,
352 WNVCR = 0xB1,
353
354 RVCR = 0x85,
355 WVCR = 0x81,
356
357 REVCR = 0x65,
358 WEVCR = 0x61,
359 } FlashCMD;
360
361 typedef enum {
362 STATE_IDLE,
363 STATE_PAGE_PROGRAM,
364 STATE_READ,
365 STATE_COLLECTING_DATA,
366 STATE_COLLECTING_VAR_LEN_DATA,
367 STATE_READING_DATA,
368 } CMDState;
369
370 typedef enum {
371 MAN_SPANSION,
372 MAN_MACRONIX,
373 MAN_NUMONYX,
374 MAN_WINBOND,
375 MAN_GENERIC,
376 } Manufacturer;
377
378 typedef struct Flash {
379 SSISlave parent_obj;
380
381 BlockBackend *blk;
382
383 uint8_t *storage;
384 uint32_t size;
385 int page_size;
386
387 uint8_t state;
388 uint8_t data[16];
389 uint32_t len;
390 uint32_t pos;
391 uint8_t needed_bytes;
392 uint8_t cmd_in_progress;
393 uint32_t cur_addr;
394 uint32_t nonvolatile_cfg;
395 /* Configuration register for Macronix */
396 uint32_t volatile_cfg;
397 uint32_t enh_volatile_cfg;
398 /* Spansion cfg registers. */
399 uint8_t spansion_cr1nv;
400 uint8_t spansion_cr2nv;
401 uint8_t spansion_cr3nv;
402 uint8_t spansion_cr4nv;
403 uint8_t spansion_cr1v;
404 uint8_t spansion_cr2v;
405 uint8_t spansion_cr3v;
406 uint8_t spansion_cr4v;
407 bool write_enable;
408 bool four_bytes_address_mode;
409 bool reset_enable;
410 bool quad_enable;
411 uint8_t ear;
412
413 int64_t dirty_page;
414
415 const FlashPartInfo *pi;
416
417 } Flash;
418
419 typedef struct M25P80Class {
420 SSISlaveClass parent_class;
421 FlashPartInfo *pi;
422 } M25P80Class;
423
424 #define TYPE_M25P80 "m25p80-generic"
425 #define M25P80(obj) \
426 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
427 #define M25P80_CLASS(klass) \
428 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
429 #define M25P80_GET_CLASS(obj) \
430 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
431
432 static inline Manufacturer get_man(Flash *s)
433 {
434 switch (s->pi->id[0]) {
435 case 0x20:
436 return MAN_NUMONYX;
437 case 0xEF:
438 return MAN_WINBOND;
439 case 0x01:
440 return MAN_SPANSION;
441 case 0xC2:
442 return MAN_MACRONIX;
443 default:
444 return MAN_GENERIC;
445 }
446 }
447
448 static void blk_sync_complete(void *opaque, int ret)
449 {
450 QEMUIOVector *iov = opaque;
451
452 qemu_iovec_destroy(iov);
453 g_free(iov);
454
455 /* do nothing. Masters do not directly interact with the backing store,
456 * only the working copy so no mutexing required.
457 */
458 }
459
460 static void flash_sync_page(Flash *s, int page)
461 {
462 QEMUIOVector *iov;
463
464 if (!s->blk || blk_is_read_only(s->blk)) {
465 return;
466 }
467
468 iov = g_new(QEMUIOVector, 1);
469 qemu_iovec_init(iov, 1);
470 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
471 s->pi->page_size);
472 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
473 blk_sync_complete, iov);
474 }
475
476 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
477 {
478 QEMUIOVector *iov;
479
480 if (!s->blk || blk_is_read_only(s->blk)) {
481 return;
482 }
483
484 assert(!(len % BDRV_SECTOR_SIZE));
485 iov = g_new(QEMUIOVector, 1);
486 qemu_iovec_init(iov, 1);
487 qemu_iovec_add(iov, s->storage + off, len);
488 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
489 }
490
491 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
492 {
493 uint32_t len;
494 uint8_t capa_to_assert = 0;
495
496 switch (cmd) {
497 case ERASE_4K:
498 case ERASE4_4K:
499 len = 4 << 10;
500 capa_to_assert = ER_4K;
501 break;
502 case ERASE_32K:
503 case ERASE4_32K:
504 len = 32 << 10;
505 capa_to_assert = ER_32K;
506 break;
507 case ERASE_SECTOR:
508 case ERASE4_SECTOR:
509 len = s->pi->sector_size;
510 break;
511 case BULK_ERASE:
512 len = s->size;
513 break;
514 default:
515 abort();
516 }
517
518 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
519 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
520 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
521 " device\n", len);
522 }
523
524 if (!s->write_enable) {
525 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
526 return;
527 }
528 memset(s->storage + offset, 0xff, len);
529 flash_sync_area(s, offset, len);
530 }
531
532 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
533 {
534 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
535 flash_sync_page(s, s->dirty_page);
536 s->dirty_page = newpage;
537 }
538 }
539
540 static inline
541 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
542 {
543 uint32_t page = addr / s->pi->page_size;
544 uint8_t prev = s->storage[s->cur_addr];
545
546 if (!s->write_enable) {
547 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
548 }
549
550 if ((prev ^ data) & data) {
551 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
552 " -> %" PRIx8 "\n", addr, prev, data);
553 }
554
555 if (s->pi->flags & EEPROM) {
556 s->storage[s->cur_addr] = data;
557 } else {
558 s->storage[s->cur_addr] &= data;
559 }
560
561 flash_sync_dirty(s, page);
562 s->dirty_page = page;
563 }
564
565 static inline int get_addr_length(Flash *s)
566 {
567 /* check if eeprom is in use */
568 if (s->pi->flags == EEPROM) {
569 return 2;
570 }
571
572 switch (s->cmd_in_progress) {
573 case PP4:
574 case PP4_4:
575 case READ4:
576 case QIOR4:
577 case ERASE4_4K:
578 case ERASE4_32K:
579 case ERASE4_SECTOR:
580 case FAST_READ4:
581 case DOR4:
582 case QOR4:
583 case DIOR4:
584 return 4;
585 default:
586 return s->four_bytes_address_mode ? 4 : 3;
587 }
588 }
589
590 static void complete_collecting_data(Flash *s)
591 {
592 int i, n;
593
594 n = get_addr_length(s);
595 s->cur_addr = (n == 3 ? s->ear : 0);
596 for (i = 0; i < n; ++i) {
597 s->cur_addr <<= 8;
598 s->cur_addr |= s->data[i];
599 }
600
601 s->cur_addr &= s->size - 1;
602
603 s->state = STATE_IDLE;
604
605 switch (s->cmd_in_progress) {
606 case DPP:
607 case QPP:
608 case PP:
609 case PP4:
610 case PP4_4:
611 s->state = STATE_PAGE_PROGRAM;
612 break;
613 case READ:
614 case READ4:
615 case FAST_READ:
616 case FAST_READ4:
617 case DOR:
618 case DOR4:
619 case QOR:
620 case QOR4:
621 case DIOR:
622 case DIOR4:
623 case QIOR:
624 case QIOR4:
625 s->state = STATE_READ;
626 break;
627 case ERASE_4K:
628 case ERASE4_4K:
629 case ERASE_32K:
630 case ERASE4_32K:
631 case ERASE_SECTOR:
632 case ERASE4_SECTOR:
633 flash_erase(s, s->cur_addr, s->cmd_in_progress);
634 break;
635 case WRSR:
636 switch (get_man(s)) {
637 case MAN_SPANSION:
638 s->quad_enable = !!(s->data[1] & 0x02);
639 break;
640 case MAN_MACRONIX:
641 s->quad_enable = extract32(s->data[0], 6, 1);
642 if (s->len > 1) {
643 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
644 }
645 break;
646 default:
647 break;
648 }
649 if (s->write_enable) {
650 s->write_enable = false;
651 }
652 break;
653 case EXTEND_ADDR_WRITE:
654 s->ear = s->data[0];
655 break;
656 case WNVCR:
657 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
658 break;
659 case WVCR:
660 s->volatile_cfg = s->data[0];
661 break;
662 case WEVCR:
663 s->enh_volatile_cfg = s->data[0];
664 break;
665 default:
666 break;
667 }
668 }
669
670 static void reset_memory(Flash *s)
671 {
672 s->cmd_in_progress = NOP;
673 s->cur_addr = 0;
674 s->ear = 0;
675 s->four_bytes_address_mode = false;
676 s->len = 0;
677 s->needed_bytes = 0;
678 s->pos = 0;
679 s->state = STATE_IDLE;
680 s->write_enable = false;
681 s->reset_enable = false;
682 s->quad_enable = false;
683
684 switch (get_man(s)) {
685 case MAN_NUMONYX:
686 s->volatile_cfg = 0;
687 s->volatile_cfg |= VCFG_DUMMY;
688 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
689 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
690 != NVCFG_XIP_MODE_DISABLED) {
691 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
692 }
693 s->volatile_cfg |= deposit32(s->volatile_cfg,
694 VCFG_DUMMY_CLK_POS,
695 CFG_DUMMY_CLK_LEN,
696 extract32(s->nonvolatile_cfg,
697 NVCFG_DUMMY_CLK_POS,
698 CFG_DUMMY_CLK_LEN)
699 );
700
701 s->enh_volatile_cfg = 0;
702 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
703 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
704 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
705 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
706 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
707 }
708 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
709 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
710 }
711 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
712 s->four_bytes_address_mode = true;
713 }
714 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
715 s->ear = s->size / MAX_3BYTES_SIZE - 1;
716 }
717 break;
718 case MAN_MACRONIX:
719 s->volatile_cfg = 0x7;
720 break;
721 case MAN_SPANSION:
722 s->spansion_cr1v = s->spansion_cr1nv;
723 s->spansion_cr2v = s->spansion_cr2nv;
724 s->spansion_cr3v = s->spansion_cr3nv;
725 s->spansion_cr4v = s->spansion_cr4nv;
726 s->quad_enable = extract32(s->spansion_cr1v,
727 SPANSION_QUAD_CFG_POS,
728 SPANSION_QUAD_CFG_LEN
729 );
730 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
731 SPANSION_ADDR_LEN_POS,
732 SPANSION_ADDR_LEN_LEN
733 );
734 break;
735 default:
736 break;
737 }
738
739 DB_PRINT_L(0, "Reset done.\n");
740 }
741
742 static void decode_fast_read_cmd(Flash *s)
743 {
744 s->needed_bytes = get_addr_length(s);
745 switch (get_man(s)) {
746 /* Dummy cycles - modeled with bytes writes instead of bits */
747 case MAN_WINBOND:
748 s->needed_bytes += 8;
749 break;
750 case MAN_NUMONYX:
751 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
752 break;
753 case MAN_MACRONIX:
754 if (extract32(s->volatile_cfg, 6, 2) == 1) {
755 s->needed_bytes += 6;
756 } else {
757 s->needed_bytes += 8;
758 }
759 break;
760 case MAN_SPANSION:
761 s->needed_bytes += extract32(s->spansion_cr2v,
762 SPANSION_DUMMY_CLK_POS,
763 SPANSION_DUMMY_CLK_LEN
764 );
765 break;
766 default:
767 break;
768 }
769 s->pos = 0;
770 s->len = 0;
771 s->state = STATE_COLLECTING_DATA;
772 }
773
774 static void decode_dio_read_cmd(Flash *s)
775 {
776 s->needed_bytes = get_addr_length(s);
777 /* Dummy cycles modeled with bytes writes instead of bits */
778 switch (get_man(s)) {
779 case MAN_WINBOND:
780 s->needed_bytes += 8;
781 break;
782 case MAN_SPANSION:
783 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
784 s->needed_bytes += extract32(s->spansion_cr2v,
785 SPANSION_DUMMY_CLK_POS,
786 SPANSION_DUMMY_CLK_LEN
787 );
788 break;
789 case MAN_NUMONYX:
790 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
791 break;
792 case MAN_MACRONIX:
793 switch (extract32(s->volatile_cfg, 6, 2)) {
794 case 1:
795 s->needed_bytes += 6;
796 break;
797 case 2:
798 s->needed_bytes += 8;
799 break;
800 default:
801 s->needed_bytes += 4;
802 break;
803 }
804 break;
805 default:
806 break;
807 }
808 s->pos = 0;
809 s->len = 0;
810 s->state = STATE_COLLECTING_DATA;
811 }
812
813 static void decode_qio_read_cmd(Flash *s)
814 {
815 s->needed_bytes = get_addr_length(s);
816 /* Dummy cycles modeled with bytes writes instead of bits */
817 switch (get_man(s)) {
818 case MAN_WINBOND:
819 s->needed_bytes += 8;
820 break;
821 case MAN_SPANSION:
822 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
823 s->needed_bytes += extract32(s->spansion_cr2v,
824 SPANSION_DUMMY_CLK_POS,
825 SPANSION_DUMMY_CLK_LEN
826 );
827 break;
828 case MAN_NUMONYX:
829 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
830 break;
831 case MAN_MACRONIX:
832 switch (extract32(s->volatile_cfg, 6, 2)) {
833 case 1:
834 s->needed_bytes += 4;
835 break;
836 case 2:
837 s->needed_bytes += 8;
838 break;
839 default:
840 s->needed_bytes += 6;
841 break;
842 }
843 break;
844 default:
845 break;
846 }
847 s->pos = 0;
848 s->len = 0;
849 s->state = STATE_COLLECTING_DATA;
850 }
851
852 static void decode_new_cmd(Flash *s, uint32_t value)
853 {
854 s->cmd_in_progress = value;
855 int i;
856 DB_PRINT_L(0, "decoded new command:%x\n", value);
857
858 if (value != RESET_MEMORY) {
859 s->reset_enable = false;
860 }
861
862 switch (value) {
863
864 case ERASE_4K:
865 case ERASE4_4K:
866 case ERASE_32K:
867 case ERASE4_32K:
868 case ERASE_SECTOR:
869 case ERASE4_SECTOR:
870 case READ:
871 case READ4:
872 case DPP:
873 case QPP:
874 case PP:
875 case PP4:
876 case PP4_4:
877 s->needed_bytes = get_addr_length(s);
878 s->pos = 0;
879 s->len = 0;
880 s->state = STATE_COLLECTING_DATA;
881 break;
882
883 case FAST_READ:
884 case FAST_READ4:
885 case DOR:
886 case DOR4:
887 case QOR:
888 case QOR4:
889 decode_fast_read_cmd(s);
890 break;
891
892 case DIOR:
893 case DIOR4:
894 decode_dio_read_cmd(s);
895 break;
896
897 case QIOR:
898 case QIOR4:
899 decode_qio_read_cmd(s);
900 break;
901
902 case WRSR:
903 if (s->write_enable) {
904 switch (get_man(s)) {
905 case MAN_SPANSION:
906 s->needed_bytes = 2;
907 s->state = STATE_COLLECTING_DATA;
908 break;
909 case MAN_MACRONIX:
910 s->needed_bytes = 2;
911 s->state = STATE_COLLECTING_VAR_LEN_DATA;
912 break;
913 default:
914 s->needed_bytes = 1;
915 s->state = STATE_COLLECTING_DATA;
916 }
917 s->pos = 0;
918 }
919 break;
920
921 case WRDI:
922 s->write_enable = false;
923 break;
924 case WREN:
925 s->write_enable = true;
926 break;
927
928 case RDSR:
929 s->data[0] = (!!s->write_enable) << 1;
930 if (get_man(s) == MAN_MACRONIX) {
931 s->data[0] |= (!!s->quad_enable) << 6;
932 }
933 s->pos = 0;
934 s->len = 1;
935 s->state = STATE_READING_DATA;
936 break;
937
938 case READ_FSR:
939 s->data[0] = FSR_FLASH_READY;
940 if (s->four_bytes_address_mode) {
941 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
942 }
943 s->pos = 0;
944 s->len = 1;
945 s->state = STATE_READING_DATA;
946 break;
947
948 case JEDEC_READ:
949 DB_PRINT_L(0, "populated jedec code\n");
950 for (i = 0; i < s->pi->id_len; i++) {
951 s->data[i] = s->pi->id[i];
952 }
953
954 s->len = s->pi->id_len;
955 s->pos = 0;
956 s->state = STATE_READING_DATA;
957 break;
958
959 case RDCR:
960 s->data[0] = s->volatile_cfg & 0xFF;
961 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
962 s->pos = 0;
963 s->len = 1;
964 s->state = STATE_READING_DATA;
965 break;
966
967 case BULK_ERASE:
968 if (s->write_enable) {
969 DB_PRINT_L(0, "chip erase\n");
970 flash_erase(s, 0, BULK_ERASE);
971 } else {
972 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
973 "protect!\n");
974 }
975 break;
976 case NOP:
977 break;
978 case EN_4BYTE_ADDR:
979 s->four_bytes_address_mode = true;
980 break;
981 case EX_4BYTE_ADDR:
982 s->four_bytes_address_mode = false;
983 break;
984 case EXTEND_ADDR_READ:
985 s->data[0] = s->ear;
986 s->pos = 0;
987 s->len = 1;
988 s->state = STATE_READING_DATA;
989 break;
990 case EXTEND_ADDR_WRITE:
991 if (s->write_enable) {
992 s->needed_bytes = 1;
993 s->pos = 0;
994 s->len = 0;
995 s->state = STATE_COLLECTING_DATA;
996 }
997 break;
998 case RNVCR:
999 s->data[0] = s->nonvolatile_cfg & 0xFF;
1000 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1001 s->pos = 0;
1002 s->len = 2;
1003 s->state = STATE_READING_DATA;
1004 break;
1005 case WNVCR:
1006 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1007 s->needed_bytes = 2;
1008 s->pos = 0;
1009 s->len = 0;
1010 s->state = STATE_COLLECTING_DATA;
1011 }
1012 break;
1013 case RVCR:
1014 s->data[0] = s->volatile_cfg & 0xFF;
1015 s->pos = 0;
1016 s->len = 1;
1017 s->state = STATE_READING_DATA;
1018 break;
1019 case WVCR:
1020 if (s->write_enable) {
1021 s->needed_bytes = 1;
1022 s->pos = 0;
1023 s->len = 0;
1024 s->state = STATE_COLLECTING_DATA;
1025 }
1026 break;
1027 case REVCR:
1028 s->data[0] = s->enh_volatile_cfg & 0xFF;
1029 s->pos = 0;
1030 s->len = 1;
1031 s->state = STATE_READING_DATA;
1032 break;
1033 case WEVCR:
1034 if (s->write_enable) {
1035 s->needed_bytes = 1;
1036 s->pos = 0;
1037 s->len = 0;
1038 s->state = STATE_COLLECTING_DATA;
1039 }
1040 break;
1041 case RESET_ENABLE:
1042 s->reset_enable = true;
1043 break;
1044 case RESET_MEMORY:
1045 if (s->reset_enable) {
1046 reset_memory(s);
1047 }
1048 break;
1049 case RDCR_EQIO:
1050 switch (get_man(s)) {
1051 case MAN_SPANSION:
1052 s->data[0] = (!!s->quad_enable) << 1;
1053 s->pos = 0;
1054 s->len = 1;
1055 s->state = STATE_READING_DATA;
1056 break;
1057 case MAN_MACRONIX:
1058 s->quad_enable = true;
1059 break;
1060 default:
1061 break;
1062 }
1063 break;
1064 case RSTQIO:
1065 s->quad_enable = false;
1066 break;
1067 default:
1068 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1069 break;
1070 }
1071 }
1072
1073 static int m25p80_cs(SSISlave *ss, bool select)
1074 {
1075 Flash *s = M25P80(ss);
1076
1077 if (select) {
1078 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1079 complete_collecting_data(s);
1080 }
1081 s->len = 0;
1082 s->pos = 0;
1083 s->state = STATE_IDLE;
1084 flash_sync_dirty(s, -1);
1085 }
1086
1087 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1088
1089 return 0;
1090 }
1091
1092 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1093 {
1094 Flash *s = M25P80(ss);
1095 uint32_t r = 0;
1096
1097 switch (s->state) {
1098
1099 case STATE_PAGE_PROGRAM:
1100 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
1101 s->cur_addr, (uint8_t)tx);
1102 flash_write8(s, s->cur_addr, (uint8_t)tx);
1103 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1104 break;
1105
1106 case STATE_READ:
1107 r = s->storage[s->cur_addr];
1108 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
1109 (uint8_t)r);
1110 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1111 break;
1112
1113 case STATE_COLLECTING_DATA:
1114 case STATE_COLLECTING_VAR_LEN_DATA:
1115 s->data[s->len] = (uint8_t)tx;
1116 s->len++;
1117
1118 if (s->len == s->needed_bytes) {
1119 complete_collecting_data(s);
1120 }
1121 break;
1122
1123 case STATE_READING_DATA:
1124 r = s->data[s->pos];
1125 s->pos++;
1126 if (s->pos == s->len) {
1127 s->pos = 0;
1128 s->state = STATE_IDLE;
1129 }
1130 break;
1131
1132 default:
1133 case STATE_IDLE:
1134 decode_new_cmd(s, (uint8_t)tx);
1135 break;
1136 }
1137
1138 return r;
1139 }
1140
1141 static void m25p80_realize(SSISlave *ss, Error **errp)
1142 {
1143 Flash *s = M25P80(ss);
1144 M25P80Class *mc = M25P80_GET_CLASS(s);
1145
1146 s->pi = mc->pi;
1147
1148 s->size = s->pi->sector_size * s->pi->n_sectors;
1149 s->dirty_page = -1;
1150
1151 if (s->blk) {
1152 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1153 s->storage = blk_blockalign(s->blk, s->size);
1154
1155 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1156 error_setg(errp, "failed to read the initial flash content");
1157 return;
1158 }
1159 } else {
1160 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1161 s->storage = blk_blockalign(NULL, s->size);
1162 memset(s->storage, 0xFF, s->size);
1163 }
1164 }
1165
1166 static void m25p80_reset(DeviceState *d)
1167 {
1168 Flash *s = M25P80(d);
1169
1170 reset_memory(s);
1171 }
1172
1173 static void m25p80_pre_save(void *opaque)
1174 {
1175 flash_sync_dirty((Flash *)opaque, -1);
1176 }
1177
1178 static Property m25p80_properties[] = {
1179 /* This is default value for Micron flash */
1180 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1181 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1182 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1183 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1184 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1185 DEFINE_PROP_DRIVE("drive", Flash, blk),
1186 DEFINE_PROP_END_OF_LIST(),
1187 };
1188
1189 static const VMStateDescription vmstate_m25p80 = {
1190 .name = "xilinx_spi",
1191 .version_id = 3,
1192 .minimum_version_id = 1,
1193 .pre_save = m25p80_pre_save,
1194 .fields = (VMStateField[]) {
1195 VMSTATE_UINT8(state, Flash),
1196 VMSTATE_UINT8_ARRAY(data, Flash, 16),
1197 VMSTATE_UINT32(len, Flash),
1198 VMSTATE_UINT32(pos, Flash),
1199 VMSTATE_UINT8(needed_bytes, Flash),
1200 VMSTATE_UINT8(cmd_in_progress, Flash),
1201 VMSTATE_UNUSED(4),
1202 VMSTATE_UINT32(cur_addr, Flash),
1203 VMSTATE_BOOL(write_enable, Flash),
1204 VMSTATE_BOOL_V(reset_enable, Flash, 2),
1205 VMSTATE_UINT8_V(ear, Flash, 2),
1206 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
1207 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
1208 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
1209 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
1210 VMSTATE_BOOL_V(quad_enable, Flash, 3),
1211 VMSTATE_UINT8_V(spansion_cr1nv, Flash, 3),
1212 VMSTATE_UINT8_V(spansion_cr2nv, Flash, 3),
1213 VMSTATE_UINT8_V(spansion_cr3nv, Flash, 3),
1214 VMSTATE_UINT8_V(spansion_cr4nv, Flash, 3),
1215 VMSTATE_END_OF_LIST()
1216 }
1217 };
1218
1219 static void m25p80_class_init(ObjectClass *klass, void *data)
1220 {
1221 DeviceClass *dc = DEVICE_CLASS(klass);
1222 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1223 M25P80Class *mc = M25P80_CLASS(klass);
1224
1225 k->realize = m25p80_realize;
1226 k->transfer = m25p80_transfer8;
1227 k->set_cs = m25p80_cs;
1228 k->cs_polarity = SSI_CS_LOW;
1229 dc->vmsd = &vmstate_m25p80;
1230 dc->props = m25p80_properties;
1231 dc->reset = m25p80_reset;
1232 mc->pi = data;
1233 }
1234
1235 static const TypeInfo m25p80_info = {
1236 .name = TYPE_M25P80,
1237 .parent = TYPE_SSI_SLAVE,
1238 .instance_size = sizeof(Flash),
1239 .class_size = sizeof(M25P80Class),
1240 .abstract = true,
1241 };
1242
1243 static void m25p80_register_types(void)
1244 {
1245 int i;
1246
1247 type_register_static(&m25p80_info);
1248 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1249 TypeInfo ti = {
1250 .name = known_devices[i].part_name,
1251 .parent = TYPE_M25P80,
1252 .class_init = m25p80_class_init,
1253 .class_data = (void *)&known_devices[i],
1254 };
1255 type_register(&ti);
1256 }
1257 }
1258
1259 type_init(m25p80_register_types)
QEmu